macromem.hh revision 7724:ba11187e2582 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_MACROMEM_HH__
43#define __ARCH_ARM_MACROMEM_HH__
44
45#include "arch/arm/insts/pred_inst.hh"
46#include "arch/arm/tlb.hh"
47
48namespace ArmISA
49{
50
51static inline unsigned int
52number_of_ones(int32_t val)
53{
54    uint32_t ones = 0;
55    for (int i = 0; i < 32; i++ )
56    {
57        if ( val & (1<<i) )
58            ones++;
59    }
60    return ones;
61}
62
63/**
64 * Base class for Memory microops
65 */
66class MicroOp : public PredOp
67{
68  protected:
69    MicroOp(const char *mnem, ExtMachInst machInst, OpClass __opClass)
70            : PredOp(mnem, machInst, __opClass)
71    {
72    }
73
74  public:
75    void
76    advancePC(PCState &pcState) const
77    {
78        if (flags[IsLastMicroop]) {
79            pcState.uEnd();
80        } else if (flags[IsMicroop]) {
81            pcState.uAdvance();
82        } else {
83            pcState.advance();
84        }
85    }
86};
87
88/**
89 * Microops for Neon loads/stores
90 */
91class MicroNeonMemOp : public MicroOp
92{
93  protected:
94    RegIndex dest, ura;
95    uint32_t imm;
96    unsigned memAccessFlags;
97
98    MicroNeonMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
99                   RegIndex _dest, RegIndex _ura, uint32_t _imm)
100            : MicroOp(mnem, machInst, __opClass),
101              dest(_dest), ura(_ura), imm(_imm),
102              memAccessFlags(TLB::MustBeOne)
103    {
104    }
105};
106
107/**
108 * Microops for Neon load/store (de)interleaving
109 */
110class MicroNeonMixOp : public MicroOp
111{
112  protected:
113    RegIndex dest, op1;
114    uint32_t step;
115
116    MicroNeonMixOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
117                   RegIndex _dest, RegIndex _op1, uint32_t _step)
118            : MicroOp(mnem, machInst, __opClass),
119              dest(_dest), op1(_op1), step(_step)
120    {
121    }
122};
123
124class MicroNeonMixLaneOp : public MicroNeonMixOp
125{
126  protected:
127    unsigned lane;
128
129    MicroNeonMixLaneOp(const char *mnem, ExtMachInst machInst,
130                       OpClass __opClass, RegIndex _dest, RegIndex _op1,
131                       uint32_t _step, unsigned _lane)
132            : MicroNeonMixOp(mnem, machInst, __opClass, _dest, _op1, _step),
133              lane(_lane)
134    {
135    }
136};
137/**
138 * Microops of the form IntRegA = IntRegB
139 */
140class MicroIntMov : public MicroOp
141{
142  protected:
143    RegIndex ura, urb;
144
145    MicroIntMov(const char *mnem, ExtMachInst machInst, OpClass __opClass,
146               RegIndex _ura, RegIndex _urb)
147            : MicroOp(mnem, machInst, __opClass),
148              ura(_ura), urb(_urb)
149    {
150    }
151
152    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
153};
154
155/**
156 * Microops of the form IntRegA = IntRegB op Imm
157 */
158class MicroIntImmOp : public MicroOp
159{
160  protected:
161    RegIndex ura, urb;
162    uint32_t imm;
163
164    MicroIntImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
165                  RegIndex _ura, RegIndex _urb, uint32_t _imm)
166            : MicroOp(mnem, machInst, __opClass),
167              ura(_ura), urb(_urb), imm(_imm)
168    {
169    }
170
171    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
172};
173
174/**
175 * Microops of the form IntRegA = IntRegB op IntRegC
176 */
177class MicroIntOp : public MicroOp
178{
179  protected:
180    RegIndex ura, urb, urc;
181
182    MicroIntOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
183               RegIndex _ura, RegIndex _urb, RegIndex _urc)
184            : MicroOp(mnem, machInst, __opClass),
185              ura(_ura), urb(_urb), urc(_urc)
186    {
187    }
188
189    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
190};
191
192/**
193 * Microops of the form IntRegA = IntRegB op shifted IntRegC
194 */
195class MicroIntRegOp : public MicroOp
196{
197  protected:
198    RegIndex ura, urb, urc;
199    int32_t shiftAmt;
200    ArmShiftType shiftType;
201
202    MicroIntRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
203               RegIndex _ura, RegIndex _urb, RegIndex _urc,
204               int32_t _shiftAmt, ArmShiftType _shiftType)
205            : MicroOp(mnem, machInst, __opClass),
206              ura(_ura), urb(_urb), urc(_urc),
207              shiftAmt(_shiftAmt), shiftType(_shiftType)
208    {
209    }
210};
211
212/**
213 * Memory microops which use IntReg + Imm addressing
214 */
215class MicroMemOp : public MicroIntImmOp
216{
217  protected:
218    bool up;
219    unsigned memAccessFlags;
220
221    MicroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
222               RegIndex _ura, RegIndex _urb, bool _up, uint8_t _imm)
223            : MicroIntImmOp(mnem, machInst, __opClass, _ura, _urb, _imm),
224              up(_up), memAccessFlags(TLB::MustBeOne | TLB::AlignWord)
225    {
226    }
227
228    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
229};
230
231/**
232 * Base class for microcoded integer memory instructions.
233 */
234class MacroMemOp : public PredMacroOp
235{
236  protected:
237    MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
238               IntRegIndex rn, bool index, bool up, bool user,
239               bool writeback, bool load, uint32_t reglist);
240};
241
242/**
243 * Base classes for microcoded integer memory instructions.
244 */
245class VldMultOp : public PredMacroOp
246{
247  protected:
248    VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
249              unsigned elems, RegIndex rn, RegIndex vd, unsigned regs,
250              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
251};
252
253class VldSingleOp : public PredMacroOp
254{
255  protected:
256    VldSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
257                bool all, unsigned elems, RegIndex rn, RegIndex vd,
258                unsigned regs, unsigned inc, uint32_t size,
259                uint32_t align, RegIndex rm, unsigned lane);
260};
261
262/**
263 * Base class for microcoded integer memory instructions.
264 */
265class VstMultOp : public PredMacroOp
266{
267  protected:
268    VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
269              unsigned width, RegIndex rn, RegIndex vd, unsigned regs,
270              unsigned inc, uint32_t size, uint32_t align, RegIndex rm);
271};
272
273class VstSingleOp : public PredMacroOp
274{
275  protected:
276    VstSingleOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
277                bool all, unsigned elems, RegIndex rn, RegIndex vd,
278                unsigned regs, unsigned inc, uint32_t size,
279                uint32_t align, RegIndex rm, unsigned lane);
280};
281
282/**
283 * Base class for microcoded floating point memory instructions.
284 */
285class MacroVFPMemOp : public PredMacroOp
286{
287  protected:
288    MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
289                  IntRegIndex rn, RegIndex vd, bool single, bool up,
290                  bool writeback, bool load, uint32_t offset);
291};
292
293}
294
295#endif //__ARCH_ARM_INSTS_MACROMEM_HH__
296