macromem.hh revision 6253:988a001820f8
1/* Copyright (c) 2007-2008 The Florida State University 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution; 11 * neither the name of the copyright holders nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Authors: Stephen Hines 28 */ 29#ifndef __ARCH_ARM_MACROMEM_HH__ 30#define __ARCH_ARM_MACROMEM_HH__ 31 32#include "arch/arm/insts/pred_inst.hh" 33 34namespace ArmISA 35{ 36 37static inline unsigned int 38number_of_ones(int32_t val) 39{ 40 uint32_t ones = 0; 41 for (int i = 0; i < 32; i++ ) 42 { 43 if ( val & (1<<i) ) 44 ones++; 45 } 46 return ones; 47} 48 49/** 50 * Arm Macro Memory operations like LDM/STM 51 */ 52class ArmMacroMemoryOp : public PredMacroOp 53{ 54 protected: 55 /// Memory request flags. See mem_req_base.hh. 56 unsigned memAccessFlags; 57 /// Pointer to EAComp object. 58 const StaticInstPtr eaCompPtr; 59 /// Pointer to MemAcc object. 60 const StaticInstPtr memAccPtr; 61 62 uint32_t reglist; 63 uint32_t ones; 64 uint32_t puswl, 65 prepost, 66 up, 67 psruser, 68 writeback, 69 loadop; 70 71 ArmMacroMemoryOp(const char *mnem, ExtMachInst _machInst, 72 OpClass __opClass, 73 StaticInstPtr _eaCompPtr = nullStaticInstPtr, 74 StaticInstPtr _memAccPtr = nullStaticInstPtr) 75 : PredMacroOp(mnem, _machInst, __opClass), 76 memAccessFlags(0), 77 eaCompPtr(_eaCompPtr), memAccPtr(_memAccPtr), 78 reglist(machInst.regList), ones(0), 79 puswl(machInst.puswl), 80 prepost(machInst.puswl.prepost), 81 up(machInst.puswl.up), 82 psruser(machInst.puswl.psruser), 83 writeback(machInst.puswl.writeback), 84 loadop(machInst.puswl.loadOp) 85 { 86 ones = number_of_ones(reglist); 87 numMicroops = ones + writeback + 1; 88 // Remember that writeback adds a uop 89 microOps = new StaticInstPtr[numMicroops]; 90 } 91}; 92 93/** 94 * Arm Macro FPA operations to fix ldfd and stfd instructions 95 */ 96class ArmMacroFPAOp : public PredMacroOp 97{ 98 protected: 99 uint32_t puswl, 100 prepost, 101 up, 102 psruser, 103 writeback, 104 loadop; 105 int32_t disp8; 106 107 ArmMacroFPAOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 108 : PredMacroOp(mnem, _machInst, __opClass), 109 puswl(machInst.puswl), 110 prepost(machInst.puswl.prepost), 111 up(machInst.puswl.up), 112 psruser(machInst.puswl.psruser), 113 writeback(machInst.puswl.writeback), 114 loadop(machInst.puswl.loadOp), 115 disp8(machInst.immed7_0 << 2) 116 { 117 numMicroops = 3 + writeback; 118 microOps = new StaticInstPtr[numMicroops]; 119 } 120}; 121 122/** 123 * Arm Macro FM operations to fix lfm and sfm 124 */ 125class ArmMacroFMOp : public PredMacroOp 126{ 127 protected: 128 uint32_t punwl, 129 prepost, 130 up, 131 n1bit, 132 writeback, 133 loadop, 134 n0bit, 135 count; 136 int32_t disp8; 137 138 ArmMacroFMOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 139 : PredMacroOp(mnem, _machInst, __opClass), 140 punwl(machInst.punwl), 141 prepost(machInst.puswl.prepost), 142 up(machInst.puswl.up), 143 n1bit(machInst.opcode22), 144 writeback(machInst.puswl.writeback), 145 loadop(machInst.puswl.loadOp), 146 n0bit(machInst.opcode15), 147 disp8(machInst.immed7_0 << 2) 148 { 149 // Transfer 1-4 registers based on n1 and n0 bits (with 00 repr. 4) 150 count = (n1bit << 1) | n0bit; 151 if (count == 0) 152 count = 4; 153 numMicroops = (3*count) + writeback; 154 microOps = new StaticInstPtr[numMicroops]; 155 } 156}; 157} 158 159#endif //__ARCH_ARM_INSTS_MACROMEM_HH__ 160