macromem.cc revision 8148
17170Sgblack@eecs.umich.edu/* 27170Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37170Sgblack@eecs.umich.edu * All rights reserved 47170Sgblack@eecs.umich.edu * 57170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137170Sgblack@eecs.umich.edu * 147170Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157170Sgblack@eecs.umich.edu * All rights reserved. 167170Sgblack@eecs.umich.edu * 177170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267170Sgblack@eecs.umich.edu * this software without specific prior written permission. 277170Sgblack@eecs.umich.edu * 287170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397170Sgblack@eecs.umich.edu * 407170Sgblack@eecs.umich.edu * Authors: Stephen Hines 417170Sgblack@eecs.umich.edu */ 427170Sgblack@eecs.umich.edu 437170Sgblack@eecs.umich.edu#include "arch/arm/insts/macromem.hh" 447170Sgblack@eecs.umich.edu#include "arch/arm/decoder.hh" 457853SMatt.Horsnell@ARM.com#include <sstream> 467170Sgblack@eecs.umich.edu 477853SMatt.Horsnell@ARM.comusing namespace std; 487170Sgblack@eecs.umich.eduusing namespace ArmISAInst; 497170Sgblack@eecs.umich.edu 507170Sgblack@eecs.umich.edunamespace ArmISA 517170Sgblack@eecs.umich.edu{ 527170Sgblack@eecs.umich.edu 537170Sgblack@eecs.umich.eduMacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, 547170Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 557170Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, 567170Sgblack@eecs.umich.edu bool load, uint32_t reglist) : 577170Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 587170Sgblack@eecs.umich.edu{ 597170Sgblack@eecs.umich.edu uint32_t regs = reglist; 607170Sgblack@eecs.umich.edu uint32_t ones = number_of_ones(reglist); 618148SAli.Saidi@ARM.com // Remember that writeback adds a uop or two and the temp register adds one 628148SAli.Saidi@ARM.com numMicroops = ones + (writeback ? (load ? 2 : 1) : 0) + 1; 638148SAli.Saidi@ARM.com 648148SAli.Saidi@ARM.com // It's technically legal to do a lot of nothing 658148SAli.Saidi@ARM.com if (!ones) 668148SAli.Saidi@ARM.com numMicroops = 1; 678148SAli.Saidi@ARM.com 687170Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 697170Sgblack@eecs.umich.edu uint32_t addr = 0; 707170Sgblack@eecs.umich.edu 717170Sgblack@eecs.umich.edu if (!up) 727170Sgblack@eecs.umich.edu addr = (ones << 2) - 4; 737170Sgblack@eecs.umich.edu 747170Sgblack@eecs.umich.edu if (!index) 757170Sgblack@eecs.umich.edu addr += 4; 767170Sgblack@eecs.umich.edu 777190Sgblack@eecs.umich.edu StaticInstPtr *uop = microOps; 787190Sgblack@eecs.umich.edu 797170Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in ureg0. 807170Sgblack@eecs.umich.edu // This is equivalent to a move. 817190Sgblack@eecs.umich.edu *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 827190Sgblack@eecs.umich.edu 837170Sgblack@eecs.umich.edu unsigned reg = 0; 848148SAli.Saidi@ARM.com unsigned regIdx = 0; 857170Sgblack@eecs.umich.edu bool force_user = user & !bits(reglist, 15); 867170Sgblack@eecs.umich.edu bool exception_ret = user & bits(reglist, 15); 877170Sgblack@eecs.umich.edu 887190Sgblack@eecs.umich.edu for (int i = 0; i < ones; i++) { 897170Sgblack@eecs.umich.edu // Find the next register. 907170Sgblack@eecs.umich.edu while (!bits(regs, reg)) 917170Sgblack@eecs.umich.edu reg++; 927170Sgblack@eecs.umich.edu replaceBits(regs, reg, 0); 937170Sgblack@eecs.umich.edu 948148SAli.Saidi@ARM.com regIdx = reg; 957170Sgblack@eecs.umich.edu if (force_user) { 967310Sgblack@eecs.umich.edu regIdx = intRegInMode(MODE_USER, regIdx); 977170Sgblack@eecs.umich.edu } 987170Sgblack@eecs.umich.edu 997170Sgblack@eecs.umich.edu if (load) { 1008148SAli.Saidi@ARM.com if (writeback && i == ones - 1) { 1018148SAli.Saidi@ARM.com // If it's a writeback and this is the last register 1028148SAli.Saidi@ARM.com // do the load into a temporary register which we'll move 1038148SAli.Saidi@ARM.com // into the final one later 1048148SAli.Saidi@ARM.com *++uop = new MicroLdrUop(machInst, INTREG_UREG1, INTREG_UREG0, 1058148SAli.Saidi@ARM.com up, addr); 1067170Sgblack@eecs.umich.edu } else { 1078148SAli.Saidi@ARM.com // Otherwise just do it normally 1088148SAli.Saidi@ARM.com if (reg == INTREG_PC && exception_ret) { 1098148SAli.Saidi@ARM.com // This must be the exception return form of ldm. 1108148SAli.Saidi@ARM.com *++uop = new MicroLdrRetUop(machInst, regIdx, 1118148SAli.Saidi@ARM.com INTREG_UREG0, up, addr); 1128148SAli.Saidi@ARM.com } else { 1138148SAli.Saidi@ARM.com *++uop = new MicroLdrUop(machInst, regIdx, 1148148SAli.Saidi@ARM.com INTREG_UREG0, up, addr); 1158148SAli.Saidi@ARM.com } 1167170Sgblack@eecs.umich.edu } 1177170Sgblack@eecs.umich.edu } else { 1187190Sgblack@eecs.umich.edu *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1197170Sgblack@eecs.umich.edu } 1207170Sgblack@eecs.umich.edu 1217170Sgblack@eecs.umich.edu if (up) 1227170Sgblack@eecs.umich.edu addr += 4; 1237170Sgblack@eecs.umich.edu else 1247170Sgblack@eecs.umich.edu addr -= 4; 1257170Sgblack@eecs.umich.edu } 1267170Sgblack@eecs.umich.edu 1278148SAli.Saidi@ARM.com if (writeback && ones) { 1288148SAli.Saidi@ARM.com // put the register update after we're done all loading 1298148SAli.Saidi@ARM.com if (up) 1308148SAli.Saidi@ARM.com *++uop = new MicroAddiUop(machInst, rn, rn, ones * 4); 1318148SAli.Saidi@ARM.com else 1328148SAli.Saidi@ARM.com *++uop = new MicroSubiUop(machInst, rn, rn, ones * 4); 1338148SAli.Saidi@ARM.com 1348148SAli.Saidi@ARM.com // If this was a load move the last temporary value into place 1358148SAli.Saidi@ARM.com // this way we can't take an exception after we update the base 1368148SAli.Saidi@ARM.com // register. 1378148SAli.Saidi@ARM.com if (load && reg == INTREG_PC && exception_ret) { 1388148SAli.Saidi@ARM.com *++uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1); 1398148SAli.Saidi@ARM.com warn("creating instruction with exception return at curTick:%d\n", 1408148SAli.Saidi@ARM.com curTick()); 1418148SAli.Saidi@ARM.com } else if (load) { 1428148SAli.Saidi@ARM.com *++uop = new MicroUopRegMov(machInst, regIdx, INTREG_UREG1); 1438148SAli.Saidi@ARM.com if (reg == INTREG_PC) { 1448148SAli.Saidi@ARM.com (*uop)->setFlag(StaticInstBase::IsControl); 1458148SAli.Saidi@ARM.com (*uop)->setFlag(StaticInstBase::IsCondControl); 1468148SAli.Saidi@ARM.com (*uop)->setFlag(StaticInstBase::IsIndirectControl); 1478148SAli.Saidi@ARM.com // This is created as a RAS POP 1488148SAli.Saidi@ARM.com if (rn == INTREG_SP) 1498148SAli.Saidi@ARM.com (*uop)->setFlag(StaticInstBase::IsReturn); 1508148SAli.Saidi@ARM.com 1518148SAli.Saidi@ARM.com } 1528148SAli.Saidi@ARM.com } 1537170Sgblack@eecs.umich.edu } 1547190Sgblack@eecs.umich.edu 1557190Sgblack@eecs.umich.edu (*uop)->setLastMicroop(); 1567343Sgblack@eecs.umich.edu 1577343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 1587343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 1597343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 1607343Sgblack@eecs.umich.edu assert(uopPtr); 1617343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 1627343Sgblack@eecs.umich.edu } 1637170Sgblack@eecs.umich.edu} 1647170Sgblack@eecs.umich.edu 1657639Sgblack@eecs.umich.eduVldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1667639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 1677639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 1687639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 1697639Sgblack@eecs.umich.edu{ 1707639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 1717639Sgblack@eecs.umich.edu assert(regs % elems == 0); 1727639Sgblack@eecs.umich.edu 1737639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 1747639Sgblack@eecs.umich.edu bool wb = (rm != 15); 1757639Sgblack@eecs.umich.edu bool deinterleave = (elems > 1); 1767639Sgblack@eecs.umich.edu 1777639Sgblack@eecs.umich.edu if (wb) numMicroops++; 1787639Sgblack@eecs.umich.edu if (deinterleave) numMicroops += (regs / elems); 1797639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1807639Sgblack@eecs.umich.edu 1817639Sgblack@eecs.umich.edu RegIndex rMid = deinterleave ? NumFloatArchRegs : vd * 2; 1827639Sgblack@eecs.umich.edu 1837639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 1847639Sgblack@eecs.umich.edu 1857639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 1867639Sgblack@eecs.umich.edu switch (regs) { 1877639Sgblack@eecs.umich.edu case 4: 1887639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1897639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1907639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1917639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1927639Sgblack@eecs.umich.edu break; 1937639Sgblack@eecs.umich.edu case 3: 1947639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1957639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1967639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 1977639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1987639Sgblack@eecs.umich.edu break; 1997639Sgblack@eecs.umich.edu case 2: 2007639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 2017639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 2027639Sgblack@eecs.umich.edu break; 2037639Sgblack@eecs.umich.edu case 1: 2047639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 2057639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 2067639Sgblack@eecs.umich.edu break; 2077639Sgblack@eecs.umich.edu default: 2087853SMatt.Horsnell@ARM.com // Unknown number of registers 2097853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 2107639Sgblack@eecs.umich.edu } 2117639Sgblack@eecs.umich.edu if (wb) { 2127639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 2137639Sgblack@eecs.umich.edu microOps[uopIdx++] = 2147646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 2157639Sgblack@eecs.umich.edu } else { 2167639Sgblack@eecs.umich.edu microOps[uopIdx++] = 2177639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 2187639Sgblack@eecs.umich.edu } 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu if (deinterleave) { 2217639Sgblack@eecs.umich.edu switch (elems) { 2227639Sgblack@eecs.umich.edu case 4: 2237639Sgblack@eecs.umich.edu assert(regs == 4); 2247639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon8Uop>( 2257639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2267639Sgblack@eecs.umich.edu break; 2277639Sgblack@eecs.umich.edu case 3: 2287639Sgblack@eecs.umich.edu assert(regs == 3); 2297639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon6Uop>( 2307639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2317639Sgblack@eecs.umich.edu break; 2327639Sgblack@eecs.umich.edu case 2: 2337639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 2347639Sgblack@eecs.umich.edu if (regs == 4) { 2357639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2367639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2377639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2387639Sgblack@eecs.umich.edu size, machInst, vd * 2 + 2, rMid + 4, inc * 2); 2397639Sgblack@eecs.umich.edu } else { 2407639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2417639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2427639Sgblack@eecs.umich.edu } 2437639Sgblack@eecs.umich.edu break; 2447639Sgblack@eecs.umich.edu default: 2457853SMatt.Horsnell@ARM.com // Bad number of elements to deinterleave 2467853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 2477639Sgblack@eecs.umich.edu } 2487639Sgblack@eecs.umich.edu } 2497639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 2507639Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 2527639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 2537639Sgblack@eecs.umich.edu assert(uopPtr); 2547639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 2557639Sgblack@eecs.umich.edu } 2567639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 2577639Sgblack@eecs.umich.edu} 2587639Sgblack@eecs.umich.edu 2597639Sgblack@eecs.umich.eduVldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, 2607639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 2617639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 2627639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 2637639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 2647639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 2657639Sgblack@eecs.umich.edu{ 2667639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 2677639Sgblack@eecs.umich.edu assert(regs % elems == 0); 2687639Sgblack@eecs.umich.edu 2697639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 2707639Sgblack@eecs.umich.edu unsigned loadSize = eBytes * elems; 2717639Sgblack@eecs.umich.edu unsigned loadRegs M5_VAR_USED = (loadSize + sizeof(FloatRegBits) - 1) / 2727639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 2737639Sgblack@eecs.umich.edu 2747639Sgblack@eecs.umich.edu assert(loadRegs > 0 && loadRegs <= 4); 2757639Sgblack@eecs.umich.edu 2767639Sgblack@eecs.umich.edu numMicroops = 1; 2777639Sgblack@eecs.umich.edu bool wb = (rm != 15); 2787639Sgblack@eecs.umich.edu 2797639Sgblack@eecs.umich.edu if (wb) numMicroops++; 2807639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 2817639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 2827639Sgblack@eecs.umich.edu 2837639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 2847639Sgblack@eecs.umich.edu 2857639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 2867639Sgblack@eecs.umich.edu switch (loadSize) { 2877639Sgblack@eecs.umich.edu case 1: 2887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon1Uop<uint8_t>( 2897639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2907639Sgblack@eecs.umich.edu break; 2917639Sgblack@eecs.umich.edu case 2: 2927639Sgblack@eecs.umich.edu if (eBytes == 2) { 2937639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint16_t>( 2947639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2957639Sgblack@eecs.umich.edu } else { 2967639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint8_t>( 2977639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2987639Sgblack@eecs.umich.edu } 2997639Sgblack@eecs.umich.edu break; 3007639Sgblack@eecs.umich.edu case 3: 3017639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon3Uop<uint8_t>( 3027639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3037639Sgblack@eecs.umich.edu break; 3047639Sgblack@eecs.umich.edu case 4: 3057639Sgblack@eecs.umich.edu switch (eBytes) { 3067639Sgblack@eecs.umich.edu case 1: 3077639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint8_t>( 3087639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3097639Sgblack@eecs.umich.edu break; 3107639Sgblack@eecs.umich.edu case 2: 3117639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint16_t>( 3127639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3137639Sgblack@eecs.umich.edu break; 3147639Sgblack@eecs.umich.edu case 4: 3157639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint32_t>( 3167639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3177639Sgblack@eecs.umich.edu break; 3187639Sgblack@eecs.umich.edu } 3197639Sgblack@eecs.umich.edu break; 3207639Sgblack@eecs.umich.edu case 6: 3217639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon6Uop<uint16_t>( 3227639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3237639Sgblack@eecs.umich.edu break; 3247639Sgblack@eecs.umich.edu case 8: 3257639Sgblack@eecs.umich.edu switch (eBytes) { 3267639Sgblack@eecs.umich.edu case 2: 3277639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint16_t>( 3287639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3297639Sgblack@eecs.umich.edu break; 3307639Sgblack@eecs.umich.edu case 4: 3317639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint32_t>( 3327639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3337639Sgblack@eecs.umich.edu break; 3347639Sgblack@eecs.umich.edu } 3357639Sgblack@eecs.umich.edu break; 3367639Sgblack@eecs.umich.edu case 12: 3377639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon12Uop<uint32_t>( 3387639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3397639Sgblack@eecs.umich.edu break; 3407639Sgblack@eecs.umich.edu case 16: 3417639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon16Uop<uint32_t>( 3427639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3437639Sgblack@eecs.umich.edu break; 3447639Sgblack@eecs.umich.edu default: 3457853SMatt.Horsnell@ARM.com // Unrecognized load size 3467853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3477639Sgblack@eecs.umich.edu } 3487639Sgblack@eecs.umich.edu if (wb) { 3497639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 3507639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3517646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 3527639Sgblack@eecs.umich.edu } else { 3537639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3547639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, loadSize); 3557639Sgblack@eecs.umich.edu } 3567639Sgblack@eecs.umich.edu } 3577639Sgblack@eecs.umich.edu switch (elems) { 3587639Sgblack@eecs.umich.edu case 4: 3597639Sgblack@eecs.umich.edu assert(regs == 4); 3607639Sgblack@eecs.umich.edu switch (size) { 3617639Sgblack@eecs.umich.edu case 0: 3627639Sgblack@eecs.umich.edu if (all) { 3637639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint8_t>( 3647639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3657639Sgblack@eecs.umich.edu } else { 3667639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint8_t>( 3677639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3687639Sgblack@eecs.umich.edu } 3697639Sgblack@eecs.umich.edu break; 3707639Sgblack@eecs.umich.edu case 1: 3717639Sgblack@eecs.umich.edu if (all) { 3727639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint16_t>( 3737639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3747639Sgblack@eecs.umich.edu } else { 3757639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint16_t>( 3767639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3777639Sgblack@eecs.umich.edu } 3787639Sgblack@eecs.umich.edu break; 3797639Sgblack@eecs.umich.edu case 2: 3807639Sgblack@eecs.umich.edu if (all) { 3817639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to8Uop<uint32_t>( 3827639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3837639Sgblack@eecs.umich.edu } else { 3847639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to8Uop<uint32_t>( 3857639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3867639Sgblack@eecs.umich.edu } 3877639Sgblack@eecs.umich.edu break; 3887639Sgblack@eecs.umich.edu default: 3897853SMatt.Horsnell@ARM.com // Bad size 3907853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3917639Sgblack@eecs.umich.edu break; 3927639Sgblack@eecs.umich.edu } 3937639Sgblack@eecs.umich.edu break; 3947639Sgblack@eecs.umich.edu case 3: 3957639Sgblack@eecs.umich.edu assert(regs == 3); 3967639Sgblack@eecs.umich.edu switch (size) { 3977639Sgblack@eecs.umich.edu case 0: 3987639Sgblack@eecs.umich.edu if (all) { 3997639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint8_t>( 4007639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4017639Sgblack@eecs.umich.edu } else { 4027639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint8_t>( 4037639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4047639Sgblack@eecs.umich.edu } 4057639Sgblack@eecs.umich.edu break; 4067639Sgblack@eecs.umich.edu case 1: 4077639Sgblack@eecs.umich.edu if (all) { 4087639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint16_t>( 4097639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4107639Sgblack@eecs.umich.edu } else { 4117639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint16_t>( 4127639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4137639Sgblack@eecs.umich.edu } 4147639Sgblack@eecs.umich.edu break; 4157639Sgblack@eecs.umich.edu case 2: 4167639Sgblack@eecs.umich.edu if (all) { 4177639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to6Uop<uint32_t>( 4187639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4197639Sgblack@eecs.umich.edu } else { 4207639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to6Uop<uint32_t>( 4217639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4227639Sgblack@eecs.umich.edu } 4237639Sgblack@eecs.umich.edu break; 4247639Sgblack@eecs.umich.edu default: 4257853SMatt.Horsnell@ARM.com // Bad size 4267853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4277639Sgblack@eecs.umich.edu break; 4287639Sgblack@eecs.umich.edu } 4297639Sgblack@eecs.umich.edu break; 4307639Sgblack@eecs.umich.edu case 2: 4317639Sgblack@eecs.umich.edu assert(regs == 2); 4327639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4337639Sgblack@eecs.umich.edu switch (size) { 4347639Sgblack@eecs.umich.edu case 0: 4357639Sgblack@eecs.umich.edu if (all) { 4367639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint8_t>( 4377639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4387639Sgblack@eecs.umich.edu } else { 4397639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint8_t>( 4407639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4417639Sgblack@eecs.umich.edu } 4427639Sgblack@eecs.umich.edu break; 4437639Sgblack@eecs.umich.edu case 1: 4447639Sgblack@eecs.umich.edu if (all) { 4457639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint16_t>( 4467639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4477639Sgblack@eecs.umich.edu } else { 4487639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint16_t>( 4497639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4507639Sgblack@eecs.umich.edu } 4517639Sgblack@eecs.umich.edu break; 4527639Sgblack@eecs.umich.edu case 2: 4537639Sgblack@eecs.umich.edu if (all) { 4547639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint32_t>( 4557639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4567639Sgblack@eecs.umich.edu } else { 4577639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint32_t>( 4587639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4597639Sgblack@eecs.umich.edu } 4607639Sgblack@eecs.umich.edu break; 4617639Sgblack@eecs.umich.edu default: 4627853SMatt.Horsnell@ARM.com // Bad size 4637853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4647639Sgblack@eecs.umich.edu break; 4657639Sgblack@eecs.umich.edu } 4667639Sgblack@eecs.umich.edu break; 4677639Sgblack@eecs.umich.edu case 1: 4687639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 4697639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4707639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 4717639Sgblack@eecs.umich.edu switch (size) { 4727639Sgblack@eecs.umich.edu case 0: 4737639Sgblack@eecs.umich.edu if (all) { 4747639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4757639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint8_t>( 4767639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4777639Sgblack@eecs.umich.edu } else { 4787639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4797639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint8_t>( 4807639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4817639Sgblack@eecs.umich.edu } 4827639Sgblack@eecs.umich.edu break; 4837639Sgblack@eecs.umich.edu case 1: 4847639Sgblack@eecs.umich.edu if (all) { 4857639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4867639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint16_t>( 4877639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4887639Sgblack@eecs.umich.edu } else { 4897639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4907639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint16_t>( 4917639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4927639Sgblack@eecs.umich.edu } 4937639Sgblack@eecs.umich.edu break; 4947639Sgblack@eecs.umich.edu case 2: 4957639Sgblack@eecs.umich.edu if (all) { 4967639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4977639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint32_t>( 4987639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4997639Sgblack@eecs.umich.edu } else { 5007639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5017639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint32_t>( 5027639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 5037639Sgblack@eecs.umich.edu } 5047639Sgblack@eecs.umich.edu break; 5057639Sgblack@eecs.umich.edu default: 5067853SMatt.Horsnell@ARM.com // Bad size 5077853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5087639Sgblack@eecs.umich.edu break; 5097639Sgblack@eecs.umich.edu } 5107639Sgblack@eecs.umich.edu } 5117639Sgblack@eecs.umich.edu break; 5127639Sgblack@eecs.umich.edu default: 5137853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 5147853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5157639Sgblack@eecs.umich.edu } 5167639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 5177639Sgblack@eecs.umich.edu 5187639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 5197639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 5207639Sgblack@eecs.umich.edu assert(uopPtr); 5217639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 5227639Sgblack@eecs.umich.edu } 5237639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 5247639Sgblack@eecs.umich.edu} 5257639Sgblack@eecs.umich.edu 5267639Sgblack@eecs.umich.eduVstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 5277639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 5287639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 5297639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 5307639Sgblack@eecs.umich.edu{ 5317639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 5327639Sgblack@eecs.umich.edu assert(regs % elems == 0); 5337639Sgblack@eecs.umich.edu 5347639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 5357639Sgblack@eecs.umich.edu bool wb = (rm != 15); 5367639Sgblack@eecs.umich.edu bool interleave = (elems > 1); 5377639Sgblack@eecs.umich.edu 5387639Sgblack@eecs.umich.edu if (wb) numMicroops++; 5397639Sgblack@eecs.umich.edu if (interleave) numMicroops += (regs / elems); 5407639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 5417639Sgblack@eecs.umich.edu 5427639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 5437639Sgblack@eecs.umich.edu 5447639Sgblack@eecs.umich.edu RegIndex rMid = interleave ? NumFloatArchRegs : vd * 2; 5457639Sgblack@eecs.umich.edu 5467639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 5477639Sgblack@eecs.umich.edu if (interleave) { 5487639Sgblack@eecs.umich.edu switch (elems) { 5497639Sgblack@eecs.umich.edu case 4: 5507639Sgblack@eecs.umich.edu assert(regs == 4); 5517639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon8Uop>( 5527639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5537639Sgblack@eecs.umich.edu break; 5547639Sgblack@eecs.umich.edu case 3: 5557639Sgblack@eecs.umich.edu assert(regs == 3); 5567639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon6Uop>( 5577639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5587639Sgblack@eecs.umich.edu break; 5597639Sgblack@eecs.umich.edu case 2: 5607639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 5617639Sgblack@eecs.umich.edu if (regs == 4) { 5627639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5637639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5647639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5657639Sgblack@eecs.umich.edu size, machInst, rMid + 4, vd * 2 + 2, inc * 2); 5667639Sgblack@eecs.umich.edu } else { 5677639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5687639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5697639Sgblack@eecs.umich.edu } 5707639Sgblack@eecs.umich.edu break; 5717639Sgblack@eecs.umich.edu default: 5727853SMatt.Horsnell@ARM.com // Bad number of elements to interleave 5737853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5747639Sgblack@eecs.umich.edu } 5757639Sgblack@eecs.umich.edu } 5767639Sgblack@eecs.umich.edu switch (regs) { 5777639Sgblack@eecs.umich.edu case 4: 5787639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5797639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5807639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5817639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5827639Sgblack@eecs.umich.edu break; 5837639Sgblack@eecs.umich.edu case 3: 5847639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5857639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5867639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5877639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5887639Sgblack@eecs.umich.edu break; 5897639Sgblack@eecs.umich.edu case 2: 5907639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5917639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5927639Sgblack@eecs.umich.edu break; 5937639Sgblack@eecs.umich.edu case 1: 5947639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5957639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5967639Sgblack@eecs.umich.edu break; 5977639Sgblack@eecs.umich.edu default: 5987853SMatt.Horsnell@ARM.com // Unknown number of registers 5997853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6007639Sgblack@eecs.umich.edu } 6017639Sgblack@eecs.umich.edu if (wb) { 6027639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 6037639Sgblack@eecs.umich.edu microOps[uopIdx++] = 6047646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 6057639Sgblack@eecs.umich.edu } else { 6067639Sgblack@eecs.umich.edu microOps[uopIdx++] = 6077639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 6087639Sgblack@eecs.umich.edu } 6097639Sgblack@eecs.umich.edu } 6107639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 6117639Sgblack@eecs.umich.edu 6127639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 6137639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 6147639Sgblack@eecs.umich.edu assert(uopPtr); 6157639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 6167639Sgblack@eecs.umich.edu } 6177639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 6187639Sgblack@eecs.umich.edu} 6197639Sgblack@eecs.umich.edu 6207639Sgblack@eecs.umich.eduVstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, 6217639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 6227639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 6237639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 6247639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 6257639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 6267639Sgblack@eecs.umich.edu{ 6277639Sgblack@eecs.umich.edu assert(!all); 6287639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 6297639Sgblack@eecs.umich.edu assert(regs % elems == 0); 6307639Sgblack@eecs.umich.edu 6317639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 6327639Sgblack@eecs.umich.edu unsigned storeSize = eBytes * elems; 6337639Sgblack@eecs.umich.edu unsigned storeRegs M5_VAR_USED = (storeSize + sizeof(FloatRegBits) - 1) / 6347639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 6357639Sgblack@eecs.umich.edu 6367639Sgblack@eecs.umich.edu assert(storeRegs > 0 && storeRegs <= 4); 6377639Sgblack@eecs.umich.edu 6387639Sgblack@eecs.umich.edu numMicroops = 1; 6397639Sgblack@eecs.umich.edu bool wb = (rm != 15); 6407639Sgblack@eecs.umich.edu 6417639Sgblack@eecs.umich.edu if (wb) numMicroops++; 6427639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 6437639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 6447639Sgblack@eecs.umich.edu 6457639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 6467639Sgblack@eecs.umich.edu 6477639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 6487639Sgblack@eecs.umich.edu switch (elems) { 6497639Sgblack@eecs.umich.edu case 4: 6507639Sgblack@eecs.umich.edu assert(regs == 4); 6517639Sgblack@eecs.umich.edu switch (size) { 6527639Sgblack@eecs.umich.edu case 0: 6537639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint8_t>( 6547639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6557639Sgblack@eecs.umich.edu break; 6567639Sgblack@eecs.umich.edu case 1: 6577639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint16_t>( 6587639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6597639Sgblack@eecs.umich.edu break; 6607639Sgblack@eecs.umich.edu case 2: 6617639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to4Uop<uint32_t>( 6627639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6637639Sgblack@eecs.umich.edu break; 6647639Sgblack@eecs.umich.edu default: 6657853SMatt.Horsnell@ARM.com // Bad size 6667853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6677639Sgblack@eecs.umich.edu break; 6687639Sgblack@eecs.umich.edu } 6697639Sgblack@eecs.umich.edu break; 6707639Sgblack@eecs.umich.edu case 3: 6717639Sgblack@eecs.umich.edu assert(regs == 3); 6727639Sgblack@eecs.umich.edu switch (size) { 6737639Sgblack@eecs.umich.edu case 0: 6747639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint8_t>( 6757639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6767639Sgblack@eecs.umich.edu break; 6777639Sgblack@eecs.umich.edu case 1: 6787639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint16_t>( 6797639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6807639Sgblack@eecs.umich.edu break; 6817639Sgblack@eecs.umich.edu case 2: 6827639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to4Uop<uint32_t>( 6837639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6847639Sgblack@eecs.umich.edu break; 6857639Sgblack@eecs.umich.edu default: 6867853SMatt.Horsnell@ARM.com // Bad size 6877853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6887639Sgblack@eecs.umich.edu break; 6897639Sgblack@eecs.umich.edu } 6907639Sgblack@eecs.umich.edu break; 6917639Sgblack@eecs.umich.edu case 2: 6927639Sgblack@eecs.umich.edu assert(regs == 2); 6937639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 6947639Sgblack@eecs.umich.edu switch (size) { 6957639Sgblack@eecs.umich.edu case 0: 6967639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint8_t>( 6977639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6987639Sgblack@eecs.umich.edu break; 6997639Sgblack@eecs.umich.edu case 1: 7007639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint16_t>( 7017639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 7027639Sgblack@eecs.umich.edu break; 7037639Sgblack@eecs.umich.edu case 2: 7047639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint32_t>( 7057639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 7067639Sgblack@eecs.umich.edu break; 7077639Sgblack@eecs.umich.edu default: 7087853SMatt.Horsnell@ARM.com // Bad size 7097853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7107639Sgblack@eecs.umich.edu break; 7117639Sgblack@eecs.umich.edu } 7127639Sgblack@eecs.umich.edu break; 7137639Sgblack@eecs.umich.edu case 1: 7147639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 7157639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 7167639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 7177639Sgblack@eecs.umich.edu switch (size) { 7187639Sgblack@eecs.umich.edu case 0: 7197639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint8_t>( 7207639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7217639Sgblack@eecs.umich.edu break; 7227639Sgblack@eecs.umich.edu case 1: 7237639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint16_t>( 7247639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7257639Sgblack@eecs.umich.edu break; 7267639Sgblack@eecs.umich.edu case 2: 7277639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint32_t>( 7287639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7297639Sgblack@eecs.umich.edu break; 7307639Sgblack@eecs.umich.edu default: 7317853SMatt.Horsnell@ARM.com // Bad size 7327853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7337639Sgblack@eecs.umich.edu break; 7347639Sgblack@eecs.umich.edu } 7357639Sgblack@eecs.umich.edu } 7367639Sgblack@eecs.umich.edu break; 7377639Sgblack@eecs.umich.edu default: 7387853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 7397853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7407639Sgblack@eecs.umich.edu } 7417639Sgblack@eecs.umich.edu switch (storeSize) { 7427639Sgblack@eecs.umich.edu case 1: 7437639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon1Uop<uint8_t>( 7447639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7457639Sgblack@eecs.umich.edu break; 7467639Sgblack@eecs.umich.edu case 2: 7477639Sgblack@eecs.umich.edu if (eBytes == 2) { 7487639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint16_t>( 7497639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7507639Sgblack@eecs.umich.edu } else { 7517639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint8_t>( 7527639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7537639Sgblack@eecs.umich.edu } 7547639Sgblack@eecs.umich.edu break; 7557639Sgblack@eecs.umich.edu case 3: 7567639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon3Uop<uint8_t>( 7577639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7587639Sgblack@eecs.umich.edu break; 7597639Sgblack@eecs.umich.edu case 4: 7607639Sgblack@eecs.umich.edu switch (eBytes) { 7617639Sgblack@eecs.umich.edu case 1: 7627639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint8_t>( 7637639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7647639Sgblack@eecs.umich.edu break; 7657639Sgblack@eecs.umich.edu case 2: 7667639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint16_t>( 7677639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7687639Sgblack@eecs.umich.edu break; 7697639Sgblack@eecs.umich.edu case 4: 7707639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint32_t>( 7717639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7727639Sgblack@eecs.umich.edu break; 7737639Sgblack@eecs.umich.edu } 7747639Sgblack@eecs.umich.edu break; 7757639Sgblack@eecs.umich.edu case 6: 7767639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon6Uop<uint16_t>( 7777639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7787639Sgblack@eecs.umich.edu break; 7797639Sgblack@eecs.umich.edu case 8: 7807639Sgblack@eecs.umich.edu switch (eBytes) { 7817639Sgblack@eecs.umich.edu case 2: 7827639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint16_t>( 7837639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7847639Sgblack@eecs.umich.edu break; 7857639Sgblack@eecs.umich.edu case 4: 7867639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint32_t>( 7877639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7887639Sgblack@eecs.umich.edu break; 7897639Sgblack@eecs.umich.edu } 7907639Sgblack@eecs.umich.edu break; 7917639Sgblack@eecs.umich.edu case 12: 7927639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon12Uop<uint32_t>( 7937639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7947639Sgblack@eecs.umich.edu break; 7957639Sgblack@eecs.umich.edu case 16: 7967639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon16Uop<uint32_t>( 7977639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7987639Sgblack@eecs.umich.edu break; 7997639Sgblack@eecs.umich.edu default: 8007853SMatt.Horsnell@ARM.com // Bad store size 8017853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 8027639Sgblack@eecs.umich.edu } 8037639Sgblack@eecs.umich.edu if (wb) { 8047639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 8057639Sgblack@eecs.umich.edu microOps[uopIdx++] = 8067646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 8077639Sgblack@eecs.umich.edu } else { 8087639Sgblack@eecs.umich.edu microOps[uopIdx++] = 8097639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, storeSize); 8107639Sgblack@eecs.umich.edu } 8117639Sgblack@eecs.umich.edu } 8127639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 8137639Sgblack@eecs.umich.edu 8147639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 8157639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 8167639Sgblack@eecs.umich.edu assert(uopPtr); 8177639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 8187639Sgblack@eecs.umich.edu } 8197639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 8207639Sgblack@eecs.umich.edu} 8217639Sgblack@eecs.umich.edu 8227175Sgblack@eecs.umich.eduMacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, 8237175Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 8247175Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, 8257175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset) : 8267175Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 8277175Sgblack@eecs.umich.edu{ 8287175Sgblack@eecs.umich.edu int i = 0; 8297175Sgblack@eecs.umich.edu 8307175Sgblack@eecs.umich.edu // The lowest order bit selects fldmx (set) or fldmd (clear). These seem 8317175Sgblack@eecs.umich.edu // to be functionally identical except that fldmx is deprecated. For now 8327175Sgblack@eecs.umich.edu // we'll assume they're otherwise interchangable. 8337175Sgblack@eecs.umich.edu int count = (single ? offset : (offset / 2)); 8347175Sgblack@eecs.umich.edu if (count == 0 || count > NumFloatArchRegs) 8357175Sgblack@eecs.umich.edu warn_once("Bad offset field for VFP load/store multiple.\n"); 8367175Sgblack@eecs.umich.edu if (count == 0) { 8377175Sgblack@eecs.umich.edu // Force there to be at least one microop so the macroop makes sense. 8387175Sgblack@eecs.umich.edu writeback = true; 8397175Sgblack@eecs.umich.edu } 8407175Sgblack@eecs.umich.edu if (count > NumFloatArchRegs) 8417175Sgblack@eecs.umich.edu count = NumFloatArchRegs; 8427175Sgblack@eecs.umich.edu 8437342Sgblack@eecs.umich.edu numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0); 8447342Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 8457342Sgblack@eecs.umich.edu 8467395Sgblack@eecs.umich.edu int64_t addr = 0; 8477175Sgblack@eecs.umich.edu 8487342Sgblack@eecs.umich.edu if (!up) 8497342Sgblack@eecs.umich.edu addr = 4 * offset; 8507175Sgblack@eecs.umich.edu 8517342Sgblack@eecs.umich.edu bool tempUp = up; 8527175Sgblack@eecs.umich.edu for (int j = 0; j < count; j++) { 8537175Sgblack@eecs.umich.edu if (load) { 8547639Sgblack@eecs.umich.edu if (single) { 8557639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, 8567639Sgblack@eecs.umich.edu tempUp, addr); 8577639Sgblack@eecs.umich.edu } else { 8587639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDBFpUop(machInst, vd++, rn, 8597639Sgblack@eecs.umich.edu tempUp, addr); 8607639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDTFpUop(machInst, vd++, rn, tempUp, 8617639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8627639Sgblack@eecs.umich.edu } 8637175Sgblack@eecs.umich.edu } else { 8647639Sgblack@eecs.umich.edu if (single) { 8657639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, 8667639Sgblack@eecs.umich.edu tempUp, addr); 8677639Sgblack@eecs.umich.edu } else { 8687639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDBFpUop(machInst, vd++, rn, 8697639Sgblack@eecs.umich.edu tempUp, addr); 8707639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDTFpUop(machInst, vd++, rn, tempUp, 8717639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8727639Sgblack@eecs.umich.edu } 8737175Sgblack@eecs.umich.edu } 8747342Sgblack@eecs.umich.edu if (!tempUp) { 8757342Sgblack@eecs.umich.edu addr -= (single ? 4 : 8); 8767342Sgblack@eecs.umich.edu // The microops don't handle negative displacement, so turn if we 8777342Sgblack@eecs.umich.edu // hit zero, flip polarity and start adding. 8787395Sgblack@eecs.umich.edu if (addr <= 0) { 8797342Sgblack@eecs.umich.edu tempUp = true; 8807395Sgblack@eecs.umich.edu addr = -addr; 8817342Sgblack@eecs.umich.edu } 8827342Sgblack@eecs.umich.edu } else { 8837342Sgblack@eecs.umich.edu addr += (single ? 4 : 8); 8847342Sgblack@eecs.umich.edu } 8857175Sgblack@eecs.umich.edu } 8867175Sgblack@eecs.umich.edu 8877175Sgblack@eecs.umich.edu if (writeback) { 8887175Sgblack@eecs.umich.edu if (up) { 8897175Sgblack@eecs.umich.edu microOps[i++] = 8907175Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, 4 * offset); 8917175Sgblack@eecs.umich.edu } else { 8927175Sgblack@eecs.umich.edu microOps[i++] = 8937175Sgblack@eecs.umich.edu new MicroSubiUop(machInst, rn, rn, 4 * offset); 8947175Sgblack@eecs.umich.edu } 8957175Sgblack@eecs.umich.edu } 8967175Sgblack@eecs.umich.edu 8977342Sgblack@eecs.umich.edu assert(numMicroops == i); 8987175Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 8997343Sgblack@eecs.umich.edu 9007343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 9017343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 9027343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 9037343Sgblack@eecs.umich.edu assert(uopPtr); 9047343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 9057343Sgblack@eecs.umich.edu } 9067170Sgblack@eecs.umich.edu} 9077175Sgblack@eecs.umich.edu 9087615Sminkyu.jeong@arm.comstd::string 9097639Sgblack@eecs.umich.eduMicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9107639Sgblack@eecs.umich.edu{ 9117639Sgblack@eecs.umich.edu std::stringstream ss; 9127639Sgblack@eecs.umich.edu printMnemonic(ss); 9137639Sgblack@eecs.umich.edu printReg(ss, ura); 9147639Sgblack@eecs.umich.edu ss << ", "; 9157639Sgblack@eecs.umich.edu printReg(ss, urb); 9167639Sgblack@eecs.umich.edu ss << ", "; 9177639Sgblack@eecs.umich.edu ccprintf(ss, "#%d", imm); 9187639Sgblack@eecs.umich.edu return ss.str(); 9197639Sgblack@eecs.umich.edu} 9207639Sgblack@eecs.umich.edu 9217639Sgblack@eecs.umich.edustd::string 9228140SMatt.Horsnell@arm.comMicroSetPCCPSR::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9238140SMatt.Horsnell@arm.com{ 9248140SMatt.Horsnell@arm.com std::stringstream ss; 9258140SMatt.Horsnell@arm.com printMnemonic(ss); 9268140SMatt.Horsnell@arm.com ss << "[PC,CPSR]"; 9278140SMatt.Horsnell@arm.com return ss.str(); 9288140SMatt.Horsnell@arm.com} 9298140SMatt.Horsnell@arm.com 9308140SMatt.Horsnell@arm.comstd::string 9317646Sgene.wu@arm.comMicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9327646Sgene.wu@arm.com{ 9337646Sgene.wu@arm.com std::stringstream ss; 9347646Sgene.wu@arm.com printMnemonic(ss); 9357646Sgene.wu@arm.com printReg(ss, ura); 9367646Sgene.wu@arm.com ss << ", "; 9377646Sgene.wu@arm.com printReg(ss, urb); 9387646Sgene.wu@arm.com return ss.str(); 9397646Sgene.wu@arm.com} 9407646Sgene.wu@arm.com 9417646Sgene.wu@arm.comstd::string 9427615Sminkyu.jeong@arm.comMicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9437615Sminkyu.jeong@arm.com{ 9447615Sminkyu.jeong@arm.com std::stringstream ss; 9457615Sminkyu.jeong@arm.com printMnemonic(ss); 9467615Sminkyu.jeong@arm.com printReg(ss, ura); 9477615Sminkyu.jeong@arm.com ss << ", "; 9487615Sminkyu.jeong@arm.com printReg(ss, urb); 9497615Sminkyu.jeong@arm.com ss << ", "; 9507639Sgblack@eecs.umich.edu printReg(ss, urc); 9517615Sminkyu.jeong@arm.com return ss.str(); 9527175Sgblack@eecs.umich.edu} 9537615Sminkyu.jeong@arm.com 9547615Sminkyu.jeong@arm.comstd::string 9557615Sminkyu.jeong@arm.comMicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9567615Sminkyu.jeong@arm.com{ 9577615Sminkyu.jeong@arm.com std::stringstream ss; 9587615Sminkyu.jeong@arm.com printMnemonic(ss); 9597615Sminkyu.jeong@arm.com printReg(ss, ura); 9607615Sminkyu.jeong@arm.com ss << ", ["; 9617615Sminkyu.jeong@arm.com printReg(ss, urb); 9627615Sminkyu.jeong@arm.com ss << ", "; 9637615Sminkyu.jeong@arm.com ccprintf(ss, "#%d", imm); 9647615Sminkyu.jeong@arm.com ss << "]"; 9657615Sminkyu.jeong@arm.com return ss.str(); 9667615Sminkyu.jeong@arm.com} 9677615Sminkyu.jeong@arm.com 9687615Sminkyu.jeong@arm.com} 969