macromem.cc revision 7853
17170Sgblack@eecs.umich.edu/* 27170Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37170Sgblack@eecs.umich.edu * All rights reserved 47170Sgblack@eecs.umich.edu * 57170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137170Sgblack@eecs.umich.edu * 147170Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157170Sgblack@eecs.umich.edu * All rights reserved. 167170Sgblack@eecs.umich.edu * 177170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267170Sgblack@eecs.umich.edu * this software without specific prior written permission. 277170Sgblack@eecs.umich.edu * 287170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397170Sgblack@eecs.umich.edu * 407170Sgblack@eecs.umich.edu * Authors: Stephen Hines 417170Sgblack@eecs.umich.edu */ 427170Sgblack@eecs.umich.edu 437170Sgblack@eecs.umich.edu#include "arch/arm/insts/macromem.hh" 447170Sgblack@eecs.umich.edu#include "arch/arm/decoder.hh" 457853SMatt.Horsnell@ARM.com#include <sstream> 467170Sgblack@eecs.umich.edu 477853SMatt.Horsnell@ARM.comusing namespace std; 487170Sgblack@eecs.umich.eduusing namespace ArmISAInst; 497170Sgblack@eecs.umich.edu 507170Sgblack@eecs.umich.edunamespace ArmISA 517170Sgblack@eecs.umich.edu{ 527170Sgblack@eecs.umich.edu 537170Sgblack@eecs.umich.eduMacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, 547170Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 557170Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, 567170Sgblack@eecs.umich.edu bool load, uint32_t reglist) : 577170Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 587170Sgblack@eecs.umich.edu{ 597170Sgblack@eecs.umich.edu uint32_t regs = reglist; 607170Sgblack@eecs.umich.edu uint32_t ones = number_of_ones(reglist); 617170Sgblack@eecs.umich.edu // Remember that writeback adds a uop 627170Sgblack@eecs.umich.edu numMicroops = ones + (writeback ? 1 : 0) + 1; 637170Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 647170Sgblack@eecs.umich.edu uint32_t addr = 0; 657170Sgblack@eecs.umich.edu 667170Sgblack@eecs.umich.edu if (!up) 677170Sgblack@eecs.umich.edu addr = (ones << 2) - 4; 687170Sgblack@eecs.umich.edu 697170Sgblack@eecs.umich.edu if (!index) 707170Sgblack@eecs.umich.edu addr += 4; 717170Sgblack@eecs.umich.edu 727190Sgblack@eecs.umich.edu StaticInstPtr *uop = microOps; 737190Sgblack@eecs.umich.edu StaticInstPtr wbUop; 747190Sgblack@eecs.umich.edu if (writeback) { 757190Sgblack@eecs.umich.edu if (up) { 767190Sgblack@eecs.umich.edu wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4); 777190Sgblack@eecs.umich.edu } else { 787190Sgblack@eecs.umich.edu wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4); 797190Sgblack@eecs.umich.edu } 807190Sgblack@eecs.umich.edu } 817190Sgblack@eecs.umich.edu 827170Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in ureg0. 837170Sgblack@eecs.umich.edu // This is equivalent to a move. 847190Sgblack@eecs.umich.edu *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 857190Sgblack@eecs.umich.edu 867190Sgblack@eecs.umich.edu // Write back at the start for loads. This covers the ldm exception return 877190Sgblack@eecs.umich.edu // case where the base needs to be written in the old mode. Stores may need 887190Sgblack@eecs.umich.edu // the original value of the base, but they don't change mode and can 897190Sgblack@eecs.umich.edu // write back at the end like before. 907190Sgblack@eecs.umich.edu if (load && writeback) { 917190Sgblack@eecs.umich.edu *++uop = wbUop; 927190Sgblack@eecs.umich.edu } 937170Sgblack@eecs.umich.edu 947170Sgblack@eecs.umich.edu unsigned reg = 0; 957170Sgblack@eecs.umich.edu bool force_user = user & !bits(reglist, 15); 967170Sgblack@eecs.umich.edu bool exception_ret = user & bits(reglist, 15); 977170Sgblack@eecs.umich.edu 987190Sgblack@eecs.umich.edu for (int i = 0; i < ones; i++) { 997170Sgblack@eecs.umich.edu // Find the next register. 1007170Sgblack@eecs.umich.edu while (!bits(regs, reg)) 1017170Sgblack@eecs.umich.edu reg++; 1027170Sgblack@eecs.umich.edu replaceBits(regs, reg, 0); 1037170Sgblack@eecs.umich.edu 1047170Sgblack@eecs.umich.edu unsigned regIdx = reg; 1057170Sgblack@eecs.umich.edu if (force_user) { 1067310Sgblack@eecs.umich.edu regIdx = intRegInMode(MODE_USER, regIdx); 1077170Sgblack@eecs.umich.edu } 1087170Sgblack@eecs.umich.edu 1097170Sgblack@eecs.umich.edu if (load) { 1107170Sgblack@eecs.umich.edu if (reg == INTREG_PC && exception_ret) { 1117170Sgblack@eecs.umich.edu // This must be the exception return form of ldm. 1127190Sgblack@eecs.umich.edu *++uop = new MicroLdrRetUop(machInst, regIdx, 1137190Sgblack@eecs.umich.edu INTREG_UREG0, up, addr); 1147170Sgblack@eecs.umich.edu } else { 1157190Sgblack@eecs.umich.edu *++uop = new MicroLdrUop(machInst, regIdx, 1167190Sgblack@eecs.umich.edu INTREG_UREG0, up, addr); 1177170Sgblack@eecs.umich.edu } 1187170Sgblack@eecs.umich.edu } else { 1197190Sgblack@eecs.umich.edu *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1207170Sgblack@eecs.umich.edu } 1217170Sgblack@eecs.umich.edu 1227170Sgblack@eecs.umich.edu if (up) 1237170Sgblack@eecs.umich.edu addr += 4; 1247170Sgblack@eecs.umich.edu else 1257170Sgblack@eecs.umich.edu addr -= 4; 1267170Sgblack@eecs.umich.edu } 1277170Sgblack@eecs.umich.edu 1287190Sgblack@eecs.umich.edu if (!load && writeback) { 1297190Sgblack@eecs.umich.edu *++uop = wbUop; 1307170Sgblack@eecs.umich.edu } 1317190Sgblack@eecs.umich.edu 1327190Sgblack@eecs.umich.edu (*uop)->setLastMicroop(); 1337343Sgblack@eecs.umich.edu 1347343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 1357343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 1367343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 1377343Sgblack@eecs.umich.edu assert(uopPtr); 1387343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 1397343Sgblack@eecs.umich.edu } 1407170Sgblack@eecs.umich.edu} 1417170Sgblack@eecs.umich.edu 1427639Sgblack@eecs.umich.eduVldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1437639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 1447639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 1457639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 1467639Sgblack@eecs.umich.edu{ 1477639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 1487639Sgblack@eecs.umich.edu assert(regs % elems == 0); 1497639Sgblack@eecs.umich.edu 1507639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 1517639Sgblack@eecs.umich.edu bool wb = (rm != 15); 1527639Sgblack@eecs.umich.edu bool deinterleave = (elems > 1); 1537639Sgblack@eecs.umich.edu 1547639Sgblack@eecs.umich.edu if (wb) numMicroops++; 1557639Sgblack@eecs.umich.edu if (deinterleave) numMicroops += (regs / elems); 1567639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1577639Sgblack@eecs.umich.edu 1587639Sgblack@eecs.umich.edu RegIndex rMid = deinterleave ? NumFloatArchRegs : vd * 2; 1597639Sgblack@eecs.umich.edu 1607639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 1617639Sgblack@eecs.umich.edu 1627639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 1637639Sgblack@eecs.umich.edu switch (regs) { 1647639Sgblack@eecs.umich.edu case 4: 1657639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1667639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1677639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1687639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1697639Sgblack@eecs.umich.edu break; 1707639Sgblack@eecs.umich.edu case 3: 1717639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1727639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1737639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 1747639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1757639Sgblack@eecs.umich.edu break; 1767639Sgblack@eecs.umich.edu case 2: 1777639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1787639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1797639Sgblack@eecs.umich.edu break; 1807639Sgblack@eecs.umich.edu case 1: 1817639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 1827639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1837639Sgblack@eecs.umich.edu break; 1847639Sgblack@eecs.umich.edu default: 1857853SMatt.Horsnell@ARM.com // Unknown number of registers 1867853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 1877639Sgblack@eecs.umich.edu } 1887639Sgblack@eecs.umich.edu if (wb) { 1897639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 1907639Sgblack@eecs.umich.edu microOps[uopIdx++] = 1917646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 1927639Sgblack@eecs.umich.edu } else { 1937639Sgblack@eecs.umich.edu microOps[uopIdx++] = 1947639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 1957639Sgblack@eecs.umich.edu } 1967639Sgblack@eecs.umich.edu } 1977639Sgblack@eecs.umich.edu if (deinterleave) { 1987639Sgblack@eecs.umich.edu switch (elems) { 1997639Sgblack@eecs.umich.edu case 4: 2007639Sgblack@eecs.umich.edu assert(regs == 4); 2017639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon8Uop>( 2027639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2037639Sgblack@eecs.umich.edu break; 2047639Sgblack@eecs.umich.edu case 3: 2057639Sgblack@eecs.umich.edu assert(regs == 3); 2067639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon6Uop>( 2077639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2087639Sgblack@eecs.umich.edu break; 2097639Sgblack@eecs.umich.edu case 2: 2107639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 2117639Sgblack@eecs.umich.edu if (regs == 4) { 2127639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2137639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2147639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2157639Sgblack@eecs.umich.edu size, machInst, vd * 2 + 2, rMid + 4, inc * 2); 2167639Sgblack@eecs.umich.edu } else { 2177639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2187639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2197639Sgblack@eecs.umich.edu } 2207639Sgblack@eecs.umich.edu break; 2217639Sgblack@eecs.umich.edu default: 2227853SMatt.Horsnell@ARM.com // Bad number of elements to deinterleave 2237853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 2247639Sgblack@eecs.umich.edu } 2257639Sgblack@eecs.umich.edu } 2267639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 2277639Sgblack@eecs.umich.edu 2287639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 2297639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 2307639Sgblack@eecs.umich.edu assert(uopPtr); 2317639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 2327639Sgblack@eecs.umich.edu } 2337639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 2347639Sgblack@eecs.umich.edu} 2357639Sgblack@eecs.umich.edu 2367639Sgblack@eecs.umich.eduVldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, 2377639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 2387639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 2397639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 2407639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 2417639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 2427639Sgblack@eecs.umich.edu{ 2437639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 2447639Sgblack@eecs.umich.edu assert(regs % elems == 0); 2457639Sgblack@eecs.umich.edu 2467639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 2477639Sgblack@eecs.umich.edu unsigned loadSize = eBytes * elems; 2487639Sgblack@eecs.umich.edu unsigned loadRegs M5_VAR_USED = (loadSize + sizeof(FloatRegBits) - 1) / 2497639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 2507639Sgblack@eecs.umich.edu 2517639Sgblack@eecs.umich.edu assert(loadRegs > 0 && loadRegs <= 4); 2527639Sgblack@eecs.umich.edu 2537639Sgblack@eecs.umich.edu numMicroops = 1; 2547639Sgblack@eecs.umich.edu bool wb = (rm != 15); 2557639Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edu if (wb) numMicroops++; 2577639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 2587639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 2597639Sgblack@eecs.umich.edu 2607639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 2617639Sgblack@eecs.umich.edu 2627639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 2637639Sgblack@eecs.umich.edu switch (loadSize) { 2647639Sgblack@eecs.umich.edu case 1: 2657639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon1Uop<uint8_t>( 2667639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2677639Sgblack@eecs.umich.edu break; 2687639Sgblack@eecs.umich.edu case 2: 2697639Sgblack@eecs.umich.edu if (eBytes == 2) { 2707639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint16_t>( 2717639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2727639Sgblack@eecs.umich.edu } else { 2737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint8_t>( 2747639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2757639Sgblack@eecs.umich.edu } 2767639Sgblack@eecs.umich.edu break; 2777639Sgblack@eecs.umich.edu case 3: 2787639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon3Uop<uint8_t>( 2797639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2807639Sgblack@eecs.umich.edu break; 2817639Sgblack@eecs.umich.edu case 4: 2827639Sgblack@eecs.umich.edu switch (eBytes) { 2837639Sgblack@eecs.umich.edu case 1: 2847639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint8_t>( 2857639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2867639Sgblack@eecs.umich.edu break; 2877639Sgblack@eecs.umich.edu case 2: 2887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint16_t>( 2897639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2907639Sgblack@eecs.umich.edu break; 2917639Sgblack@eecs.umich.edu case 4: 2927639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint32_t>( 2937639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2947639Sgblack@eecs.umich.edu break; 2957639Sgblack@eecs.umich.edu } 2967639Sgblack@eecs.umich.edu break; 2977639Sgblack@eecs.umich.edu case 6: 2987639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon6Uop<uint16_t>( 2997639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3007639Sgblack@eecs.umich.edu break; 3017639Sgblack@eecs.umich.edu case 8: 3027639Sgblack@eecs.umich.edu switch (eBytes) { 3037639Sgblack@eecs.umich.edu case 2: 3047639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint16_t>( 3057639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3067639Sgblack@eecs.umich.edu break; 3077639Sgblack@eecs.umich.edu case 4: 3087639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint32_t>( 3097639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3107639Sgblack@eecs.umich.edu break; 3117639Sgblack@eecs.umich.edu } 3127639Sgblack@eecs.umich.edu break; 3137639Sgblack@eecs.umich.edu case 12: 3147639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon12Uop<uint32_t>( 3157639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3167639Sgblack@eecs.umich.edu break; 3177639Sgblack@eecs.umich.edu case 16: 3187639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon16Uop<uint32_t>( 3197639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3207639Sgblack@eecs.umich.edu break; 3217639Sgblack@eecs.umich.edu default: 3227853SMatt.Horsnell@ARM.com // Unrecognized load size 3237853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3247639Sgblack@eecs.umich.edu } 3257639Sgblack@eecs.umich.edu if (wb) { 3267639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 3277639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3287646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 3297639Sgblack@eecs.umich.edu } else { 3307639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3317639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, loadSize); 3327639Sgblack@eecs.umich.edu } 3337639Sgblack@eecs.umich.edu } 3347639Sgblack@eecs.umich.edu switch (elems) { 3357639Sgblack@eecs.umich.edu case 4: 3367639Sgblack@eecs.umich.edu assert(regs == 4); 3377639Sgblack@eecs.umich.edu switch (size) { 3387639Sgblack@eecs.umich.edu case 0: 3397639Sgblack@eecs.umich.edu if (all) { 3407639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint8_t>( 3417639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3427639Sgblack@eecs.umich.edu } else { 3437639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint8_t>( 3447639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3457639Sgblack@eecs.umich.edu } 3467639Sgblack@eecs.umich.edu break; 3477639Sgblack@eecs.umich.edu case 1: 3487639Sgblack@eecs.umich.edu if (all) { 3497639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint16_t>( 3507639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3517639Sgblack@eecs.umich.edu } else { 3527639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint16_t>( 3537639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3547639Sgblack@eecs.umich.edu } 3557639Sgblack@eecs.umich.edu break; 3567639Sgblack@eecs.umich.edu case 2: 3577639Sgblack@eecs.umich.edu if (all) { 3587639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to8Uop<uint32_t>( 3597639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3607639Sgblack@eecs.umich.edu } else { 3617639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to8Uop<uint32_t>( 3627639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3637639Sgblack@eecs.umich.edu } 3647639Sgblack@eecs.umich.edu break; 3657639Sgblack@eecs.umich.edu default: 3667853SMatt.Horsnell@ARM.com // Bad size 3677853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 3687639Sgblack@eecs.umich.edu break; 3697639Sgblack@eecs.umich.edu } 3707639Sgblack@eecs.umich.edu break; 3717639Sgblack@eecs.umich.edu case 3: 3727639Sgblack@eecs.umich.edu assert(regs == 3); 3737639Sgblack@eecs.umich.edu switch (size) { 3747639Sgblack@eecs.umich.edu case 0: 3757639Sgblack@eecs.umich.edu if (all) { 3767639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint8_t>( 3777639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3787639Sgblack@eecs.umich.edu } else { 3797639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint8_t>( 3807639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3817639Sgblack@eecs.umich.edu } 3827639Sgblack@eecs.umich.edu break; 3837639Sgblack@eecs.umich.edu case 1: 3847639Sgblack@eecs.umich.edu if (all) { 3857639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint16_t>( 3867639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3877639Sgblack@eecs.umich.edu } else { 3887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint16_t>( 3897639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3907639Sgblack@eecs.umich.edu } 3917639Sgblack@eecs.umich.edu break; 3927639Sgblack@eecs.umich.edu case 2: 3937639Sgblack@eecs.umich.edu if (all) { 3947639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to6Uop<uint32_t>( 3957639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3967639Sgblack@eecs.umich.edu } else { 3977639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to6Uop<uint32_t>( 3987639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3997639Sgblack@eecs.umich.edu } 4007639Sgblack@eecs.umich.edu break; 4017639Sgblack@eecs.umich.edu default: 4027853SMatt.Horsnell@ARM.com // Bad size 4037853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4047639Sgblack@eecs.umich.edu break; 4057639Sgblack@eecs.umich.edu } 4067639Sgblack@eecs.umich.edu break; 4077639Sgblack@eecs.umich.edu case 2: 4087639Sgblack@eecs.umich.edu assert(regs == 2); 4097639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4107639Sgblack@eecs.umich.edu switch (size) { 4117639Sgblack@eecs.umich.edu case 0: 4127639Sgblack@eecs.umich.edu if (all) { 4137639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint8_t>( 4147639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4157639Sgblack@eecs.umich.edu } else { 4167639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint8_t>( 4177639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4187639Sgblack@eecs.umich.edu } 4197639Sgblack@eecs.umich.edu break; 4207639Sgblack@eecs.umich.edu case 1: 4217639Sgblack@eecs.umich.edu if (all) { 4227639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint16_t>( 4237639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4247639Sgblack@eecs.umich.edu } else { 4257639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint16_t>( 4267639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4277639Sgblack@eecs.umich.edu } 4287639Sgblack@eecs.umich.edu break; 4297639Sgblack@eecs.umich.edu case 2: 4307639Sgblack@eecs.umich.edu if (all) { 4317639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint32_t>( 4327639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4337639Sgblack@eecs.umich.edu } else { 4347639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint32_t>( 4357639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4367639Sgblack@eecs.umich.edu } 4377639Sgblack@eecs.umich.edu break; 4387639Sgblack@eecs.umich.edu default: 4397853SMatt.Horsnell@ARM.com // Bad size 4407853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4417639Sgblack@eecs.umich.edu break; 4427639Sgblack@eecs.umich.edu } 4437639Sgblack@eecs.umich.edu break; 4447639Sgblack@eecs.umich.edu case 1: 4457639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 4467639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4477639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 4487639Sgblack@eecs.umich.edu switch (size) { 4497639Sgblack@eecs.umich.edu case 0: 4507639Sgblack@eecs.umich.edu if (all) { 4517639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4527639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint8_t>( 4537639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4547639Sgblack@eecs.umich.edu } else { 4557639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4567639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint8_t>( 4577639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4587639Sgblack@eecs.umich.edu } 4597639Sgblack@eecs.umich.edu break; 4607639Sgblack@eecs.umich.edu case 1: 4617639Sgblack@eecs.umich.edu if (all) { 4627639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4637639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint16_t>( 4647639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4657639Sgblack@eecs.umich.edu } else { 4667639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4677639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint16_t>( 4687639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4697639Sgblack@eecs.umich.edu } 4707639Sgblack@eecs.umich.edu break; 4717639Sgblack@eecs.umich.edu case 2: 4727639Sgblack@eecs.umich.edu if (all) { 4737639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4747639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint32_t>( 4757639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4767639Sgblack@eecs.umich.edu } else { 4777639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4787639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint32_t>( 4797639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4807639Sgblack@eecs.umich.edu } 4817639Sgblack@eecs.umich.edu break; 4827639Sgblack@eecs.umich.edu default: 4837853SMatt.Horsnell@ARM.com // Bad size 4847853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4857639Sgblack@eecs.umich.edu break; 4867639Sgblack@eecs.umich.edu } 4877639Sgblack@eecs.umich.edu } 4887639Sgblack@eecs.umich.edu break; 4897639Sgblack@eecs.umich.edu default: 4907853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 4917853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 4927639Sgblack@eecs.umich.edu } 4937639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 4947639Sgblack@eecs.umich.edu 4957639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 4967639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 4977639Sgblack@eecs.umich.edu assert(uopPtr); 4987639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 4997639Sgblack@eecs.umich.edu } 5007639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 5017639Sgblack@eecs.umich.edu} 5027639Sgblack@eecs.umich.edu 5037639Sgblack@eecs.umich.eduVstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 5047639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 5057639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 5067639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 5077639Sgblack@eecs.umich.edu{ 5087639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 5097639Sgblack@eecs.umich.edu assert(regs % elems == 0); 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 5127639Sgblack@eecs.umich.edu bool wb = (rm != 15); 5137639Sgblack@eecs.umich.edu bool interleave = (elems > 1); 5147639Sgblack@eecs.umich.edu 5157639Sgblack@eecs.umich.edu if (wb) numMicroops++; 5167639Sgblack@eecs.umich.edu if (interleave) numMicroops += (regs / elems); 5177639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 5187639Sgblack@eecs.umich.edu 5197639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 5207639Sgblack@eecs.umich.edu 5217639Sgblack@eecs.umich.edu RegIndex rMid = interleave ? NumFloatArchRegs : vd * 2; 5227639Sgblack@eecs.umich.edu 5237639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 5247639Sgblack@eecs.umich.edu if (interleave) { 5257639Sgblack@eecs.umich.edu switch (elems) { 5267639Sgblack@eecs.umich.edu case 4: 5277639Sgblack@eecs.umich.edu assert(regs == 4); 5287639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon8Uop>( 5297639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5307639Sgblack@eecs.umich.edu break; 5317639Sgblack@eecs.umich.edu case 3: 5327639Sgblack@eecs.umich.edu assert(regs == 3); 5337639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon6Uop>( 5347639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5357639Sgblack@eecs.umich.edu break; 5367639Sgblack@eecs.umich.edu case 2: 5377639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 5387639Sgblack@eecs.umich.edu if (regs == 4) { 5397639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5407639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5417639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5427639Sgblack@eecs.umich.edu size, machInst, rMid + 4, vd * 2 + 2, inc * 2); 5437639Sgblack@eecs.umich.edu } else { 5447639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5457639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5467639Sgblack@eecs.umich.edu } 5477639Sgblack@eecs.umich.edu break; 5487639Sgblack@eecs.umich.edu default: 5497853SMatt.Horsnell@ARM.com // Bad number of elements to interleave 5507853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5517639Sgblack@eecs.umich.edu } 5527639Sgblack@eecs.umich.edu } 5537639Sgblack@eecs.umich.edu switch (regs) { 5547639Sgblack@eecs.umich.edu case 4: 5557639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5567639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5577639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5587639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5597639Sgblack@eecs.umich.edu break; 5607639Sgblack@eecs.umich.edu case 3: 5617639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5627639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5637639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5647639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5657639Sgblack@eecs.umich.edu break; 5667639Sgblack@eecs.umich.edu case 2: 5677639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5687639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5697639Sgblack@eecs.umich.edu break; 5707639Sgblack@eecs.umich.edu case 1: 5717639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5727639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5737639Sgblack@eecs.umich.edu break; 5747639Sgblack@eecs.umich.edu default: 5757853SMatt.Horsnell@ARM.com // Unknown number of registers 5767853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 5777639Sgblack@eecs.umich.edu } 5787639Sgblack@eecs.umich.edu if (wb) { 5797639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 5807639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5817646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 5827639Sgblack@eecs.umich.edu } else { 5837639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5847639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 5857639Sgblack@eecs.umich.edu } 5867639Sgblack@eecs.umich.edu } 5877639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 5887639Sgblack@eecs.umich.edu 5897639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 5907639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 5917639Sgblack@eecs.umich.edu assert(uopPtr); 5927639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 5937639Sgblack@eecs.umich.edu } 5947639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 5957639Sgblack@eecs.umich.edu} 5967639Sgblack@eecs.umich.edu 5977639Sgblack@eecs.umich.eduVstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, 5987639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 5997639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 6007639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 6017639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 6027639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 6037639Sgblack@eecs.umich.edu{ 6047639Sgblack@eecs.umich.edu assert(!all); 6057639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 6067639Sgblack@eecs.umich.edu assert(regs % elems == 0); 6077639Sgblack@eecs.umich.edu 6087639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 6097639Sgblack@eecs.umich.edu unsigned storeSize = eBytes * elems; 6107639Sgblack@eecs.umich.edu unsigned storeRegs M5_VAR_USED = (storeSize + sizeof(FloatRegBits) - 1) / 6117639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 6127639Sgblack@eecs.umich.edu 6137639Sgblack@eecs.umich.edu assert(storeRegs > 0 && storeRegs <= 4); 6147639Sgblack@eecs.umich.edu 6157639Sgblack@eecs.umich.edu numMicroops = 1; 6167639Sgblack@eecs.umich.edu bool wb = (rm != 15); 6177639Sgblack@eecs.umich.edu 6187639Sgblack@eecs.umich.edu if (wb) numMicroops++; 6197639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 6207639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 6217639Sgblack@eecs.umich.edu 6227639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 6237639Sgblack@eecs.umich.edu 6247639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 6257639Sgblack@eecs.umich.edu switch (elems) { 6267639Sgblack@eecs.umich.edu case 4: 6277639Sgblack@eecs.umich.edu assert(regs == 4); 6287639Sgblack@eecs.umich.edu switch (size) { 6297639Sgblack@eecs.umich.edu case 0: 6307639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint8_t>( 6317639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6327639Sgblack@eecs.umich.edu break; 6337639Sgblack@eecs.umich.edu case 1: 6347639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint16_t>( 6357639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6367639Sgblack@eecs.umich.edu break; 6377639Sgblack@eecs.umich.edu case 2: 6387639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to4Uop<uint32_t>( 6397639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6407639Sgblack@eecs.umich.edu break; 6417639Sgblack@eecs.umich.edu default: 6427853SMatt.Horsnell@ARM.com // Bad size 6437853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6447639Sgblack@eecs.umich.edu break; 6457639Sgblack@eecs.umich.edu } 6467639Sgblack@eecs.umich.edu break; 6477639Sgblack@eecs.umich.edu case 3: 6487639Sgblack@eecs.umich.edu assert(regs == 3); 6497639Sgblack@eecs.umich.edu switch (size) { 6507639Sgblack@eecs.umich.edu case 0: 6517639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint8_t>( 6527639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6537639Sgblack@eecs.umich.edu break; 6547639Sgblack@eecs.umich.edu case 1: 6557639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint16_t>( 6567639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6577639Sgblack@eecs.umich.edu break; 6587639Sgblack@eecs.umich.edu case 2: 6597639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to4Uop<uint32_t>( 6607639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6617639Sgblack@eecs.umich.edu break; 6627639Sgblack@eecs.umich.edu default: 6637853SMatt.Horsnell@ARM.com // Bad size 6647853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6657639Sgblack@eecs.umich.edu break; 6667639Sgblack@eecs.umich.edu } 6677639Sgblack@eecs.umich.edu break; 6687639Sgblack@eecs.umich.edu case 2: 6697639Sgblack@eecs.umich.edu assert(regs == 2); 6707639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 6717639Sgblack@eecs.umich.edu switch (size) { 6727639Sgblack@eecs.umich.edu case 0: 6737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint8_t>( 6747639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6757639Sgblack@eecs.umich.edu break; 6767639Sgblack@eecs.umich.edu case 1: 6777639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint16_t>( 6787639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6797639Sgblack@eecs.umich.edu break; 6807639Sgblack@eecs.umich.edu case 2: 6817639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint32_t>( 6827639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6837639Sgblack@eecs.umich.edu break; 6847639Sgblack@eecs.umich.edu default: 6857853SMatt.Horsnell@ARM.com // Bad size 6867853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 6877639Sgblack@eecs.umich.edu break; 6887639Sgblack@eecs.umich.edu } 6897639Sgblack@eecs.umich.edu break; 6907639Sgblack@eecs.umich.edu case 1: 6917639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 6927639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 6937639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 6947639Sgblack@eecs.umich.edu switch (size) { 6957639Sgblack@eecs.umich.edu case 0: 6967639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint8_t>( 6977639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 6987639Sgblack@eecs.umich.edu break; 6997639Sgblack@eecs.umich.edu case 1: 7007639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint16_t>( 7017639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7027639Sgblack@eecs.umich.edu break; 7037639Sgblack@eecs.umich.edu case 2: 7047639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint32_t>( 7057639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 7067639Sgblack@eecs.umich.edu break; 7077639Sgblack@eecs.umich.edu default: 7087853SMatt.Horsnell@ARM.com // Bad size 7097853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7107639Sgblack@eecs.umich.edu break; 7117639Sgblack@eecs.umich.edu } 7127639Sgblack@eecs.umich.edu } 7137639Sgblack@eecs.umich.edu break; 7147639Sgblack@eecs.umich.edu default: 7157853SMatt.Horsnell@ARM.com // Bad number of elements to unpack 7167853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7177639Sgblack@eecs.umich.edu } 7187639Sgblack@eecs.umich.edu switch (storeSize) { 7197639Sgblack@eecs.umich.edu case 1: 7207639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon1Uop<uint8_t>( 7217639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7227639Sgblack@eecs.umich.edu break; 7237639Sgblack@eecs.umich.edu case 2: 7247639Sgblack@eecs.umich.edu if (eBytes == 2) { 7257639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint16_t>( 7267639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7277639Sgblack@eecs.umich.edu } else { 7287639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint8_t>( 7297639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7307639Sgblack@eecs.umich.edu } 7317639Sgblack@eecs.umich.edu break; 7327639Sgblack@eecs.umich.edu case 3: 7337639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon3Uop<uint8_t>( 7347639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7357639Sgblack@eecs.umich.edu break; 7367639Sgblack@eecs.umich.edu case 4: 7377639Sgblack@eecs.umich.edu switch (eBytes) { 7387639Sgblack@eecs.umich.edu case 1: 7397639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint8_t>( 7407639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7417639Sgblack@eecs.umich.edu break; 7427639Sgblack@eecs.umich.edu case 2: 7437639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint16_t>( 7447639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7457639Sgblack@eecs.umich.edu break; 7467639Sgblack@eecs.umich.edu case 4: 7477639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint32_t>( 7487639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7497639Sgblack@eecs.umich.edu break; 7507639Sgblack@eecs.umich.edu } 7517639Sgblack@eecs.umich.edu break; 7527639Sgblack@eecs.umich.edu case 6: 7537639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon6Uop<uint16_t>( 7547639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7557639Sgblack@eecs.umich.edu break; 7567639Sgblack@eecs.umich.edu case 8: 7577639Sgblack@eecs.umich.edu switch (eBytes) { 7587639Sgblack@eecs.umich.edu case 2: 7597639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint16_t>( 7607639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7617639Sgblack@eecs.umich.edu break; 7627639Sgblack@eecs.umich.edu case 4: 7637639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint32_t>( 7647639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7657639Sgblack@eecs.umich.edu break; 7667639Sgblack@eecs.umich.edu } 7677639Sgblack@eecs.umich.edu break; 7687639Sgblack@eecs.umich.edu case 12: 7697639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon12Uop<uint32_t>( 7707639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7717639Sgblack@eecs.umich.edu break; 7727639Sgblack@eecs.umich.edu case 16: 7737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon16Uop<uint32_t>( 7747639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7757639Sgblack@eecs.umich.edu break; 7767639Sgblack@eecs.umich.edu default: 7777853SMatt.Horsnell@ARM.com // Bad store size 7787853SMatt.Horsnell@ARM.com microOps[uopIdx++] = new Unknown(machInst); 7797639Sgblack@eecs.umich.edu } 7807639Sgblack@eecs.umich.edu if (wb) { 7817639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 7827639Sgblack@eecs.umich.edu microOps[uopIdx++] = 7837646Sgene.wu@arm.com new MicroAddUop(machInst, rn, rn, rm, 0, ArmISA::LSL); 7847639Sgblack@eecs.umich.edu } else { 7857639Sgblack@eecs.umich.edu microOps[uopIdx++] = 7867639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, storeSize); 7877639Sgblack@eecs.umich.edu } 7887639Sgblack@eecs.umich.edu } 7897639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 7907639Sgblack@eecs.umich.edu 7917639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 7927639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 7937639Sgblack@eecs.umich.edu assert(uopPtr); 7947639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 7957639Sgblack@eecs.umich.edu } 7967639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 7977639Sgblack@eecs.umich.edu} 7987639Sgblack@eecs.umich.edu 7997175Sgblack@eecs.umich.eduMacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, 8007175Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 8017175Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, 8027175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset) : 8037175Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 8047175Sgblack@eecs.umich.edu{ 8057175Sgblack@eecs.umich.edu int i = 0; 8067175Sgblack@eecs.umich.edu 8077175Sgblack@eecs.umich.edu // The lowest order bit selects fldmx (set) or fldmd (clear). These seem 8087175Sgblack@eecs.umich.edu // to be functionally identical except that fldmx is deprecated. For now 8097175Sgblack@eecs.umich.edu // we'll assume they're otherwise interchangable. 8107175Sgblack@eecs.umich.edu int count = (single ? offset : (offset / 2)); 8117175Sgblack@eecs.umich.edu if (count == 0 || count > NumFloatArchRegs) 8127175Sgblack@eecs.umich.edu warn_once("Bad offset field for VFP load/store multiple.\n"); 8137175Sgblack@eecs.umich.edu if (count == 0) { 8147175Sgblack@eecs.umich.edu // Force there to be at least one microop so the macroop makes sense. 8157175Sgblack@eecs.umich.edu writeback = true; 8167175Sgblack@eecs.umich.edu } 8177175Sgblack@eecs.umich.edu if (count > NumFloatArchRegs) 8187175Sgblack@eecs.umich.edu count = NumFloatArchRegs; 8197175Sgblack@eecs.umich.edu 8207342Sgblack@eecs.umich.edu numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0); 8217342Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 8227342Sgblack@eecs.umich.edu 8237395Sgblack@eecs.umich.edu int64_t addr = 0; 8247175Sgblack@eecs.umich.edu 8257342Sgblack@eecs.umich.edu if (!up) 8267342Sgblack@eecs.umich.edu addr = 4 * offset; 8277175Sgblack@eecs.umich.edu 8287342Sgblack@eecs.umich.edu bool tempUp = up; 8297175Sgblack@eecs.umich.edu for (int j = 0; j < count; j++) { 8307175Sgblack@eecs.umich.edu if (load) { 8317639Sgblack@eecs.umich.edu if (single) { 8327639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, 8337639Sgblack@eecs.umich.edu tempUp, addr); 8347639Sgblack@eecs.umich.edu } else { 8357639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDBFpUop(machInst, vd++, rn, 8367639Sgblack@eecs.umich.edu tempUp, addr); 8377639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDTFpUop(machInst, vd++, rn, tempUp, 8387639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8397639Sgblack@eecs.umich.edu } 8407175Sgblack@eecs.umich.edu } else { 8417639Sgblack@eecs.umich.edu if (single) { 8427639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, 8437639Sgblack@eecs.umich.edu tempUp, addr); 8447639Sgblack@eecs.umich.edu } else { 8457639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDBFpUop(machInst, vd++, rn, 8467639Sgblack@eecs.umich.edu tempUp, addr); 8477639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDTFpUop(machInst, vd++, rn, tempUp, 8487639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8497639Sgblack@eecs.umich.edu } 8507175Sgblack@eecs.umich.edu } 8517342Sgblack@eecs.umich.edu if (!tempUp) { 8527342Sgblack@eecs.umich.edu addr -= (single ? 4 : 8); 8537342Sgblack@eecs.umich.edu // The microops don't handle negative displacement, so turn if we 8547342Sgblack@eecs.umich.edu // hit zero, flip polarity and start adding. 8557395Sgblack@eecs.umich.edu if (addr <= 0) { 8567342Sgblack@eecs.umich.edu tempUp = true; 8577395Sgblack@eecs.umich.edu addr = -addr; 8587342Sgblack@eecs.umich.edu } 8597342Sgblack@eecs.umich.edu } else { 8607342Sgblack@eecs.umich.edu addr += (single ? 4 : 8); 8617342Sgblack@eecs.umich.edu } 8627175Sgblack@eecs.umich.edu } 8637175Sgblack@eecs.umich.edu 8647175Sgblack@eecs.umich.edu if (writeback) { 8657175Sgblack@eecs.umich.edu if (up) { 8667175Sgblack@eecs.umich.edu microOps[i++] = 8677175Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, 4 * offset); 8687175Sgblack@eecs.umich.edu } else { 8697175Sgblack@eecs.umich.edu microOps[i++] = 8707175Sgblack@eecs.umich.edu new MicroSubiUop(machInst, rn, rn, 4 * offset); 8717175Sgblack@eecs.umich.edu } 8727175Sgblack@eecs.umich.edu } 8737175Sgblack@eecs.umich.edu 8747342Sgblack@eecs.umich.edu assert(numMicroops == i); 8757175Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 8767343Sgblack@eecs.umich.edu 8777343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 8787343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 8797343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 8807343Sgblack@eecs.umich.edu assert(uopPtr); 8817343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 8827343Sgblack@eecs.umich.edu } 8837170Sgblack@eecs.umich.edu} 8847175Sgblack@eecs.umich.edu 8857615Sminkyu.jeong@arm.comstd::string 8867639Sgblack@eecs.umich.eduMicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8877639Sgblack@eecs.umich.edu{ 8887639Sgblack@eecs.umich.edu std::stringstream ss; 8897639Sgblack@eecs.umich.edu printMnemonic(ss); 8907639Sgblack@eecs.umich.edu printReg(ss, ura); 8917639Sgblack@eecs.umich.edu ss << ", "; 8927639Sgblack@eecs.umich.edu printReg(ss, urb); 8937639Sgblack@eecs.umich.edu ss << ", "; 8947639Sgblack@eecs.umich.edu ccprintf(ss, "#%d", imm); 8957639Sgblack@eecs.umich.edu return ss.str(); 8967639Sgblack@eecs.umich.edu} 8977639Sgblack@eecs.umich.edu 8987639Sgblack@eecs.umich.edustd::string 8997646Sgene.wu@arm.comMicroIntMov::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9007646Sgene.wu@arm.com{ 9017646Sgene.wu@arm.com std::stringstream ss; 9027646Sgene.wu@arm.com printMnemonic(ss); 9037646Sgene.wu@arm.com printReg(ss, ura); 9047646Sgene.wu@arm.com ss << ", "; 9057646Sgene.wu@arm.com printReg(ss, urb); 9067646Sgene.wu@arm.com return ss.str(); 9077646Sgene.wu@arm.com} 9087646Sgene.wu@arm.com 9097646Sgene.wu@arm.comstd::string 9107615Sminkyu.jeong@arm.comMicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9117615Sminkyu.jeong@arm.com{ 9127615Sminkyu.jeong@arm.com std::stringstream ss; 9137615Sminkyu.jeong@arm.com printMnemonic(ss); 9147615Sminkyu.jeong@arm.com printReg(ss, ura); 9157615Sminkyu.jeong@arm.com ss << ", "; 9167615Sminkyu.jeong@arm.com printReg(ss, urb); 9177615Sminkyu.jeong@arm.com ss << ", "; 9187639Sgblack@eecs.umich.edu printReg(ss, urc); 9197615Sminkyu.jeong@arm.com return ss.str(); 9207175Sgblack@eecs.umich.edu} 9217615Sminkyu.jeong@arm.com 9227615Sminkyu.jeong@arm.comstd::string 9237615Sminkyu.jeong@arm.comMicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 9247615Sminkyu.jeong@arm.com{ 9257615Sminkyu.jeong@arm.com std::stringstream ss; 9267615Sminkyu.jeong@arm.com printMnemonic(ss); 9277615Sminkyu.jeong@arm.com printReg(ss, ura); 9287615Sminkyu.jeong@arm.com ss << ", ["; 9297615Sminkyu.jeong@arm.com printReg(ss, urb); 9307615Sminkyu.jeong@arm.com ss << ", "; 9317615Sminkyu.jeong@arm.com ccprintf(ss, "#%d", imm); 9327615Sminkyu.jeong@arm.com ss << "]"; 9337615Sminkyu.jeong@arm.com return ss.str(); 9347615Sminkyu.jeong@arm.com} 9357615Sminkyu.jeong@arm.com 9367615Sminkyu.jeong@arm.com} 937