macromem.cc revision 7639
17170Sgblack@eecs.umich.edu/* 27170Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37170Sgblack@eecs.umich.edu * All rights reserved 47170Sgblack@eecs.umich.edu * 57170Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67170Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77170Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87170Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97170Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107170Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117170Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127170Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137170Sgblack@eecs.umich.edu * 147170Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 157170Sgblack@eecs.umich.edu * All rights reserved. 167170Sgblack@eecs.umich.edu * 177170Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 187170Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 197170Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 207170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 217170Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 227170Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 237170Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 247170Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 257170Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 267170Sgblack@eecs.umich.edu * this software without specific prior written permission. 277170Sgblack@eecs.umich.edu * 287170Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297170Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307170Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317170Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327170Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337170Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347170Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357170Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367170Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377170Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387170Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397170Sgblack@eecs.umich.edu * 407170Sgblack@eecs.umich.edu * Authors: Stephen Hines 417170Sgblack@eecs.umich.edu */ 427170Sgblack@eecs.umich.edu 437170Sgblack@eecs.umich.edu#include "arch/arm/insts/macromem.hh" 447170Sgblack@eecs.umich.edu#include "arch/arm/decoder.hh" 457170Sgblack@eecs.umich.edu 467170Sgblack@eecs.umich.eduusing namespace ArmISAInst; 477170Sgblack@eecs.umich.edu 487170Sgblack@eecs.umich.edunamespace ArmISA 497170Sgblack@eecs.umich.edu{ 507170Sgblack@eecs.umich.edu 517170Sgblack@eecs.umich.eduMacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst, 527170Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 537170Sgblack@eecs.umich.edu bool index, bool up, bool user, bool writeback, 547170Sgblack@eecs.umich.edu bool load, uint32_t reglist) : 557170Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 567170Sgblack@eecs.umich.edu{ 577170Sgblack@eecs.umich.edu uint32_t regs = reglist; 587170Sgblack@eecs.umich.edu uint32_t ones = number_of_ones(reglist); 597170Sgblack@eecs.umich.edu // Remember that writeback adds a uop 607170Sgblack@eecs.umich.edu numMicroops = ones + (writeback ? 1 : 0) + 1; 617170Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 627170Sgblack@eecs.umich.edu uint32_t addr = 0; 637170Sgblack@eecs.umich.edu 647170Sgblack@eecs.umich.edu if (!up) 657170Sgblack@eecs.umich.edu addr = (ones << 2) - 4; 667170Sgblack@eecs.umich.edu 677170Sgblack@eecs.umich.edu if (!index) 687170Sgblack@eecs.umich.edu addr += 4; 697170Sgblack@eecs.umich.edu 707190Sgblack@eecs.umich.edu StaticInstPtr *uop = microOps; 717190Sgblack@eecs.umich.edu StaticInstPtr wbUop; 727190Sgblack@eecs.umich.edu if (writeback) { 737190Sgblack@eecs.umich.edu if (up) { 747190Sgblack@eecs.umich.edu wbUop = new MicroAddiUop(machInst, rn, rn, ones * 4); 757190Sgblack@eecs.umich.edu } else { 767190Sgblack@eecs.umich.edu wbUop = new MicroSubiUop(machInst, rn, rn, ones * 4); 777190Sgblack@eecs.umich.edu } 787190Sgblack@eecs.umich.edu } 797190Sgblack@eecs.umich.edu 807170Sgblack@eecs.umich.edu // Add 0 to Rn and stick it in ureg0. 817170Sgblack@eecs.umich.edu // This is equivalent to a move. 827190Sgblack@eecs.umich.edu *uop = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0); 837190Sgblack@eecs.umich.edu 847190Sgblack@eecs.umich.edu // Write back at the start for loads. This covers the ldm exception return 857190Sgblack@eecs.umich.edu // case where the base needs to be written in the old mode. Stores may need 867190Sgblack@eecs.umich.edu // the original value of the base, but they don't change mode and can 877190Sgblack@eecs.umich.edu // write back at the end like before. 887190Sgblack@eecs.umich.edu if (load && writeback) { 897190Sgblack@eecs.umich.edu *++uop = wbUop; 907190Sgblack@eecs.umich.edu } 917170Sgblack@eecs.umich.edu 927170Sgblack@eecs.umich.edu unsigned reg = 0; 937170Sgblack@eecs.umich.edu bool force_user = user & !bits(reglist, 15); 947170Sgblack@eecs.umich.edu bool exception_ret = user & bits(reglist, 15); 957170Sgblack@eecs.umich.edu 967190Sgblack@eecs.umich.edu for (int i = 0; i < ones; i++) { 977170Sgblack@eecs.umich.edu // Find the next register. 987170Sgblack@eecs.umich.edu while (!bits(regs, reg)) 997170Sgblack@eecs.umich.edu reg++; 1007170Sgblack@eecs.umich.edu replaceBits(regs, reg, 0); 1017170Sgblack@eecs.umich.edu 1027170Sgblack@eecs.umich.edu unsigned regIdx = reg; 1037170Sgblack@eecs.umich.edu if (force_user) { 1047310Sgblack@eecs.umich.edu regIdx = intRegInMode(MODE_USER, regIdx); 1057170Sgblack@eecs.umich.edu } 1067170Sgblack@eecs.umich.edu 1077170Sgblack@eecs.umich.edu if (load) { 1087170Sgblack@eecs.umich.edu if (reg == INTREG_PC && exception_ret) { 1097170Sgblack@eecs.umich.edu // This must be the exception return form of ldm. 1107190Sgblack@eecs.umich.edu *++uop = new MicroLdrRetUop(machInst, regIdx, 1117190Sgblack@eecs.umich.edu INTREG_UREG0, up, addr); 1127170Sgblack@eecs.umich.edu } else { 1137190Sgblack@eecs.umich.edu *++uop = new MicroLdrUop(machInst, regIdx, 1147190Sgblack@eecs.umich.edu INTREG_UREG0, up, addr); 1157170Sgblack@eecs.umich.edu } 1167170Sgblack@eecs.umich.edu } else { 1177190Sgblack@eecs.umich.edu *++uop = new MicroStrUop(machInst, regIdx, INTREG_UREG0, up, addr); 1187170Sgblack@eecs.umich.edu } 1197170Sgblack@eecs.umich.edu 1207170Sgblack@eecs.umich.edu if (up) 1217170Sgblack@eecs.umich.edu addr += 4; 1227170Sgblack@eecs.umich.edu else 1237170Sgblack@eecs.umich.edu addr -= 4; 1247170Sgblack@eecs.umich.edu } 1257170Sgblack@eecs.umich.edu 1267190Sgblack@eecs.umich.edu if (!load && writeback) { 1277190Sgblack@eecs.umich.edu *++uop = wbUop; 1287170Sgblack@eecs.umich.edu } 1297190Sgblack@eecs.umich.edu 1307190Sgblack@eecs.umich.edu (*uop)->setLastMicroop(); 1317343Sgblack@eecs.umich.edu 1327343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 1337343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 1347343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 1357343Sgblack@eecs.umich.edu assert(uopPtr); 1367343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 1377343Sgblack@eecs.umich.edu } 1387170Sgblack@eecs.umich.edu} 1397170Sgblack@eecs.umich.edu 1407639Sgblack@eecs.umich.eduVldMultOp::VldMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 1417639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 1427639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 1437639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 1447639Sgblack@eecs.umich.edu{ 1457639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 1467639Sgblack@eecs.umich.edu assert(regs % elems == 0); 1477639Sgblack@eecs.umich.edu 1487639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 1497639Sgblack@eecs.umich.edu bool wb = (rm != 15); 1507639Sgblack@eecs.umich.edu bool deinterleave = (elems > 1); 1517639Sgblack@eecs.umich.edu 1527639Sgblack@eecs.umich.edu if (wb) numMicroops++; 1537639Sgblack@eecs.umich.edu if (deinterleave) numMicroops += (regs / elems); 1547639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 1557639Sgblack@eecs.umich.edu 1567639Sgblack@eecs.umich.edu RegIndex rMid = deinterleave ? NumFloatArchRegs : vd * 2; 1577639Sgblack@eecs.umich.edu 1587639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 1597639Sgblack@eecs.umich.edu 1607639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 1617639Sgblack@eecs.umich.edu switch (regs) { 1627639Sgblack@eecs.umich.edu case 4: 1637639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1647639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1657639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1667639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1677639Sgblack@eecs.umich.edu break; 1687639Sgblack@eecs.umich.edu case 3: 1697639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1707639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1717639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 1727639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 1737639Sgblack@eecs.umich.edu break; 1747639Sgblack@eecs.umich.edu case 2: 1757639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon16Uop>( 1767639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1777639Sgblack@eecs.umich.edu break; 1787639Sgblack@eecs.umich.edu case 1: 1797639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroLdrNeon8Uop>( 1807639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 1817639Sgblack@eecs.umich.edu break; 1827639Sgblack@eecs.umich.edu default: 1837639Sgblack@eecs.umich.edu panic("Unrecognized number of registers %d.\n", regs); 1847639Sgblack@eecs.umich.edu } 1857639Sgblack@eecs.umich.edu if (wb) { 1867639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 1877639Sgblack@eecs.umich.edu microOps[uopIdx++] = 1887639Sgblack@eecs.umich.edu new MicroAddUop(machInst, rn, rn, rm); 1897639Sgblack@eecs.umich.edu } else { 1907639Sgblack@eecs.umich.edu microOps[uopIdx++] = 1917639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 1927639Sgblack@eecs.umich.edu } 1937639Sgblack@eecs.umich.edu } 1947639Sgblack@eecs.umich.edu if (deinterleave) { 1957639Sgblack@eecs.umich.edu switch (elems) { 1967639Sgblack@eecs.umich.edu case 4: 1977639Sgblack@eecs.umich.edu assert(regs == 4); 1987639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon8Uop>( 1997639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2007639Sgblack@eecs.umich.edu break; 2017639Sgblack@eecs.umich.edu case 3: 2027639Sgblack@eecs.umich.edu assert(regs == 3); 2037639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon6Uop>( 2047639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2057639Sgblack@eecs.umich.edu break; 2067639Sgblack@eecs.umich.edu case 2: 2077639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 2087639Sgblack@eecs.umich.edu if (regs == 4) { 2097639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2107639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2117639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2127639Sgblack@eecs.umich.edu size, machInst, vd * 2 + 2, rMid + 4, inc * 2); 2137639Sgblack@eecs.umich.edu } else { 2147639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroDeintNeon4Uop>( 2157639Sgblack@eecs.umich.edu size, machInst, vd * 2, rMid, inc * 2); 2167639Sgblack@eecs.umich.edu } 2177639Sgblack@eecs.umich.edu break; 2187639Sgblack@eecs.umich.edu default: 2197639Sgblack@eecs.umich.edu panic("Bad number of elements to deinterleave %d.\n", elems); 2207639Sgblack@eecs.umich.edu } 2217639Sgblack@eecs.umich.edu } 2227639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 2237639Sgblack@eecs.umich.edu 2247639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 2257639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 2267639Sgblack@eecs.umich.edu assert(uopPtr); 2277639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 2287639Sgblack@eecs.umich.edu } 2297639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 2307639Sgblack@eecs.umich.edu} 2317639Sgblack@eecs.umich.edu 2327639Sgblack@eecs.umich.eduVldSingleOp::VldSingleOp(const char *mnem, ExtMachInst machInst, 2337639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 2347639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 2357639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 2367639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 2377639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 2387639Sgblack@eecs.umich.edu{ 2397639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 2407639Sgblack@eecs.umich.edu assert(regs % elems == 0); 2417639Sgblack@eecs.umich.edu 2427639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 2437639Sgblack@eecs.umich.edu unsigned loadSize = eBytes * elems; 2447639Sgblack@eecs.umich.edu unsigned loadRegs M5_VAR_USED = (loadSize + sizeof(FloatRegBits) - 1) / 2457639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 2467639Sgblack@eecs.umich.edu 2477639Sgblack@eecs.umich.edu assert(loadRegs > 0 && loadRegs <= 4); 2487639Sgblack@eecs.umich.edu 2497639Sgblack@eecs.umich.edu numMicroops = 1; 2507639Sgblack@eecs.umich.edu bool wb = (rm != 15); 2517639Sgblack@eecs.umich.edu 2527639Sgblack@eecs.umich.edu if (wb) numMicroops++; 2537639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 2547639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 2557639Sgblack@eecs.umich.edu 2567639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 2577639Sgblack@eecs.umich.edu 2587639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 2597639Sgblack@eecs.umich.edu switch (loadSize) { 2607639Sgblack@eecs.umich.edu case 1: 2617639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon1Uop<uint8_t>( 2627639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2637639Sgblack@eecs.umich.edu break; 2647639Sgblack@eecs.umich.edu case 2: 2657639Sgblack@eecs.umich.edu if (eBytes == 2) { 2667639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint16_t>( 2677639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2687639Sgblack@eecs.umich.edu } else { 2697639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon2Uop<uint8_t>( 2707639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2717639Sgblack@eecs.umich.edu } 2727639Sgblack@eecs.umich.edu break; 2737639Sgblack@eecs.umich.edu case 3: 2747639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon3Uop<uint8_t>( 2757639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2767639Sgblack@eecs.umich.edu break; 2777639Sgblack@eecs.umich.edu case 4: 2787639Sgblack@eecs.umich.edu switch (eBytes) { 2797639Sgblack@eecs.umich.edu case 1: 2807639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint8_t>( 2817639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2827639Sgblack@eecs.umich.edu break; 2837639Sgblack@eecs.umich.edu case 2: 2847639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint16_t>( 2857639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2867639Sgblack@eecs.umich.edu break; 2877639Sgblack@eecs.umich.edu case 4: 2887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon4Uop<uint32_t>( 2897639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2907639Sgblack@eecs.umich.edu break; 2917639Sgblack@eecs.umich.edu } 2927639Sgblack@eecs.umich.edu break; 2937639Sgblack@eecs.umich.edu case 6: 2947639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon6Uop<uint16_t>( 2957639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 2967639Sgblack@eecs.umich.edu break; 2977639Sgblack@eecs.umich.edu case 8: 2987639Sgblack@eecs.umich.edu switch (eBytes) { 2997639Sgblack@eecs.umich.edu case 2: 3007639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint16_t>( 3017639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3027639Sgblack@eecs.umich.edu break; 3037639Sgblack@eecs.umich.edu case 4: 3047639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon8Uop<uint32_t>( 3057639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3067639Sgblack@eecs.umich.edu break; 3077639Sgblack@eecs.umich.edu } 3087639Sgblack@eecs.umich.edu break; 3097639Sgblack@eecs.umich.edu case 12: 3107639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon12Uop<uint32_t>( 3117639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3127639Sgblack@eecs.umich.edu break; 3137639Sgblack@eecs.umich.edu case 16: 3147639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroLdrNeon16Uop<uint32_t>( 3157639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 3167639Sgblack@eecs.umich.edu break; 3177639Sgblack@eecs.umich.edu default: 3187639Sgblack@eecs.umich.edu panic("Unrecognized load size %d.\n", regs); 3197639Sgblack@eecs.umich.edu } 3207639Sgblack@eecs.umich.edu if (wb) { 3217639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 3227639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3237639Sgblack@eecs.umich.edu new MicroAddUop(machInst, rn, rn, rm); 3247639Sgblack@eecs.umich.edu } else { 3257639Sgblack@eecs.umich.edu microOps[uopIdx++] = 3267639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, loadSize); 3277639Sgblack@eecs.umich.edu } 3287639Sgblack@eecs.umich.edu } 3297639Sgblack@eecs.umich.edu switch (elems) { 3307639Sgblack@eecs.umich.edu case 4: 3317639Sgblack@eecs.umich.edu assert(regs == 4); 3327639Sgblack@eecs.umich.edu switch (size) { 3337639Sgblack@eecs.umich.edu case 0: 3347639Sgblack@eecs.umich.edu if (all) { 3357639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint8_t>( 3367639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3377639Sgblack@eecs.umich.edu } else { 3387639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint8_t>( 3397639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3407639Sgblack@eecs.umich.edu } 3417639Sgblack@eecs.umich.edu break; 3427639Sgblack@eecs.umich.edu case 1: 3437639Sgblack@eecs.umich.edu if (all) { 3447639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to8Uop<uint16_t>( 3457639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3467639Sgblack@eecs.umich.edu } else { 3477639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to8Uop<uint16_t>( 3487639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3497639Sgblack@eecs.umich.edu } 3507639Sgblack@eecs.umich.edu break; 3517639Sgblack@eecs.umich.edu case 2: 3527639Sgblack@eecs.umich.edu if (all) { 3537639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to8Uop<uint32_t>( 3547639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3557639Sgblack@eecs.umich.edu } else { 3567639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to8Uop<uint32_t>( 3577639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3587639Sgblack@eecs.umich.edu } 3597639Sgblack@eecs.umich.edu break; 3607639Sgblack@eecs.umich.edu default: 3617639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 3627639Sgblack@eecs.umich.edu break; 3637639Sgblack@eecs.umich.edu } 3647639Sgblack@eecs.umich.edu break; 3657639Sgblack@eecs.umich.edu case 3: 3667639Sgblack@eecs.umich.edu assert(regs == 3); 3677639Sgblack@eecs.umich.edu switch (size) { 3687639Sgblack@eecs.umich.edu case 0: 3697639Sgblack@eecs.umich.edu if (all) { 3707639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint8_t>( 3717639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3727639Sgblack@eecs.umich.edu } else { 3737639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint8_t>( 3747639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3757639Sgblack@eecs.umich.edu } 3767639Sgblack@eecs.umich.edu break; 3777639Sgblack@eecs.umich.edu case 1: 3787639Sgblack@eecs.umich.edu if (all) { 3797639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to6Uop<uint16_t>( 3807639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3817639Sgblack@eecs.umich.edu } else { 3827639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to6Uop<uint16_t>( 3837639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3847639Sgblack@eecs.umich.edu } 3857639Sgblack@eecs.umich.edu break; 3867639Sgblack@eecs.umich.edu case 2: 3877639Sgblack@eecs.umich.edu if (all) { 3887639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon4to6Uop<uint32_t>( 3897639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 3907639Sgblack@eecs.umich.edu } else { 3917639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon4to6Uop<uint32_t>( 3927639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 3937639Sgblack@eecs.umich.edu } 3947639Sgblack@eecs.umich.edu break; 3957639Sgblack@eecs.umich.edu default: 3967639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 3977639Sgblack@eecs.umich.edu break; 3987639Sgblack@eecs.umich.edu } 3997639Sgblack@eecs.umich.edu break; 4007639Sgblack@eecs.umich.edu case 2: 4017639Sgblack@eecs.umich.edu assert(regs == 2); 4027639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4037639Sgblack@eecs.umich.edu switch (size) { 4047639Sgblack@eecs.umich.edu case 0: 4057639Sgblack@eecs.umich.edu if (all) { 4067639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint8_t>( 4077639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4087639Sgblack@eecs.umich.edu } else { 4097639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint8_t>( 4107639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4117639Sgblack@eecs.umich.edu } 4127639Sgblack@eecs.umich.edu break; 4137639Sgblack@eecs.umich.edu case 1: 4147639Sgblack@eecs.umich.edu if (all) { 4157639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint16_t>( 4167639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4177639Sgblack@eecs.umich.edu } else { 4187639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint16_t>( 4197639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4207639Sgblack@eecs.umich.edu } 4217639Sgblack@eecs.umich.edu break; 4227639Sgblack@eecs.umich.edu case 2: 4237639Sgblack@eecs.umich.edu if (all) { 4247639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackAllNeon2to4Uop<uint32_t>( 4257639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2); 4267639Sgblack@eecs.umich.edu } else { 4277639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroUnpackNeon2to4Uop<uint32_t>( 4287639Sgblack@eecs.umich.edu machInst, vd * 2, ufp0, inc * 2, lane); 4297639Sgblack@eecs.umich.edu } 4307639Sgblack@eecs.umich.edu break; 4317639Sgblack@eecs.umich.edu default: 4327639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 4337639Sgblack@eecs.umich.edu break; 4347639Sgblack@eecs.umich.edu } 4357639Sgblack@eecs.umich.edu break; 4367639Sgblack@eecs.umich.edu case 1: 4377639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 4387639Sgblack@eecs.umich.edu assert(loadRegs <= 2); 4397639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 4407639Sgblack@eecs.umich.edu switch (size) { 4417639Sgblack@eecs.umich.edu case 0: 4427639Sgblack@eecs.umich.edu if (all) { 4437639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4447639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint8_t>( 4457639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4467639Sgblack@eecs.umich.edu } else { 4477639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4487639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint8_t>( 4497639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4507639Sgblack@eecs.umich.edu } 4517639Sgblack@eecs.umich.edu break; 4527639Sgblack@eecs.umich.edu case 1: 4537639Sgblack@eecs.umich.edu if (all) { 4547639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4557639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint16_t>( 4567639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4577639Sgblack@eecs.umich.edu } else { 4587639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4597639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint16_t>( 4607639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4617639Sgblack@eecs.umich.edu } 4627639Sgblack@eecs.umich.edu break; 4637639Sgblack@eecs.umich.edu case 2: 4647639Sgblack@eecs.umich.edu if (all) { 4657639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4667639Sgblack@eecs.umich.edu new MicroUnpackAllNeon2to2Uop<uint32_t>( 4677639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2); 4687639Sgblack@eecs.umich.edu } else { 4697639Sgblack@eecs.umich.edu microOps[uopIdx++] = 4707639Sgblack@eecs.umich.edu new MicroUnpackNeon2to2Uop<uint32_t>( 4717639Sgblack@eecs.umich.edu machInst, (vd + offset) * 2, ufp0, inc * 2, lane); 4727639Sgblack@eecs.umich.edu } 4737639Sgblack@eecs.umich.edu break; 4747639Sgblack@eecs.umich.edu default: 4757639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 4767639Sgblack@eecs.umich.edu break; 4777639Sgblack@eecs.umich.edu } 4787639Sgblack@eecs.umich.edu } 4797639Sgblack@eecs.umich.edu break; 4807639Sgblack@eecs.umich.edu default: 4817639Sgblack@eecs.umich.edu panic("Bad number of elements to unpack %d.\n", elems); 4827639Sgblack@eecs.umich.edu } 4837639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 4847639Sgblack@eecs.umich.edu 4857639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 4867639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 4877639Sgblack@eecs.umich.edu assert(uopPtr); 4887639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 4897639Sgblack@eecs.umich.edu } 4907639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 4917639Sgblack@eecs.umich.edu} 4927639Sgblack@eecs.umich.edu 4937639Sgblack@eecs.umich.eduVstMultOp::VstMultOp(const char *mnem, ExtMachInst machInst, OpClass __opClass, 4947639Sgblack@eecs.umich.edu unsigned elems, RegIndex rn, RegIndex vd, unsigned regs, 4957639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, RegIndex rm) : 4967639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 4977639Sgblack@eecs.umich.edu{ 4987639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 4997639Sgblack@eecs.umich.edu assert(regs % elems == 0); 5007639Sgblack@eecs.umich.edu 5017639Sgblack@eecs.umich.edu numMicroops = (regs > 2) ? 2 : 1; 5027639Sgblack@eecs.umich.edu bool wb = (rm != 15); 5037639Sgblack@eecs.umich.edu bool interleave = (elems > 1); 5047639Sgblack@eecs.umich.edu 5057639Sgblack@eecs.umich.edu if (wb) numMicroops++; 5067639Sgblack@eecs.umich.edu if (interleave) numMicroops += (regs / elems); 5077639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 5087639Sgblack@eecs.umich.edu 5097639Sgblack@eecs.umich.edu uint32_t noAlign = TLB::MustBeOne; 5107639Sgblack@eecs.umich.edu 5117639Sgblack@eecs.umich.edu RegIndex rMid = interleave ? NumFloatArchRegs : vd * 2; 5127639Sgblack@eecs.umich.edu 5137639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 5147639Sgblack@eecs.umich.edu if (interleave) { 5157639Sgblack@eecs.umich.edu switch (elems) { 5167639Sgblack@eecs.umich.edu case 4: 5177639Sgblack@eecs.umich.edu assert(regs == 4); 5187639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon8Uop>( 5197639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5207639Sgblack@eecs.umich.edu break; 5217639Sgblack@eecs.umich.edu case 3: 5227639Sgblack@eecs.umich.edu assert(regs == 3); 5237639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon6Uop>( 5247639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5257639Sgblack@eecs.umich.edu break; 5267639Sgblack@eecs.umich.edu case 2: 5277639Sgblack@eecs.umich.edu assert(regs == 4 || regs == 2); 5287639Sgblack@eecs.umich.edu if (regs == 4) { 5297639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5307639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5317639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5327639Sgblack@eecs.umich.edu size, machInst, rMid + 4, vd * 2 + 2, inc * 2); 5337639Sgblack@eecs.umich.edu } else { 5347639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMixInst<MicroInterNeon4Uop>( 5357639Sgblack@eecs.umich.edu size, machInst, rMid, vd * 2, inc * 2); 5367639Sgblack@eecs.umich.edu } 5377639Sgblack@eecs.umich.edu break; 5387639Sgblack@eecs.umich.edu default: 5397639Sgblack@eecs.umich.edu panic("Bad number of elements to interleave %d.\n", elems); 5407639Sgblack@eecs.umich.edu } 5417639Sgblack@eecs.umich.edu } 5427639Sgblack@eecs.umich.edu switch (regs) { 5437639Sgblack@eecs.umich.edu case 4: 5447639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5457639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5467639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5477639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5487639Sgblack@eecs.umich.edu break; 5497639Sgblack@eecs.umich.edu case 3: 5507639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5517639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5527639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5537639Sgblack@eecs.umich.edu size, machInst, rMid + 4, rn, 16, noAlign); 5547639Sgblack@eecs.umich.edu break; 5557639Sgblack@eecs.umich.edu case 2: 5567639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon16Uop>( 5577639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5587639Sgblack@eecs.umich.edu break; 5597639Sgblack@eecs.umich.edu case 1: 5607639Sgblack@eecs.umich.edu microOps[uopIdx++] = newNeonMemInst<MicroStrNeon8Uop>( 5617639Sgblack@eecs.umich.edu size, machInst, rMid, rn, 0, align); 5627639Sgblack@eecs.umich.edu break; 5637639Sgblack@eecs.umich.edu default: 5647639Sgblack@eecs.umich.edu panic("Unrecognized number of registers %d.\n", regs); 5657639Sgblack@eecs.umich.edu } 5667639Sgblack@eecs.umich.edu if (wb) { 5677639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 5687639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5697639Sgblack@eecs.umich.edu new MicroAddUop(machInst, rn, rn, rm); 5707639Sgblack@eecs.umich.edu } else { 5717639Sgblack@eecs.umich.edu microOps[uopIdx++] = 5727639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, regs * 8); 5737639Sgblack@eecs.umich.edu } 5747639Sgblack@eecs.umich.edu } 5757639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 5767639Sgblack@eecs.umich.edu 5777639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 5787639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 5797639Sgblack@eecs.umich.edu assert(uopPtr); 5807639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 5817639Sgblack@eecs.umich.edu } 5827639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 5837639Sgblack@eecs.umich.edu} 5847639Sgblack@eecs.umich.edu 5857639Sgblack@eecs.umich.eduVstSingleOp::VstSingleOp(const char *mnem, ExtMachInst machInst, 5867639Sgblack@eecs.umich.edu OpClass __opClass, bool all, unsigned elems, 5877639Sgblack@eecs.umich.edu RegIndex rn, RegIndex vd, unsigned regs, 5887639Sgblack@eecs.umich.edu unsigned inc, uint32_t size, uint32_t align, 5897639Sgblack@eecs.umich.edu RegIndex rm, unsigned lane) : 5907639Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 5917639Sgblack@eecs.umich.edu{ 5927639Sgblack@eecs.umich.edu assert(!all); 5937639Sgblack@eecs.umich.edu assert(regs > 0 && regs <= 4); 5947639Sgblack@eecs.umich.edu assert(regs % elems == 0); 5957639Sgblack@eecs.umich.edu 5967639Sgblack@eecs.umich.edu unsigned eBytes = (1 << size); 5977639Sgblack@eecs.umich.edu unsigned storeSize = eBytes * elems; 5987639Sgblack@eecs.umich.edu unsigned storeRegs M5_VAR_USED = (storeSize + sizeof(FloatRegBits) - 1) / 5997639Sgblack@eecs.umich.edu sizeof(FloatRegBits); 6007639Sgblack@eecs.umich.edu 6017639Sgblack@eecs.umich.edu assert(storeRegs > 0 && storeRegs <= 4); 6027639Sgblack@eecs.umich.edu 6037639Sgblack@eecs.umich.edu numMicroops = 1; 6047639Sgblack@eecs.umich.edu bool wb = (rm != 15); 6057639Sgblack@eecs.umich.edu 6067639Sgblack@eecs.umich.edu if (wb) numMicroops++; 6077639Sgblack@eecs.umich.edu numMicroops += (regs / elems); 6087639Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 6097639Sgblack@eecs.umich.edu 6107639Sgblack@eecs.umich.edu RegIndex ufp0 = NumFloatArchRegs; 6117639Sgblack@eecs.umich.edu 6127639Sgblack@eecs.umich.edu unsigned uopIdx = 0; 6137639Sgblack@eecs.umich.edu switch (elems) { 6147639Sgblack@eecs.umich.edu case 4: 6157639Sgblack@eecs.umich.edu assert(regs == 4); 6167639Sgblack@eecs.umich.edu switch (size) { 6177639Sgblack@eecs.umich.edu case 0: 6187639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint8_t>( 6197639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6207639Sgblack@eecs.umich.edu break; 6217639Sgblack@eecs.umich.edu case 1: 6227639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to2Uop<uint16_t>( 6237639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6247639Sgblack@eecs.umich.edu break; 6257639Sgblack@eecs.umich.edu case 2: 6267639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon8to4Uop<uint32_t>( 6277639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6287639Sgblack@eecs.umich.edu break; 6297639Sgblack@eecs.umich.edu default: 6307639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 6317639Sgblack@eecs.umich.edu break; 6327639Sgblack@eecs.umich.edu } 6337639Sgblack@eecs.umich.edu break; 6347639Sgblack@eecs.umich.edu case 3: 6357639Sgblack@eecs.umich.edu assert(regs == 3); 6367639Sgblack@eecs.umich.edu switch (size) { 6377639Sgblack@eecs.umich.edu case 0: 6387639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint8_t>( 6397639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6407639Sgblack@eecs.umich.edu break; 6417639Sgblack@eecs.umich.edu case 1: 6427639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to2Uop<uint16_t>( 6437639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6447639Sgblack@eecs.umich.edu break; 6457639Sgblack@eecs.umich.edu case 2: 6467639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon6to4Uop<uint32_t>( 6477639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6487639Sgblack@eecs.umich.edu break; 6497639Sgblack@eecs.umich.edu default: 6507639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 6517639Sgblack@eecs.umich.edu break; 6527639Sgblack@eecs.umich.edu } 6537639Sgblack@eecs.umich.edu break; 6547639Sgblack@eecs.umich.edu case 2: 6557639Sgblack@eecs.umich.edu assert(regs == 2); 6567639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 6577639Sgblack@eecs.umich.edu switch (size) { 6587639Sgblack@eecs.umich.edu case 0: 6597639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint8_t>( 6607639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6617639Sgblack@eecs.umich.edu break; 6627639Sgblack@eecs.umich.edu case 1: 6637639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint16_t>( 6647639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6657639Sgblack@eecs.umich.edu break; 6667639Sgblack@eecs.umich.edu case 2: 6677639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon4to2Uop<uint32_t>( 6687639Sgblack@eecs.umich.edu machInst, ufp0, vd * 2, inc * 2, lane); 6697639Sgblack@eecs.umich.edu break; 6707639Sgblack@eecs.umich.edu default: 6717639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 6727639Sgblack@eecs.umich.edu break; 6737639Sgblack@eecs.umich.edu } 6747639Sgblack@eecs.umich.edu break; 6757639Sgblack@eecs.umich.edu case 1: 6767639Sgblack@eecs.umich.edu assert(regs == 1 || (all && regs == 2)); 6777639Sgblack@eecs.umich.edu assert(storeRegs <= 2); 6787639Sgblack@eecs.umich.edu for (unsigned offset = 0; offset < regs; offset++) { 6797639Sgblack@eecs.umich.edu switch (size) { 6807639Sgblack@eecs.umich.edu case 0: 6817639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint8_t>( 6827639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 6837639Sgblack@eecs.umich.edu break; 6847639Sgblack@eecs.umich.edu case 1: 6857639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint16_t>( 6867639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 6877639Sgblack@eecs.umich.edu break; 6887639Sgblack@eecs.umich.edu case 2: 6897639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroPackNeon2to2Uop<uint32_t>( 6907639Sgblack@eecs.umich.edu machInst, ufp0, (vd + offset) * 2, inc * 2, lane); 6917639Sgblack@eecs.umich.edu break; 6927639Sgblack@eecs.umich.edu default: 6937639Sgblack@eecs.umich.edu panic("Bad size %d.\n", size); 6947639Sgblack@eecs.umich.edu break; 6957639Sgblack@eecs.umich.edu } 6967639Sgblack@eecs.umich.edu } 6977639Sgblack@eecs.umich.edu break; 6987639Sgblack@eecs.umich.edu default: 6997639Sgblack@eecs.umich.edu panic("Bad number of elements to pack %d.\n", elems); 7007639Sgblack@eecs.umich.edu } 7017639Sgblack@eecs.umich.edu switch (storeSize) { 7027639Sgblack@eecs.umich.edu case 1: 7037639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon1Uop<uint8_t>( 7047639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7057639Sgblack@eecs.umich.edu break; 7067639Sgblack@eecs.umich.edu case 2: 7077639Sgblack@eecs.umich.edu if (eBytes == 2) { 7087639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint16_t>( 7097639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7107639Sgblack@eecs.umich.edu } else { 7117639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon2Uop<uint8_t>( 7127639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7137639Sgblack@eecs.umich.edu } 7147639Sgblack@eecs.umich.edu break; 7157639Sgblack@eecs.umich.edu case 3: 7167639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon3Uop<uint8_t>( 7177639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7187639Sgblack@eecs.umich.edu break; 7197639Sgblack@eecs.umich.edu case 4: 7207639Sgblack@eecs.umich.edu switch (eBytes) { 7217639Sgblack@eecs.umich.edu case 1: 7227639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint8_t>( 7237639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7247639Sgblack@eecs.umich.edu break; 7257639Sgblack@eecs.umich.edu case 2: 7267639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint16_t>( 7277639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7287639Sgblack@eecs.umich.edu break; 7297639Sgblack@eecs.umich.edu case 4: 7307639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon4Uop<uint32_t>( 7317639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7327639Sgblack@eecs.umich.edu break; 7337639Sgblack@eecs.umich.edu } 7347639Sgblack@eecs.umich.edu break; 7357639Sgblack@eecs.umich.edu case 6: 7367639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon6Uop<uint16_t>( 7377639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7387639Sgblack@eecs.umich.edu break; 7397639Sgblack@eecs.umich.edu case 8: 7407639Sgblack@eecs.umich.edu switch (eBytes) { 7417639Sgblack@eecs.umich.edu case 2: 7427639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint16_t>( 7437639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7447639Sgblack@eecs.umich.edu break; 7457639Sgblack@eecs.umich.edu case 4: 7467639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon8Uop<uint32_t>( 7477639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7487639Sgblack@eecs.umich.edu break; 7497639Sgblack@eecs.umich.edu } 7507639Sgblack@eecs.umich.edu break; 7517639Sgblack@eecs.umich.edu case 12: 7527639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon12Uop<uint32_t>( 7537639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7547639Sgblack@eecs.umich.edu break; 7557639Sgblack@eecs.umich.edu case 16: 7567639Sgblack@eecs.umich.edu microOps[uopIdx++] = new MicroStrNeon16Uop<uint32_t>( 7577639Sgblack@eecs.umich.edu machInst, ufp0, rn, 0, align); 7587639Sgblack@eecs.umich.edu break; 7597639Sgblack@eecs.umich.edu default: 7607639Sgblack@eecs.umich.edu panic("Unrecognized store size %d.\n", regs); 7617639Sgblack@eecs.umich.edu } 7627639Sgblack@eecs.umich.edu if (wb) { 7637639Sgblack@eecs.umich.edu if (rm != 15 && rm != 13) { 7647639Sgblack@eecs.umich.edu microOps[uopIdx++] = 7657639Sgblack@eecs.umich.edu new MicroAddUop(machInst, rn, rn, rm); 7667639Sgblack@eecs.umich.edu } else { 7677639Sgblack@eecs.umich.edu microOps[uopIdx++] = 7687639Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, storeSize); 7697639Sgblack@eecs.umich.edu } 7707639Sgblack@eecs.umich.edu } 7717639Sgblack@eecs.umich.edu assert(uopIdx == numMicroops); 7727639Sgblack@eecs.umich.edu 7737639Sgblack@eecs.umich.edu for (unsigned i = 0; i < numMicroops - 1; i++) { 7747639Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(microOps[i].get()); 7757639Sgblack@eecs.umich.edu assert(uopPtr); 7767639Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 7777639Sgblack@eecs.umich.edu } 7787639Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 7797639Sgblack@eecs.umich.edu} 7807639Sgblack@eecs.umich.edu 7817175Sgblack@eecs.umich.eduMacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst, 7827175Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex rn, 7837175Sgblack@eecs.umich.edu RegIndex vd, bool single, bool up, 7847175Sgblack@eecs.umich.edu bool writeback, bool load, uint32_t offset) : 7857175Sgblack@eecs.umich.edu PredMacroOp(mnem, machInst, __opClass) 7867175Sgblack@eecs.umich.edu{ 7877175Sgblack@eecs.umich.edu int i = 0; 7887175Sgblack@eecs.umich.edu 7897175Sgblack@eecs.umich.edu // The lowest order bit selects fldmx (set) or fldmd (clear). These seem 7907175Sgblack@eecs.umich.edu // to be functionally identical except that fldmx is deprecated. For now 7917175Sgblack@eecs.umich.edu // we'll assume they're otherwise interchangable. 7927175Sgblack@eecs.umich.edu int count = (single ? offset : (offset / 2)); 7937175Sgblack@eecs.umich.edu if (count == 0 || count > NumFloatArchRegs) 7947175Sgblack@eecs.umich.edu warn_once("Bad offset field for VFP load/store multiple.\n"); 7957175Sgblack@eecs.umich.edu if (count == 0) { 7967175Sgblack@eecs.umich.edu // Force there to be at least one microop so the macroop makes sense. 7977175Sgblack@eecs.umich.edu writeback = true; 7987175Sgblack@eecs.umich.edu } 7997175Sgblack@eecs.umich.edu if (count > NumFloatArchRegs) 8007175Sgblack@eecs.umich.edu count = NumFloatArchRegs; 8017175Sgblack@eecs.umich.edu 8027342Sgblack@eecs.umich.edu numMicroops = count * (single ? 1 : 2) + (writeback ? 1 : 0); 8037342Sgblack@eecs.umich.edu microOps = new StaticInstPtr[numMicroops]; 8047342Sgblack@eecs.umich.edu 8057395Sgblack@eecs.umich.edu int64_t addr = 0; 8067175Sgblack@eecs.umich.edu 8077342Sgblack@eecs.umich.edu if (!up) 8087342Sgblack@eecs.umich.edu addr = 4 * offset; 8097175Sgblack@eecs.umich.edu 8107342Sgblack@eecs.umich.edu bool tempUp = up; 8117175Sgblack@eecs.umich.edu for (int j = 0; j < count; j++) { 8127175Sgblack@eecs.umich.edu if (load) { 8137639Sgblack@eecs.umich.edu if (single) { 8147639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrFpUop(machInst, vd++, rn, 8157639Sgblack@eecs.umich.edu tempUp, addr); 8167639Sgblack@eecs.umich.edu } else { 8177639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDBFpUop(machInst, vd++, rn, 8187639Sgblack@eecs.umich.edu tempUp, addr); 8197639Sgblack@eecs.umich.edu microOps[i++] = new MicroLdrDTFpUop(machInst, vd++, rn, tempUp, 8207639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8217639Sgblack@eecs.umich.edu } 8227175Sgblack@eecs.umich.edu } else { 8237639Sgblack@eecs.umich.edu if (single) { 8247639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrFpUop(machInst, vd++, rn, 8257639Sgblack@eecs.umich.edu tempUp, addr); 8267639Sgblack@eecs.umich.edu } else { 8277639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDBFpUop(machInst, vd++, rn, 8287639Sgblack@eecs.umich.edu tempUp, addr); 8297639Sgblack@eecs.umich.edu microOps[i++] = new MicroStrDTFpUop(machInst, vd++, rn, tempUp, 8307639Sgblack@eecs.umich.edu addr + (up ? 4 : -4)); 8317639Sgblack@eecs.umich.edu } 8327175Sgblack@eecs.umich.edu } 8337342Sgblack@eecs.umich.edu if (!tempUp) { 8347342Sgblack@eecs.umich.edu addr -= (single ? 4 : 8); 8357342Sgblack@eecs.umich.edu // The microops don't handle negative displacement, so turn if we 8367342Sgblack@eecs.umich.edu // hit zero, flip polarity and start adding. 8377395Sgblack@eecs.umich.edu if (addr <= 0) { 8387342Sgblack@eecs.umich.edu tempUp = true; 8397395Sgblack@eecs.umich.edu addr = -addr; 8407342Sgblack@eecs.umich.edu } 8417342Sgblack@eecs.umich.edu } else { 8427342Sgblack@eecs.umich.edu addr += (single ? 4 : 8); 8437342Sgblack@eecs.umich.edu } 8447175Sgblack@eecs.umich.edu } 8457175Sgblack@eecs.umich.edu 8467175Sgblack@eecs.umich.edu if (writeback) { 8477175Sgblack@eecs.umich.edu if (up) { 8487175Sgblack@eecs.umich.edu microOps[i++] = 8497175Sgblack@eecs.umich.edu new MicroAddiUop(machInst, rn, rn, 4 * offset); 8507175Sgblack@eecs.umich.edu } else { 8517175Sgblack@eecs.umich.edu microOps[i++] = 8527175Sgblack@eecs.umich.edu new MicroSubiUop(machInst, rn, rn, 4 * offset); 8537175Sgblack@eecs.umich.edu } 8547175Sgblack@eecs.umich.edu } 8557175Sgblack@eecs.umich.edu 8567342Sgblack@eecs.umich.edu assert(numMicroops == i); 8577175Sgblack@eecs.umich.edu microOps[numMicroops - 1]->setLastMicroop(); 8587343Sgblack@eecs.umich.edu 8597343Sgblack@eecs.umich.edu for (StaticInstPtr *curUop = microOps; 8607343Sgblack@eecs.umich.edu !(*curUop)->isLastMicroop(); curUop++) { 8617343Sgblack@eecs.umich.edu MicroOp * uopPtr = dynamic_cast<MicroOp *>(curUop->get()); 8627343Sgblack@eecs.umich.edu assert(uopPtr); 8637343Sgblack@eecs.umich.edu uopPtr->setDelayedCommit(); 8647343Sgblack@eecs.umich.edu } 8657170Sgblack@eecs.umich.edu} 8667175Sgblack@eecs.umich.edu 8677615Sminkyu.jeong@arm.comstd::string 8687639Sgblack@eecs.umich.eduMicroIntImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8697639Sgblack@eecs.umich.edu{ 8707639Sgblack@eecs.umich.edu std::stringstream ss; 8717639Sgblack@eecs.umich.edu printMnemonic(ss); 8727639Sgblack@eecs.umich.edu printReg(ss, ura); 8737639Sgblack@eecs.umich.edu ss << ", "; 8747639Sgblack@eecs.umich.edu printReg(ss, urb); 8757639Sgblack@eecs.umich.edu ss << ", "; 8767639Sgblack@eecs.umich.edu ccprintf(ss, "#%d", imm); 8777639Sgblack@eecs.umich.edu return ss.str(); 8787639Sgblack@eecs.umich.edu} 8797639Sgblack@eecs.umich.edu 8807639Sgblack@eecs.umich.edustd::string 8817615Sminkyu.jeong@arm.comMicroIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8827615Sminkyu.jeong@arm.com{ 8837615Sminkyu.jeong@arm.com std::stringstream ss; 8847615Sminkyu.jeong@arm.com printMnemonic(ss); 8857615Sminkyu.jeong@arm.com printReg(ss, ura); 8867615Sminkyu.jeong@arm.com ss << ", "; 8877615Sminkyu.jeong@arm.com printReg(ss, urb); 8887615Sminkyu.jeong@arm.com ss << ", "; 8897639Sgblack@eecs.umich.edu printReg(ss, urc); 8907615Sminkyu.jeong@arm.com return ss.str(); 8917175Sgblack@eecs.umich.edu} 8927615Sminkyu.jeong@arm.com 8937615Sminkyu.jeong@arm.comstd::string 8947615Sminkyu.jeong@arm.comMicroMemOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 8957615Sminkyu.jeong@arm.com{ 8967615Sminkyu.jeong@arm.com std::stringstream ss; 8977615Sminkyu.jeong@arm.com printMnemonic(ss); 8987615Sminkyu.jeong@arm.com printReg(ss, ura); 8997615Sminkyu.jeong@arm.com ss << ", ["; 9007615Sminkyu.jeong@arm.com printReg(ss, urb); 9017615Sminkyu.jeong@arm.com ss << ", "; 9027615Sminkyu.jeong@arm.com ccprintf(ss, "#%d", imm); 9037615Sminkyu.jeong@arm.com ss << "]"; 9047615Sminkyu.jeong@arm.com return ss.str(); 9057615Sminkyu.jeong@arm.com} 9067615Sminkyu.jeong@arm.com 9077615Sminkyu.jeong@arm.com} 908