branch64.hh revision 10037
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39#ifndef __ARCH_ARM_INSTS_BRANCH64_HH__ 40#define __ARCH_ARM_INSTS_BRANCH64_HH__ 41 42#include "arch/arm/insts/static_inst.hh" 43 44namespace ArmISA 45{ 46// Branch to a target computed with an immediate 47class BranchImm64 : public ArmStaticInst 48{ 49 protected: 50 int64_t imm; 51 52 public: 53 BranchImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 54 int64_t _imm) : 55 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm) 56 {} 57 58 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 59 60 /// Explicitly import the otherwise hidden branchTarget 61 using StaticInst::branchTarget; 62 63 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 64}; 65 66// Conditionally Branch to a target computed with an immediate 67class BranchImmCond64 : public BranchImm64 68{ 69 protected: 70 ConditionCode condCode; 71 72 public: 73 BranchImmCond64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 74 int64_t _imm, ConditionCode _condCode) : 75 BranchImm64(mnem, _machInst, __opClass, _imm), condCode(_condCode) 76 {} 77 78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 79}; 80 81// Branch to a target computed with a register 82class BranchReg64 : public ArmStaticInst 83{ 84 protected: 85 IntRegIndex op1; 86 87 public: 88 BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 89 IntRegIndex _op1) : 90 ArmStaticInst(mnem, _machInst, __opClass), op1(_op1) 91 {} 92 93 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 94}; 95 96// Ret instruction 97class BranchRet64 : public BranchReg64 98{ 99 public: 100 BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 101 IntRegIndex _op1) : 102 BranchReg64(mnem, _machInst, __opClass, _op1) 103 {} 104 105 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 106}; 107 108// Eret instruction 109class BranchEret64 : public ArmStaticInst 110{ 111 public: 112 BranchEret64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 113 ArmStaticInst(mnem, _machInst, __opClass) 114 {} 115 116 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 117}; 118 119// Branch to a target computed with an immediate and a register 120class BranchImmReg64 : public ArmStaticInst 121{ 122 protected: 123 int64_t imm; 124 IntRegIndex op1; 125 126 public: 127 BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 128 int64_t _imm, IntRegIndex _op1) : 129 ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1) 130 {} 131 132 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 133 134 /// Explicitly import the otherwise hidden branchTarget 135 using StaticInst::branchTarget; 136 137 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 138}; 139 140// Branch to a target computed with two immediates 141class BranchImmImmReg64 : public ArmStaticInst 142{ 143 protected: 144 int64_t imm1; 145 int64_t imm2; 146 IntRegIndex op1; 147 148 public: 149 BranchImmImmReg64(const char *mnem, ExtMachInst _machInst, 150 OpClass __opClass, int64_t _imm1, int64_t _imm2, 151 IntRegIndex _op1) : 152 ArmStaticInst(mnem, _machInst, __opClass), 153 imm1(_imm1), imm2(_imm2), op1(_op1) 154 {} 155 156 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 157 158 /// Explicitly import the otherwise hidden branchTarget 159 using StaticInst::branchTarget; 160 161 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 162}; 163 164} 165 166#endif //__ARCH_ARM_INSTS_BRANCH_HH__ 167