branch.cc revision 6262:43950710afdc
1/* Copyright (c) 2007-2008 The Florida State University 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution; 11 * neither the name of the copyright holders nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Authors: Stephen Hines 28 */ 29 30#include "arch/arm/insts/branch.hh" 31#include "base/loader/symtab.hh" 32 33namespace ArmISA 34{ 35Addr 36Branch::branchTarget(Addr branchPC) const 37{ 38 return branchPC + 8 + disp; 39} 40 41Addr 42Jump::branchTarget(ThreadContext *tc) const 43{ 44 Addr NPC = tc->readPC() + 8; 45 uint64_t Rb = tc->readIntReg(_srcRegIdx[0]); 46 return (Rb & ~3) | (NPC & 1); 47} 48 49const std::string & 50PCDependentDisassembly::disassemble(Addr pc, 51 const SymbolTable *symtab) const 52{ 53 if (!cachedDisassembly || 54 pc != cachedPC || symtab != cachedSymtab) 55 { 56 if (cachedDisassembly) 57 delete cachedDisassembly; 58 59 cachedDisassembly = 60 new std::string(generateDisassembly(pc, symtab)); 61 cachedPC = pc; 62 cachedSymtab = symtab; 63 } 64 65 return *cachedDisassembly; 66} 67 68std::string 69Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const 70{ 71 std::stringstream ss; 72 73 printMnemonic(ss); 74 75 Addr target = pc + 8 + disp; 76 77 std::string str; 78 if (symtab && symtab->findSymbol(target, str)) 79 ss << str; 80 else 81 ccprintf(ss, "0x%x", target); 82 83 return ss.str(); 84} 85 86std::string 87BranchExchange::generateDisassembly(Addr pc, const SymbolTable *symtab) const 88{ 89 std::stringstream ss; 90 printMnemonic(ss); 91 if (_numSrcRegs > 0) { 92 printReg(ss, _srcRegIdx[0]); 93 } 94 return ss.str(); 95} 96 97std::string 98Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const 99{ 100 std::stringstream ss; 101 printMnemonic(ss); 102 return ss.str(); 103} 104} 105