faults.hh revision 8782
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 48#include "arch/arm/miscregs.hh" 49#include "arch/arm/types.hh" 50#include "base/misc.hh" 51#include "sim/faults.hh" 52#include "sim/full_system.hh" 53 54// The design of the "name" and "vect" functions is in sim/faults.hh 55 56namespace ArmISA 57{ 58typedef const Addr FaultOffset; 59 60class ArmFault : public FaultBase 61{ 62 protected: 63 Addr getVector(ThreadContext *tc); 64 65 public: 66 enum StatusEncoding 67 { 68 // Fault Status register encodings 69 // ARM ARM B3.9.4 70 AlignmentFault = 0x1, 71 DebugEvent = 0x2, 72 AccessFlag0 = 0x3, 73 InstructionCacheMaintenance = 0x4, 74 Translation0 = 0x5, 75 AccessFlag1 = 0x6, 76 Translation1 = 0x7, 77 SynchronousExternalAbort0 = 0x8, 78 Domain0 = 0x9, 79 SynchronousExternalAbort1 = 0x8, 80 Domain1 = 0xb, 81 TranslationTableWalkExtAbt0 = 0xc, 82 Permission0 = 0xd, 83 TranslationTableWalkExtAbt1 = 0xe, 84 Permission1 = 0xf, 85 AsynchronousExternalAbort = 0x16, 86 MemoryAccessAsynchronousParityError = 0x18, 87 MemoryAccessSynchronousParityError = 0x19, 88 TranslationTableWalkPrtyErr0 = 0x1c, 89 TranslationTableWalkPrtyErr1 = 0x1e, 90 91 // not a real fault. This is a status code 92 // to allow the translation function to inform 93 // the memory access function not to proceed 94 // for a Prefetch that misses in the TLB. 95 PrefetchTLBMiss = 0x1f, 96 PrefetchUncacheable = 0x20 97 }; 98 99 struct FaultVals 100 { 101 const FaultName name; 102 const FaultOffset offset; 103 const OperatingMode nextMode; 104 const uint8_t armPcOffset; 105 const uint8_t thumbPcOffset; 106 const bool abortDisable; 107 const bool fiqDisable; 108 FaultStat count; 109 }; 110 111 void invoke(ThreadContext *tc, 112 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 113 virtual FaultStat& countStat() = 0; 114 virtual FaultOffset offset() = 0; 115 virtual OperatingMode nextMode() = 0; 116 virtual uint8_t armPcOffset() = 0; 117 virtual uint8_t thumbPcOffset() = 0; 118 virtual bool abortDisable() = 0; 119 virtual bool fiqDisable() = 0; 120}; 121 122template<typename T> 123class ArmFaultVals : public ArmFault 124{ 125 protected: 126 static FaultVals vals; 127 128 public: 129 FaultName name() const { return vals.name; } 130 FaultStat & countStat() {return vals.count;} 131 FaultOffset offset() { return vals.offset; } 132 OperatingMode nextMode() { return vals.nextMode; } 133 uint8_t armPcOffset() { return vals.armPcOffset; } 134 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 135 bool abortDisable() { return vals.abortDisable; } 136 bool fiqDisable() { return vals.fiqDisable; } 137}; 138 139class Reset : public ArmFaultVals<Reset> 140{ 141 public: 142 void invoke(ThreadContext *tc, 143 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 144}; 145 146class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 147{ 148 protected: 149 ExtMachInst machInst; 150 bool unknown; 151 const char *mnemonic; 152 bool disabled; 153 154 public: 155 UndefinedInstruction(ExtMachInst _machInst, 156 bool _unknown, 157 const char *_mnemonic = NULL, 158 bool _disabled = false) : 159 machInst(_machInst), unknown(_unknown), 160 mnemonic(_mnemonic), disabled(_disabled) 161 { 162 } 163 UndefinedInstruction() : 164 machInst(0), unknown(false), mnemonic("undefined"), disabled(false) 165 {} 166 167 void invoke(ThreadContext *tc, 168 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 169}; 170 171class SupervisorCall : public ArmFaultVals<SupervisorCall> 172{ 173 protected: 174 ExtMachInst machInst; 175 176 public: 177 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 178 {} 179 SupervisorCall() : machInst(0) 180 {} 181 182 void invoke(ThreadContext *tc, 183 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 184}; 185 186template <class T> 187class AbortFault : public ArmFaultVals<T> 188{ 189 protected: 190 Addr faultAddr; 191 bool write; 192 uint8_t domain; 193 uint8_t status; 194 195 public: 196 AbortFault(Addr _faultAddr, bool _write, 197 uint8_t _domain, uint8_t _status) : 198 faultAddr(_faultAddr), write(_write), 199 domain(_domain), status(_status) 200 {} 201 202 void invoke(ThreadContext *tc, 203 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 204}; 205 206class PrefetchAbort : public AbortFault<PrefetchAbort> 207{ 208 public: 209 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 210 static const MiscRegIndex FarIndex = MISCREG_IFAR; 211 212 PrefetchAbort(Addr _addr, uint8_t _status) : 213 AbortFault<PrefetchAbort>(_addr, false, 0, _status) 214 {} 215}; 216 217class DataAbort : public AbortFault<DataAbort> 218{ 219 public: 220 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 221 static const MiscRegIndex FarIndex = MISCREG_DFAR; 222 223 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 224 AbortFault<DataAbort>(_addr, _write, _domain, _status) 225 {} 226}; 227 228class Interrupt : public ArmFaultVals<Interrupt> {}; 229class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 230 231// A fault that flushes the pipe, excluding the faulting instructions 232class FlushPipe : public ArmFaultVals<FlushPipe> 233{ 234 public: 235 FlushPipe() {} 236 void invoke(ThreadContext *tc, 237 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 238}; 239 240// A fault that flushes the pipe, excluding the faulting instructions 241class ArmSev : public ArmFaultVals<ArmSev> 242{ 243 public: 244 ArmSev () {} 245 void invoke(ThreadContext *tc, 246 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 247}; 248 249} // namespace ArmISA 250 251#endif // __ARM_FAULTS_HH__ 252