faults.hh revision 7850
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 */ 44 45#ifndef __ARM_FAULTS_HH__ 46#define __ARM_FAULTS_HH__ 47 48#include "arch/arm/miscregs.hh" 49#include "arch/arm/types.hh" 50#include "config/full_system.hh" 51#include "sim/faults.hh" 52#include "base/misc.hh" 53 54// The design of the "name" and "vect" functions is in sim/faults.hh 55 56namespace ArmISA 57{ 58typedef const Addr FaultOffset; 59 60class ArmFault : public FaultBase 61{ 62 protected: 63 Addr getVector(ThreadContext *tc); 64 65 public: 66 enum StatusEncoding 67 { 68 // Fault Status register encodings 69 // ARM ARM B3.9.4 70 AlignmentFault = 0x1, 71 DebugEvent = 0x2, 72 AccessFlag0 = 0x3, 73 InstructionCacheMaintenance = 0x4, 74 Translation0 = 0x5, 75 AccessFlag1 = 0x6, 76 Translation1 = 0x7, 77 SynchronousExternalAbort0 = 0x8, 78 Domain0 = 0x9, 79 SynchronousExternalAbort1 = 0x8, 80 Domain1 = 0xb, 81 TranslationTableWalkExtAbt0 = 0xc, 82 Permission0 = 0xd, 83 TranslationTableWalkExtAbt1 = 0xe, 84 Permission1 = 0xf, 85 AsynchronousExternalAbort = 0x16, 86 MemoryAccessAsynchronousParityError = 0x18, 87 MemoryAccessSynchronousParityError = 0x19, 88 TranslationTableWalkPrtyErr0 = 0x1c, 89 TranslationTableWalkPrtyErr1 = 0x1e, 90 91 // not a real fault. This is a status code 92 // to allow the translation function to inform 93 // the memory access function not to proceed 94 // for a Prefetch that misses in the TLB. 95 PrefetchTLBMiss = 0x1f, 96 PrefetchUncacheable = 0x20 97 }; 98 99 struct FaultVals 100 { 101 const FaultName name; 102 const FaultOffset offset; 103 const OperatingMode nextMode; 104 const uint8_t armPcOffset; 105 const uint8_t thumbPcOffset; 106 const bool abortDisable; 107 const bool fiqDisable; 108 FaultStat count; 109 }; 110 111#if FULL_SYSTEM 112 void invoke(ThreadContext *tc, 113 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 114#endif 115 virtual FaultStat& countStat() = 0; 116 virtual FaultOffset offset() = 0; 117 virtual OperatingMode nextMode() = 0; 118 virtual uint8_t armPcOffset() = 0; 119 virtual uint8_t thumbPcOffset() = 0; 120 virtual bool abortDisable() = 0; 121 virtual bool fiqDisable() = 0; 122}; 123 124template<typename T> 125class ArmFaultVals : public ArmFault 126{ 127 protected: 128 static FaultVals vals; 129 130 public: 131 FaultName name() const { return vals.name; } 132 FaultStat & countStat() {return vals.count;} 133 FaultOffset offset() { return vals.offset; } 134 OperatingMode nextMode() { return vals.nextMode; } 135 uint8_t armPcOffset() { return vals.armPcOffset; } 136 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 137 bool abortDisable() { return vals.abortDisable; } 138 bool fiqDisable() { return vals.fiqDisable; } 139}; 140 141class Reset : public ArmFaultVals<Reset> 142#if FULL_SYSTEM 143{ 144 public: 145 void invoke(ThreadContext *tc, 146 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 147}; 148#else 149{}; 150#endif //FULL_SYSTEM 151 152class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 153{ 154#if !FULL_SYSTEM 155 protected: 156 ExtMachInst machInst; 157 bool unknown; 158 const char *mnemonic; 159 bool disabled; 160 161 public: 162 UndefinedInstruction(ExtMachInst _machInst, 163 bool _unknown, 164 const char *_mnemonic = NULL, 165 bool _disabled = false) : 166 machInst(_machInst), unknown(_unknown), 167 mnemonic(_mnemonic), disabled(_disabled) 168 { 169 } 170 171 void invoke(ThreadContext *tc, 172 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 173#endif 174}; 175 176class SupervisorCall : public ArmFaultVals<SupervisorCall> 177{ 178#if !FULL_SYSTEM 179 protected: 180 ExtMachInst machInst; 181 182 public: 183 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 184 {} 185 186 void invoke(ThreadContext *tc, 187 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 188#endif 189}; 190 191template <class T> 192class AbortFault : public ArmFaultVals<T> 193{ 194 protected: 195 Addr faultAddr; 196 bool write; 197 uint8_t domain; 198 uint8_t status; 199 200 public: 201 AbortFault(Addr _faultAddr, bool _write, 202 uint8_t _domain, uint8_t _status) : 203 faultAddr(_faultAddr), write(_write), 204 domain(_domain), status(_status) 205 {} 206 207 void invoke(ThreadContext *tc, 208 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 209}; 210 211class PrefetchAbort : public AbortFault<PrefetchAbort> 212{ 213 public: 214 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 215 static const MiscRegIndex FarIndex = MISCREG_IFAR; 216 217 PrefetchAbort(Addr _addr, uint8_t _status) : 218 AbortFault<PrefetchAbort>(_addr, false, 0, _status) 219 {} 220}; 221 222class DataAbort : public AbortFault<DataAbort> 223{ 224 public: 225 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 226 static const MiscRegIndex FarIndex = MISCREG_DFAR; 227 228 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 229 AbortFault<DataAbort>(_addr, _write, _domain, _status) 230 {} 231}; 232 233class Interrupt : public ArmFaultVals<Interrupt> {}; 234class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 235 236// A fault that flushes the pipe, excluding the faulting instructions 237class FlushPipe : public ArmFaultVals<FlushPipe> 238{ 239 public: 240 FlushPipe() {} 241 void invoke(ThreadContext *tc, 242 StaticInstPtr inst = StaticInst::nullStaticInstPtr); 243}; 244 245static inline Fault genMachineCheckFault() 246{ 247 return new Reset(); 248} 249 250} // namespace ArmISA 251 252#endif // __ARM_FAULTS_HH__ 253