faults.hh revision 7640
11142Shsul@eecs.umich.edu/* 21142Shsul@eecs.umich.edu * Copyright (c) 2010 ARM Limited 31142Shsul@eecs.umich.edu * All rights reserved 41142Shsul@eecs.umich.edu * 51142Shsul@eecs.umich.edu * The license below extends only to copyright in the software and shall 61142Shsul@eecs.umich.edu * not be construed as granting a license to any other intellectual 71142Shsul@eecs.umich.edu * property including but not limited to intellectual property relating 81142Shsul@eecs.umich.edu * to a hardware implementation of the functionality of the software 91142Shsul@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 101142Shsul@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 111142Shsul@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 121142Shsul@eecs.umich.edu * modified or unmodified, in source code or in binary form. 131142Shsul@eecs.umich.edu * 141142Shsul@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 151142Shsul@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 161142Shsul@eecs.umich.edu * All rights reserved. 171175Sbinkertn@umich.edu * 181142Shsul@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 191142Shsul@eecs.umich.edu * modification, are permitted provided that the following conditions are 201142Shsul@eecs.umich.edu * met: redistributions of source code must retain the above copyright 211142Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 221142Shsul@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 231142Shsul@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 241142Shsul@eecs.umich.edu * documentation and/or other materials provided with the distribution; 251175Sbinkertn@umich.edu * neither the name of the copyright holders nor the names of its 261142Shsul@eecs.umich.edu * contributors may be used to endorse or promote products derived from 271142Shsul@eecs.umich.edu * this software without specific prior written permission. 281142Shsul@eecs.umich.edu * 291142Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 301175Sbinkertn@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 311142Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 321142Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 331142Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 341142Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 351175Sbinkertn@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 361142Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 371142Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 381142Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 391142Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 401142Shsul@eecs.umich.edu * 411142Shsul@eecs.umich.edu * Authors: Ali Saidi 421142Shsul@eecs.umich.edu * Gabe Black 431142Shsul@eecs.umich.edu */ 441142Shsul@eecs.umich.edu 451142Shsul@eecs.umich.edu#ifndef __ARM_FAULTS_HH__ 461142Shsul@eecs.umich.edu#define __ARM_FAULTS_HH__ 471142Shsul@eecs.umich.edu 481142Shsul@eecs.umich.edu#include "arch/arm/miscregs.hh" 491142Shsul@eecs.umich.edu#include "arch/arm/types.hh" 501142Shsul@eecs.umich.edu#include "config/full_system.hh" 511142Shsul@eecs.umich.edu#include "sim/faults.hh" 52#include "base/misc.hh" 53 54// The design of the "name" and "vect" functions is in sim/faults.hh 55 56namespace ArmISA 57{ 58typedef const Addr FaultOffset; 59 60class ArmFault : public FaultBase 61{ 62 protected: 63 Addr getVector(ThreadContext *tc); 64 65 public: 66 enum StatusEncoding 67 { 68 // Fault Status register encodings 69 // ARM ARM B3.9.4 70 AlignmentFault = 0x1, 71 DebugEvent = 0x2, 72 AccessFlag0 = 0x3, 73 InstructionCacheMaintenance = 0x4, 74 Translation0 = 0x5, 75 AccessFlag1 = 0x6, 76 Translation1 = 0x7, 77 SynchronousExternalAbort0 = 0x8, 78 Domain0 = 0x9, 79 SynchronousExternalAbort1 = 0x8, 80 Domain1 = 0xb, 81 TranslationTableWalkExtAbt0 = 0xc, 82 Permission0 = 0xd, 83 TranslationTableWalkExtAbt1 = 0xe, 84 Permission1 = 0xf, 85 AsynchronousExternalAbort = 0x16, 86 MemoryAccessAsynchronousParityError = 0x18, 87 MemoryAccessSynchronousParityError = 0x19, 88 TranslationTableWalkPrtyErr0 = 0x1c, 89 TranslationTableWalkPrtyErr1 = 0x1e, 90 91 // not a real fault. This is a status code 92 // to allow the translation function to inform 93 // the memory access function not to proceed 94 // for a Prefetch that misses in the TLB. 95 PrefetchTLBMiss 96 }; 97 98 struct FaultVals 99 { 100 const FaultName name; 101 const FaultOffset offset; 102 const OperatingMode nextMode; 103 const uint8_t armPcOffset; 104 const uint8_t thumbPcOffset; 105 const bool abortDisable; 106 const bool fiqDisable; 107 FaultStat count; 108 }; 109 110#if FULL_SYSTEM 111 void invoke(ThreadContext *tc); 112#endif 113 virtual FaultStat& countStat() = 0; 114 virtual FaultOffset offset() = 0; 115 virtual OperatingMode nextMode() = 0; 116 virtual uint8_t armPcOffset() = 0; 117 virtual uint8_t thumbPcOffset() = 0; 118 virtual bool abortDisable() = 0; 119 virtual bool fiqDisable() = 0; 120}; 121 122template<typename T> 123class ArmFaultVals : public ArmFault 124{ 125 protected: 126 static FaultVals vals; 127 128 public: 129 FaultName name() const { return vals.name; } 130 FaultStat & countStat() {return vals.count;} 131 FaultOffset offset() { return vals.offset; } 132 OperatingMode nextMode() { return vals.nextMode; } 133 uint8_t armPcOffset() { return vals.armPcOffset; } 134 uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 135 bool abortDisable() { return vals.abortDisable; } 136 bool fiqDisable() { return vals.fiqDisable; } 137}; 138 139class Reset : public ArmFaultVals<Reset> 140#if FULL_SYSTEM 141{ 142 public: 143 void invoke(ThreadContext *tc); 144}; 145#else 146{}; 147#endif //FULL_SYSTEM 148 149class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 150{ 151#if !FULL_SYSTEM 152 protected: 153 ExtMachInst machInst; 154 bool unknown; 155 const char *mnemonic; 156 bool disabled; 157 158 public: 159 UndefinedInstruction(ExtMachInst _machInst, 160 bool _unknown, 161 const char *_mnemonic = NULL, 162 bool _disabled = false) : 163 machInst(_machInst), unknown(_unknown), 164 mnemonic(_mnemonic), disabled(_disabled) 165 { 166 } 167 168 void invoke(ThreadContext *tc); 169#endif 170}; 171 172class SupervisorCall : public ArmFaultVals<SupervisorCall> 173{ 174#if !FULL_SYSTEM 175 protected: 176 ExtMachInst machInst; 177 178 public: 179 SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 180 {} 181 182 void invoke(ThreadContext *tc); 183#endif 184}; 185 186template <class T> 187class AbortFault : public ArmFaultVals<T> 188{ 189 protected: 190 Addr faultAddr; 191 bool write; 192 uint8_t domain; 193 uint8_t status; 194 195 public: 196 AbortFault(Addr _faultAddr, bool _write, 197 uint8_t _domain, uint8_t _status) : 198 faultAddr(_faultAddr), write(_write), 199 domain(_domain), status(_status) 200 {} 201 202 void invoke(ThreadContext *tc); 203}; 204 205class PrefetchAbort : public AbortFault<PrefetchAbort> 206{ 207 public: 208 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 209 static const MiscRegIndex FarIndex = MISCREG_IFAR; 210 211 PrefetchAbort(Addr _addr, uint8_t _status) : 212 AbortFault<PrefetchAbort>(_addr, false, 0, _status) 213 {} 214}; 215 216class DataAbort : public AbortFault<DataAbort> 217{ 218 public: 219 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 220 static const MiscRegIndex FarIndex = MISCREG_DFAR; 221 222 DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 223 AbortFault<DataAbort>(_addr, _write, _domain, _status) 224 {} 225}; 226 227class Interrupt : public ArmFaultVals<Interrupt> {}; 228class FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 229 230static inline Fault genMachineCheckFault() 231{ 232 return new Reset(); 233} 234 235} // ArmISA namespace 236 237#endif // __ARM_FAULTS_HH__ 238