faults.hh revision 12511:99c28b88d4d8
17735SN/A/* 27735SN/A * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 37735SN/A * All rights reserved 48835SAli.Saidi@ARM.com * 57935SN/A * The license below extends only to copyright in the software and shall 67935SN/A * not be construed as granting a license to any other intellectual 77935SN/A * property including but not limited to intellectual property relating 87735SN/A * to a hardware implementation of the functionality of the software 97735SN/A * licensed hereunder. You may use the software subject to the license 107735SN/A * terms below provided that you ensure that this notice is replicated 118891SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 128891SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 138983Snate@binkert.org * 148528SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 159055Ssaidi@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 168528SN/A * All rights reserved. 178528SN/A * 187735SN/A * Redistribution and use in source and binary forms, with or without 198983Snate@binkert.org * modification, are permitted provided that the following conditions are 207735SN/A * met: redistributions of source code must retain the above copyright 217735SN/A * notice, this list of conditions and the following disclaimer; 227735SN/A * redistributions in binary form must reproduce the above copyright 238891SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 248528SN/A * documentation and/or other materials provided with the distribution; 258721SN/A * neither the name of the copyright holders nor the names of its 267735SN/A * contributors may be used to endorse or promote products derived from 277735SN/A * this software without specific prior written permission. 287935SN/A * 297935SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 307935SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 317935SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 327935SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 337935SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 347935SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 358891SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367735SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377735SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 387735SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 397735SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407735SN/A * 418891SAli.Saidi@ARM.com * Authors: Ali Saidi 428721SN/A * Gabe Black 438721SN/A * Giacomo Gabrielli 447735SN/A * Thomas Grocutt 458891SAli.Saidi@ARM.com */ 468891SAli.Saidi@ARM.com 477735SN/A#ifndef __ARM_FAULTS_HH__ 488528SN/A#define __ARM_FAULTS_HH__ 498528SN/A 508528SN/A#include "arch/arm/miscregs.hh" 518528SN/A#include "arch/arm/pagetable.hh" 528528SN/A#include "arch/arm/types.hh" 538528SN/A#include "base/logging.hh" 548528SN/A#include "sim/faults.hh" 558528SN/A#include "sim/full_system.hh" 568528SN/A 578528SN/A// The design of the "name" and "vect" functions is in sim/faults.hh 588528SN/A 598528SN/Anamespace ArmISA 608528SN/A{ 618528SN/Atypedef Addr FaultOffset; 628528SN/A 638528SN/Aclass ArmFault : public FaultBase 648528SN/A{ 658983Snate@binkert.org protected: 668528SN/A ExtMachInst machInst; 678528SN/A uint32_t issRaw; 687735SN/A 697735SN/A // Helper variables for ARMv8 exception handling 707735SN/A bool from64; // True if the exception is generated from the AArch64 state 717735SN/A bool to64; // True if the exception is taken in AArch64 state 727735SN/A ExceptionLevel fromEL; // Source exception level 737735SN/A ExceptionLevel toEL; // Target exception level 747735SN/A OperatingMode fromMode; // Source operating mode 757735SN/A 767735SN/A bool hypRouted; // True if the fault has been routed to Hypervisor 777735SN/A 787735SN/A Addr getVector(ThreadContext *tc); 798983Snate@binkert.org Addr getVector64(ThreadContext *tc); 807735SN/A 817735SN/A public: 827735SN/A /// Generic fault source enums used to index into 837735SN/A /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 847735SN/A /// on the current register width state and the translation table format in 857735SN/A /// use 867735SN/A enum FaultSource 877735SN/A { 887735SN/A AlignmentFault = 0, 897735SN/A InstructionCacheMaintenance, // Short-desc. format only 907735SN/A SynchExtAbtOnTranslTableWalkLL, 917735SN/A SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 927735SN/A TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 937735SN/A AccessFlagLL = TranslationLL + 4, 947735SN/A DomainLL = AccessFlagLL + 4, 957735SN/A PermissionLL = DomainLL + 4, 967735SN/A DebugEvent = PermissionLL + 4, 978835SAli.Saidi@ARM.com SynchronousExternalAbort, 987735SN/A TLBConflictAbort, // Requires LPAE 997735SN/A SynchPtyErrOnMemoryAccess, 1007735SN/A AsynchronousExternalAbort, 1017735SN/A AsynchPtyErrOnMemoryAccess, 1027735SN/A AddressSizeLL, // AArch64 only 1038891SAli.Saidi@ARM.com 1047735SN/A // Not real faults. These are faults to allow the translation function 1057735SN/A // to inform the memory access function not to proceed for a prefetch 1067735SN/A // that misses in the TLB or that targets an uncacheable address 1077735SN/A PrefetchTLBMiss = AddressSizeLL + 4, 1088150SN/A PrefetchUncacheable, 1097735SN/A 1107735SN/A NumFaultSources, 1117735SN/A FaultSourceInvalid = 0xff 1127735SN/A }; 1138835SAli.Saidi@ARM.com 1147735SN/A /// Encodings of the fault sources when the short-desc. translation table 1157735SN/A /// format is in use (ARM ARM Issue C B3.13.3) 1167735SN/A static uint8_t shortDescFaultSources[NumFaultSources]; 1177735SN/A /// Encodings of the fault sources when the long-desc. translation table 1188835SAli.Saidi@ARM.com /// format is in use (ARM ARM Issue C B3.13.3) 1197735SN/A static uint8_t longDescFaultSources[NumFaultSources]; 1207735SN/A /// Encodings of the fault sources in AArch64 state 1217735SN/A static uint8_t aarch64FaultSources[NumFaultSources]; 1227735SN/A 1237735SN/A enum AnnotationIDs 1248891SAli.Saidi@ARM.com { 1257735SN/A S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 1267735SN/A OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 1277735SN/A SAS, // DataAbort: Syndrome Access Size 1287735SN/A SSE, // DataAbort: Syndrome Sign Extend 1297735SN/A SRT, // DataAbort: Syndrome Register Transfer 1307735SN/A 1317735SN/A // AArch64 only 1327735SN/A SF, // DataAbort: width of the accessed register is SixtyFour 1337735SN/A AR // DataAbort: Acquire/Release semantics 1347735SN/A }; 1357735SN/A 1367735SN/A enum TranMethod 1378891SAli.Saidi@ARM.com { 1387735SN/A LpaeTran, 1397735SN/A VmsaTran, 1407735SN/A UnknownTran 1418891SAli.Saidi@ARM.com }; 1427735SN/A 1437735SN/A struct FaultVals 1447735SN/A { 1457735SN/A const FaultName name; 1468150SN/A 1477735SN/A const FaultOffset offset; 1487735SN/A 1497735SN/A // Offsets used for exceptions taken in AArch64 state 1507735SN/A const uint16_t currELTOffset; 1518835SAli.Saidi@ARM.com const uint16_t currELHOffset; 1527735SN/A const uint16_t lowerEL64Offset; 1537735SN/A const uint16_t lowerEL32Offset; 1547735SN/A 1557735SN/A const OperatingMode nextMode; 1568835SAli.Saidi@ARM.com 1577735SN/A const uint8_t armPcOffset; 1587735SN/A const uint8_t thumbPcOffset; 1597735SN/A // The following two values are used in place of armPcOffset and 1607735SN/A // thumbPcOffset when the exception return address is saved into ELR 1617735SN/A // registers (exceptions taken in HYP mode or in AArch64 state) 1628891SAli.Saidi@ARM.com const uint8_t armPcElrOffset; 1637735SN/A const uint8_t thumbPcElrOffset; 1647735SN/A 1657735SN/A const bool hypTrappable; 1667735SN/A const bool abortDisable; 1677735SN/A const bool fiqDisable; 1687735SN/A 1697735SN/A // Exception class used to appropriately set the syndrome register 1707735SN/A // (exceptions taken in HYP mode or in AArch64 state) 1717735SN/A const ExceptionClass ec; 1727735SN/A 1737735SN/A FaultStat count; 1747735SN/A }; 1757735SN/A 1767735SN/A ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 1777735SN/A machInst(_machInst), issRaw(_iss), from64(false), to64(false), 1788891SAli.Saidi@ARM.com fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false) {} 1797735SN/A 1807735SN/A // Returns the actual syndrome register to use based on the target 1817735SN/A // exception level 1827735SN/A MiscRegIndex getSyndromeReg64() const; 1837735SN/A // Returns the actual fault address register to use based on the target 1847735SN/A // exception level 1857735SN/A MiscRegIndex getFaultAddrReg64() const; 1867735SN/A 1877735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 1889055Ssaidi@eecs.umich.edu StaticInst::nullStaticInstPtr) override; 1897735SN/A void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 1907735SN/A StaticInst::nullStaticInstPtr); 1917735SN/A virtual void annotate(AnnotationIDs id, uint64_t val) {} 1927735SN/A virtual FaultStat& countStat() = 0; 1937735SN/A virtual FaultOffset offset(ThreadContext *tc) = 0; 1948911SAli.Saidi@ARM.com virtual FaultOffset offset64(ThreadContext *tc) = 0; 1958891SAli.Saidi@ARM.com virtual OperatingMode nextMode() = 0; 1967735SN/A virtual bool routeToMonitor(ThreadContext *tc) const = 0; 1977735SN/A virtual bool routeToHyp(ThreadContext *tc) const { return false; } 1987735SN/A virtual uint8_t armPcOffset(bool isHyp) = 0; 1998891SAli.Saidi@ARM.com virtual uint8_t thumbPcOffset(bool isHyp) = 0; 2007735SN/A virtual uint8_t armPcElrOffset() = 0; 2017735SN/A virtual uint8_t thumbPcElrOffset() = 0; 2027735SN/A virtual bool abortDisable(ThreadContext *tc) = 0; 2037735SN/A virtual bool fiqDisable(ThreadContext *tc) = 0; 2048150SN/A virtual ExceptionClass ec(ThreadContext *tc) const = 0; 2057735SN/A virtual uint32_t iss() const = 0; 2067735SN/A virtual bool isStage2() const { return false; } 2077735SN/A virtual FSR getFsr(ThreadContext *tc) { return 0; } 2087735SN/A virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2098835SAli.Saidi@ARM.com}; 2107735SN/A 2117735SN/Atemplate<typename T> 2127735SN/Aclass ArmFaultVals : public ArmFault 2137735SN/A{ 2148835SAli.Saidi@ARM.com protected: 2157735SN/A static FaultVals vals; 2167735SN/A 2177735SN/A public: 2187735SN/A ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 2198891SAli.Saidi@ARM.com ArmFault(_machInst, _iss) {} 2208891SAli.Saidi@ARM.com FaultName name() const override { return vals.name; } 2217735SN/A FaultStat & countStat() override { return vals.count; } 2227735SN/A FaultOffset offset(ThreadContext *tc) override; 2237735SN/A 2248891SAli.Saidi@ARM.com FaultOffset offset64(ThreadContext *tc) override; 2257735SN/A 2267735SN/A OperatingMode nextMode() override { return vals.nextMode; } 2277735SN/A virtual bool routeToMonitor(ThreadContext *tc) const override { 2287735SN/A return false; 2298150SN/A } 2307735SN/A uint8_t armPcOffset(bool isHyp) override { 2317735SN/A return isHyp ? vals.armPcElrOffset 2327735SN/A : vals.armPcOffset; 2337735SN/A } 2348835SAli.Saidi@ARM.com uint8_t thumbPcOffset(bool isHyp) override { 2357735SN/A return isHyp ? vals.thumbPcElrOffset 2367735SN/A : vals.thumbPcOffset; 2377735SN/A } 2387735SN/A uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 2398835SAli.Saidi@ARM.com uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 2407735SN/A bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 2417735SN/A bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 2427735SN/A ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 2437735SN/A uint32_t iss() const override { return issRaw; } 2448891SAli.Saidi@ARM.com}; 2458891SAli.Saidi@ARM.com 2467735SN/Aclass Reset : public ArmFaultVals<Reset> 2477735SN/A{ 2489055Ssaidi@eecs.umich.edu public: 2497735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 2507735SN/A StaticInst::nullStaticInstPtr) override; 2517735SN/A}; 2527735SN/A 2537735SN/Aclass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2547735SN/A{ 2557735SN/A protected: 2568891SAli.Saidi@ARM.com bool unknown; 2578891SAli.Saidi@ARM.com bool disabled; 2587735SN/A ExceptionClass overrideEc; 2597735SN/A const char *mnemonic; 2607735SN/A 2618528SN/A public: 2627735SN/A UndefinedInstruction(ExtMachInst _machInst, 2637735SN/A bool _unknown, 2647735SN/A const char *_mnemonic = NULL, 2657735SN/A bool _disabled = false) : 2667735SN/A ArmFaultVals<UndefinedInstruction>(_machInst), 2677735SN/A unknown(_unknown), disabled(_disabled), 2687735SN/A overrideEc(EC_INVALID), mnemonic(_mnemonic) 2697735SN/A {} 2707735SN/A UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 2717735SN/A ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 2727735SN/A ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 2737735SN/A unknown(false), disabled(true), overrideEc(_overrideEc), 2747735SN/A mnemonic(_mnemonic) 2757735SN/A {} 2768983Snate@binkert.org 2778983Snate@binkert.org void invoke(ThreadContext *tc, const StaticInstPtr &inst = 2787735SN/A StaticInst::nullStaticInstPtr) override; 2798983Snate@binkert.org bool routeToHyp(ThreadContext *tc) const override; 2807735SN/A ExceptionClass ec(ThreadContext *tc) const override; 2817735SN/A uint32_t iss() const override; 2827735SN/A}; 2837735SN/A 2848891SAli.Saidi@ARM.comclass SupervisorCall : public ArmFaultVals<SupervisorCall> 2858891SAli.Saidi@ARM.com{ 2867735SN/A protected: 2877735SN/A ExceptionClass overrideEc; 2887735SN/A public: 2898911SAli.Saidi@ARM.com SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 2907735SN/A ExceptionClass _overrideEc = EC_INVALID) : 2918891SAli.Saidi@ARM.com ArmFaultVals<SupervisorCall>(_machInst, _iss), 2928891SAli.Saidi@ARM.com overrideEc(_overrideEc) 2938528SN/A {} 2947735SN/A 2957735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 2968288SN/A StaticInst::nullStaticInstPtr) override; 2978288SN/A bool routeToHyp(ThreadContext *tc) const override; 2988288SN/A ExceptionClass ec(ThreadContext *tc) const override; 2998288SN/A uint32_t iss() const override; 3008288SN/A}; 3018891SAli.Saidi@ARM.com 3028288SN/Aclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 3037735SN/A{ 3047735SN/A public: 3057735SN/A SecureMonitorCall(ExtMachInst _machInst) : 3067735SN/A ArmFaultVals<SecureMonitorCall>(_machInst) 3077735SN/A {} 3087735SN/A 3097735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 3108891SAli.Saidi@ARM.com StaticInst::nullStaticInstPtr) override; 3117735SN/A ExceptionClass ec(ThreadContext *tc) const override; 3128213SN/A uint32_t iss() const override; 3138213SN/A}; 3148213SN/A 3158213SN/Aclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 3168213SN/A{ 3178213SN/A protected: 3188213SN/A ExtMachInst machInst; 3198213SN/A ExceptionClass overrideEc; 3208213SN/A 3218213SN/A public: 3228213SN/A SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 3238213SN/A ExceptionClass _overrideEc = EC_INVALID) : 3248213SN/A ArmFaultVals<SupervisorTrap>(_machInst, _iss), 3258213SN/A overrideEc(_overrideEc) 3268213SN/A {} 3278213SN/A 3288213SN/A bool routeToHyp(ThreadContext *tc) const override; 3298213SN/A uint32_t iss() const override; 3308213SN/A ExceptionClass ec(ThreadContext *tc) const override; 3318213SN/A}; 3328213SN/A 3338213SN/Aclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 3348213SN/A{ 3358213SN/A protected: 3368213SN/A ExtMachInst machInst; 3378213SN/A ExceptionClass overrideEc; 3388213SN/A 3398213SN/A public: 3408213SN/A SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 3418213SN/A ExceptionClass _overrideEc = EC_INVALID) : 3428213SN/A ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 3438213SN/A overrideEc(_overrideEc) 3448213SN/A {} 3458213SN/A 3468213SN/A ExceptionClass ec(ThreadContext *tc) const override; 3478213SN/A}; 3488213SN/A 3498213SN/Aclass HypervisorCall : public ArmFaultVals<HypervisorCall> 3508213SN/A{ 3518213SN/A public: 3528213SN/A HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 3538213SN/A 3548528SN/A ExceptionClass ec(ThreadContext *tc) const override; 3558213SN/A}; 3568213SN/A 3578213SN/Aclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 3588528SN/A{ 3598528SN/A protected: 3608213SN/A ExtMachInst machInst; 3617951SN/A ExceptionClass overrideEc; 3627951SN/A 3637951SN/A public: 3648891SAli.Saidi@ARM.com HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 3658891SAli.Saidi@ARM.com ExceptionClass _overrideEc = EC_INVALID) : 3668891SAli.Saidi@ARM.com ArmFaultVals<HypervisorTrap>(_machInst, _iss), 3677951SN/A overrideEc(_overrideEc) 3687755SN/A {} 3697755SN/A 3707755SN/A ExceptionClass ec(ThreadContext *tc) const override; 3717755SN/A}; 3727755SN/A 3737755SN/Atemplate <class T> 3747755SN/Aclass AbortFault : public ArmFaultVals<T> 3757755SN/A{ 3767735SN/A protected: 3777755SN/A /** 3787735SN/A * The virtual address the fault occured at. If 2 stages of 3797951SN/A * translation are being used then this is the intermediate 3808891SAli.Saidi@ARM.com * physical address that is the starting point for the second 3818891SAli.Saidi@ARM.com * stage of translation. 3827735SN/A */ 3837735SN/A Addr faultAddr; 3847735SN/A /** 3857735SN/A * Original virtual address. If the fault was generated on the 3867735SN/A * second stage of translation then this variable stores the 3877735SN/A * virtual address used in the original stage 1 translation. 3887735SN/A */ 3897735SN/A Addr OVAddr; 3908891SAli.Saidi@ARM.com bool write; 3917735SN/A TlbEntry::DomainType domain; 3927735SN/A uint8_t source; 3937735SN/A uint8_t srcEncoded; 3948528SN/A bool stage2; 3957735SN/A bool s1ptw; 3967735SN/A ArmFault::TranMethod tranMethod; 3978288SN/A 3987735SN/A public: 3997735SN/A AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 4007735SN/A uint8_t _source, bool _stage2, 4017735SN/A ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 4027735SN/A faultAddr(_faultAddr), OVAddr(0), write(_write), 4037735SN/A domain(_domain), source(_source), srcEncoded(0), 4047735SN/A stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4057735SN/A {} 4068891SAli.Saidi@ARM.com 4077735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 4087735SN/A StaticInst::nullStaticInstPtr) override; 4097735SN/A 4107735SN/A FSR getFsr(ThreadContext *tc) override; 4117735SN/A bool abortDisable(ThreadContext *tc) override; 4127735SN/A uint32_t iss() const override; 4137735SN/A bool isStage2() const override { return stage2; } 4148288SN/A void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 4157735SN/A bool isMMUFault() const; 4167735SN/A}; 4177735SN/A 4188891SAli.Saidi@ARM.comclass PrefetchAbort : public AbortFault<PrefetchAbort> 4197735SN/A{ 4207735SN/A public: 4217735SN/A static const MiscRegIndex FsrIndex = MISCREG_IFSR; 4227735SN/A static const MiscRegIndex FarIndex = MISCREG_IFAR; 4237735SN/A static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4247735SN/A 4257735SN/A PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 4267735SN/A ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 4278891SAli.Saidi@ARM.com AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 4287735SN/A _source, _stage2, _tranMethod) 4297735SN/A {} 4307735SN/A 4317735SN/A ExceptionClass ec(ThreadContext *tc) const override; 4327735SN/A // @todo: external aborts should be routed if SCR.EA == 1 4337735SN/A bool routeToMonitor(ThreadContext *tc) const override; 4347735SN/A bool routeToHyp(ThreadContext *tc) const override; 4357735SN/A}; 4368891SAli.Saidi@ARM.com 4377735SN/Aclass DataAbort : public AbortFault<DataAbort> 4387735SN/A{ 4397735SN/A public: 4407735SN/A static const MiscRegIndex FsrIndex = MISCREG_DFSR; 4417735SN/A static const MiscRegIndex FarIndex = MISCREG_DFAR; 4427735SN/A static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 4437735SN/A bool isv; 4447735SN/A uint8_t sas; 4458891SAli.Saidi@ARM.com uint8_t sse; 4467735SN/A uint8_t srt; 4477755SN/A 4487755SN/A // AArch64 only 4497755SN/A bool sf; 4507755SN/A bool ar; 4517951SN/A 4527755SN/A DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 4537951SN/A bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 4547735SN/A AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 4557735SN/A _tranMethod), 4567735SN/A isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4577951SN/A {} 4588891SAli.Saidi@ARM.com 4597735SN/A ExceptionClass ec(ThreadContext *tc) const override; 4607755SN/A // @todo: external aborts should be routed if SCR.EA == 1 4617755SN/A bool routeToMonitor(ThreadContext *tc) const override; 4627755SN/A bool routeToHyp(ThreadContext *tc) const override; 4637755SN/A uint32_t iss() const override; 4647951SN/A void annotate(AnnotationIDs id, uint64_t val) override; 4657755SN/A}; 4667951SN/A 4677735SN/Aclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 4687735SN/A{ 4697735SN/A public: 4707951SN/A static const MiscRegIndex FsrIndex = MISCREG_DFSR; 4718891SAli.Saidi@ARM.com static const MiscRegIndex FarIndex = MISCREG_DFAR; 4727735SN/A static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 4737735SN/A 4747735SN/A VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 4758528SN/A uint8_t _source) : 4767735SN/A AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 4777735SN/A {} 4787735SN/A 4797735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 4807735SN/A}; 4817735SN/A 4827735SN/Aclass Interrupt : public ArmFaultVals<Interrupt> 4837735SN/A{ 4847735SN/A public: 4857735SN/A bool routeToMonitor(ThreadContext *tc) const override; 4867735SN/A bool routeToHyp(ThreadContext *tc) const override; 4878891SAli.Saidi@ARM.com bool abortDisable(ThreadContext *tc) override; 4887735SN/A}; 4898528SN/A 4908528SN/Aclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 4918528SN/A{ 4928528SN/A public: 4938528SN/A VirtualInterrupt(); 4948528SN/A}; 4958528SN/A 4968528SN/Aclass FastInterrupt : public ArmFaultVals<FastInterrupt> 4978528SN/A{ 4988891SAli.Saidi@ARM.com public: 4998528SN/A bool routeToMonitor(ThreadContext *tc) const override; 5007735SN/A bool routeToHyp(ThreadContext *tc) const override; 5017735SN/A bool abortDisable(ThreadContext *tc) override; 5027735SN/A bool fiqDisable(ThreadContext *tc) override; 5037735SN/A}; 5047735SN/A 5057735SN/Aclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 5067735SN/A{ 5078891SAli.Saidi@ARM.com public: 5088891SAli.Saidi@ARM.com VirtualFastInterrupt(); 5098891SAli.Saidi@ARM.com}; 5108983Snate@binkert.org 5118983Snate@binkert.org/// PC alignment fault (AArch64 only) 5128891SAli.Saidi@ARM.comclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 5138983Snate@binkert.org{ 5148891SAli.Saidi@ARM.com protected: 5158891SAli.Saidi@ARM.com /// The unaligned value of the PC 5168891SAli.Saidi@ARM.com Addr faultPC; 5178891SAli.Saidi@ARM.com public: 5188891SAli.Saidi@ARM.com PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 5198891SAli.Saidi@ARM.com {} 5207735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 5217735SN/A StaticInst::nullStaticInstPtr) override; 5227735SN/A}; 5238288SN/A 5247735SN/A/// Stack pointer alignment fault (AArch64 only) 5257735SN/Aclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 5268528SN/A{ 5278528SN/A public: 5287735SN/A SPAlignmentFault(); 5298891SAli.Saidi@ARM.com}; 5307735SN/A 5318911SAli.Saidi@ARM.com/// System error (AArch64 only) 5328911SAli.Saidi@ARM.comclass SystemError : public ArmFaultVals<SystemError> 5338911SAli.Saidi@ARM.com{ 5348911SAli.Saidi@ARM.com public: 5358911SAli.Saidi@ARM.com SystemError(); 5368911SAli.Saidi@ARM.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 5377735SN/A StaticInst::nullStaticInstPtr) override; 5387735SN/A bool routeToMonitor(ThreadContext *tc) const override; 5397735SN/A bool routeToHyp(ThreadContext *tc) const override; 5408911SAli.Saidi@ARM.com}; 5418891SAli.Saidi@ARM.com 5427735SN/A/// System error (AArch64 only) 5437735SN/Aclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 5447735SN/A{ 5457735SN/A public: 5467735SN/A SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 5477735SN/A 5487735SN/A bool routeToHyp(ThreadContext *tc) const override; 5497735SN/A}; 5508891SAli.Saidi@ARM.com 5517735SN/A// A fault that flushes the pipe, excluding the faulting instructions 5527735SN/Aclass ArmSev : public ArmFaultVals<ArmSev> 5537735SN/A{ 5547735SN/A public: 5557735SN/A ArmSev () {} 5567735SN/A void invoke(ThreadContext *tc, const StaticInstPtr &inst = 5577735SN/A StaticInst::nullStaticInstPtr) override; 5587735SN/A}; 5598891SAli.Saidi@ARM.com 5607735SN/A/// Illegal Instruction Set State fault (AArch64 only) 5617735SN/Aclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 5627735SN/A{ 5637735SN/A public: 5647735SN/A IllegalInstSetStateFault(); 5657735SN/A}; 5667735SN/A 5677735SN/A/* 5688891SAli.Saidi@ARM.com * Explicitly declare template static member variables to avoid warnings 5697735SN/A * in some clang versions 5707735SN/A */ 5717735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 5727735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 5737735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 5747735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 5757735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 5767735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 5778891SAli.Saidi@ARM.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 5787735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 5797735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 5807735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 5817735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 5827735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 5837735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 5847735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 5857735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 5867735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 5877735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 5887735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 5897735SN/Atemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 5908891SAli.Saidi@ARM.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 5917735SN/A 5927735SN/A 5937735SN/A} // namespace ArmISA 5947735SN/A 5957735SN/A#endif // __ARM_FAULTS_HH__ 5967735SN/A