faults.hh revision 10417:710ee116eb68
112955Sgabeblack@google.com/* 212955Sgabeblack@google.com * Copyright (c) 2010, 2012-2013 ARM Limited 312955Sgabeblack@google.com * All rights reserved 412955Sgabeblack@google.com * 512955Sgabeblack@google.com * The license below extends only to copyright in the software and shall 612955Sgabeblack@google.com * not be construed as granting a license to any other intellectual 712955Sgabeblack@google.com * property including but not limited to intellectual property relating 812955Sgabeblack@google.com * to a hardware implementation of the functionality of the software 912955Sgabeblack@google.com * licensed hereunder. You may use the software subject to the license 1012955Sgabeblack@google.com * terms below provided that you ensure that this notice is replicated 1112955Sgabeblack@google.com * unmodified and in its entirety in all distributions of the software, 1212955Sgabeblack@google.com * modified or unmodified, in source code or in binary form. 1312955Sgabeblack@google.com * 1412955Sgabeblack@google.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 1512955Sgabeblack@google.com * Copyright (c) 2007-2008 The Florida State University 1612955Sgabeblack@google.com * All rights reserved. 1712955Sgabeblack@google.com * 1812955Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 1912955Sgabeblack@google.com * modification, are permitted provided that the following conditions are 2012955Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 2112955Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 2212955Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 2312955Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 2412955Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 2512955Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 2612955Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 2712955Sgabeblack@google.com * this software without specific prior written permission. 2812955Sgabeblack@google.com * 2912955Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 3012955Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3112955Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3212988Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3312955Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3412955Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3512955Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3612957Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3712957Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3812955Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3912955Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 4013086Sgabeblack@google.com * 4113086Sgabeblack@google.com * Authors: Ali Saidi 4212955Sgabeblack@google.com * Gabe Black 4312955Sgabeblack@google.com * Giacomo Gabrielli 4412955Sgabeblack@google.com * Thomas Grocutt 4512955Sgabeblack@google.com */ 4613086Sgabeblack@google.com 4712955Sgabeblack@google.com#ifndef __ARM_FAULTS_HH__ 4813086Sgabeblack@google.com#define __ARM_FAULTS_HH__ 4913086Sgabeblack@google.com 5013063Sgabeblack@google.com#include "arch/arm/miscregs.hh" 5112955Sgabeblack@google.com#include "arch/arm/pagetable.hh" 5212955Sgabeblack@google.com#include "arch/arm/types.hh" 5312955Sgabeblack@google.com#include "base/misc.hh" 5413086Sgabeblack@google.com#include "sim/faults.hh" 5513086Sgabeblack@google.com#include "sim/full_system.hh" 5613086Sgabeblack@google.com 5712955Sgabeblack@google.com// The design of the "name" and "vect" functions is in sim/faults.hh 5812955Sgabeblack@google.com 5912955Sgabeblack@google.comnamespace ArmISA 6012955Sgabeblack@google.com{ 6112988Sgabeblack@google.comtypedef const Addr FaultOffset; 6212988Sgabeblack@google.com 6312955Sgabeblack@google.comclass ArmFault : public FaultBase 6413179Sgabeblack@google.com{ 6513179Sgabeblack@google.com protected: 6613127Sgabeblack@google.com ExtMachInst machInst; 6712955Sgabeblack@google.com uint32_t issRaw; 6812955Sgabeblack@google.com 6912988Sgabeblack@google.com // Helper variables for ARMv8 exception handling 7012955Sgabeblack@google.com bool from64; // True if the exception is generated from the AArch64 state 7112988Sgabeblack@google.com bool to64; // True if the exception is taken in AArch64 state 7212955Sgabeblack@google.com ExceptionLevel fromEL; // Source exception level 7312955Sgabeblack@google.com ExceptionLevel toEL; // Target exception level 7413179Sgabeblack@google.com OperatingMode fromMode; // Source operating mode 7513179Sgabeblack@google.com 7613179Sgabeblack@google.com Addr getVector(ThreadContext *tc); 7713179Sgabeblack@google.com Addr getVector64(ThreadContext *tc); 7813179Sgabeblack@google.com 7913179Sgabeblack@google.com public: 8013179Sgabeblack@google.com /// Generic fault source enums used to index into 8113179Sgabeblack@google.com /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 8213179Sgabeblack@google.com /// on the current register width state and the translation table format in 8313179Sgabeblack@google.com /// use 8412955Sgabeblack@google.com enum FaultSource 8512955Sgabeblack@google.com { 8612955Sgabeblack@google.com AlignmentFault = 0, 8712955Sgabeblack@google.com InstructionCacheMaintenance, // Short-desc. format only 8812955Sgabeblack@google.com SynchExtAbtOnTranslTableWalkLL, 8912955Sgabeblack@google.com SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 9012955Sgabeblack@google.com TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 9112955Sgabeblack@google.com AccessFlagLL = TranslationLL + 4, 9212955Sgabeblack@google.com DomainLL = AccessFlagLL + 4, 9312955Sgabeblack@google.com PermissionLL = DomainLL + 4, 9412955Sgabeblack@google.com DebugEvent = PermissionLL + 4, 9512988Sgabeblack@google.com SynchronousExternalAbort, 9612955Sgabeblack@google.com TLBConflictAbort, // Requires LPAE 9712988Sgabeblack@google.com SynchPtyErrOnMemoryAccess, 9812988Sgabeblack@google.com AsynchronousExternalAbort, 9912988Sgabeblack@google.com AsynchPtyErrOnMemoryAccess, 10012988Sgabeblack@google.com AddressSizeLL, // AArch64 only 10112955Sgabeblack@google.com 10212955Sgabeblack@google.com // Not real faults. These are faults to allow the translation function 10312955Sgabeblack@google.com // to inform the memory access function not to proceed for a prefetch 10412955Sgabeblack@google.com // that misses in the TLB or that targets an uncacheable address 10512955Sgabeblack@google.com PrefetchTLBMiss = AddressSizeLL + 4, 10612955Sgabeblack@google.com PrefetchUncacheable, 10712957Sgabeblack@google.com 10813063Sgabeblack@google.com NumFaultSources, 10913063Sgabeblack@google.com FaultSourceInvalid = 0xff 11012955Sgabeblack@google.com }; 11112955Sgabeblack@google.com 11212955Sgabeblack@google.com /// Encodings of the fault sources when the short-desc. translation table 11312955Sgabeblack@google.com /// format is in use (ARM ARM Issue C B3.13.3) 11412955Sgabeblack@google.com static uint8_t shortDescFaultSources[NumFaultSources]; 11512955Sgabeblack@google.com /// Encodings of the fault sources when the long-desc. translation table 11612955Sgabeblack@google.com /// format is in use (ARM ARM Issue C B3.13.3) 11712955Sgabeblack@google.com static uint8_t longDescFaultSources[NumFaultSources]; 11812955Sgabeblack@google.com /// Encodings of the fault sources in AArch64 state 11912955Sgabeblack@google.com static uint8_t aarch64FaultSources[NumFaultSources]; 12012955Sgabeblack@google.com 12112955Sgabeblack@google.com enum AnnotationIDs 12212955Sgabeblack@google.com { 12312955Sgabeblack@google.com S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 12412955Sgabeblack@google.com OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 12512955Sgabeblack@google.com SAS, // DataAbort: Syndrome Access Size 12612955Sgabeblack@google.com SSE, // DataAbort: Syndrome Sign Extend 12712955Sgabeblack@google.com SRT, // DataAbort: Syndrome Register Transfer 12812955Sgabeblack@google.com 12912955Sgabeblack@google.com // AArch64 only 13012955Sgabeblack@google.com SF, // DataAbort: width of the accessed register is SixtyFour 13112955Sgabeblack@google.com AR // DataAbort: Acquire/Release semantics 13212955Sgabeblack@google.com }; 13312955Sgabeblack@google.com 13412955Sgabeblack@google.com enum TranMethod 13512955Sgabeblack@google.com { 13612955Sgabeblack@google.com LpaeTran, 13712955Sgabeblack@google.com VmsaTran, 13812955Sgabeblack@google.com UnknownTran 13913073Sgabeblack@google.com }; 14013073Sgabeblack@google.com 14113073Sgabeblack@google.com struct FaultVals 14213073Sgabeblack@google.com { 14312957Sgabeblack@google.com const FaultName name; 14412957Sgabeblack@google.com 14512957Sgabeblack@google.com const FaultOffset offset; 14612955Sgabeblack@google.com 14712955Sgabeblack@google.com // Offsets used for exceptions taken in AArch64 state 14812955Sgabeblack@google.com const uint16_t currELTOffset; 14912955Sgabeblack@google.com const uint16_t currELHOffset; 15012955Sgabeblack@google.com const uint16_t lowerEL64Offset; 15113063Sgabeblack@google.com const uint16_t lowerEL32Offset; 15213063Sgabeblack@google.com 15312957Sgabeblack@google.com const OperatingMode nextMode; 15412957Sgabeblack@google.com 15513063Sgabeblack@google.com const uint8_t armPcOffset; 15612957Sgabeblack@google.com const uint8_t thumbPcOffset; 15713063Sgabeblack@google.com // The following two values are used in place of armPcOffset and 15812955Sgabeblack@google.com // thumbPcOffset when the exception return address is saved into ELR 15912955Sgabeblack@google.com // registers (exceptions taken in HYP mode or in AArch64 state) 16012955Sgabeblack@google.com const uint8_t armPcElrOffset; 16112955Sgabeblack@google.com const uint8_t thumbPcElrOffset; 16212955Sgabeblack@google.com 16313063Sgabeblack@google.com const bool hypTrappable; 16413063Sgabeblack@google.com const bool abortDisable; 16512955Sgabeblack@google.com const bool fiqDisable; 16612955Sgabeblack@google.com 16712955Sgabeblack@google.com // Exception class used to appropriately set the syndrome register 16812955Sgabeblack@google.com // (exceptions taken in HYP mode or in AArch64 state) 16912955Sgabeblack@google.com const ExceptionClass ec; 17012955Sgabeblack@google.com 17112955Sgabeblack@google.com FaultStat count; 17212955Sgabeblack@google.com }; 17312955Sgabeblack@google.com 17412955Sgabeblack@google.com ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 17512955Sgabeblack@google.com machInst(_machInst), issRaw(_iss), from64(false), to64(false) {} 17612955Sgabeblack@google.com 17712955Sgabeblack@google.com // Returns the actual syndrome register to use based on the target 17812955Sgabeblack@google.com // exception level 17912955Sgabeblack@google.com MiscRegIndex getSyndromeReg64() const; 18012955Sgabeblack@google.com // Returns the actual fault address register to use based on the target 18112955Sgabeblack@google.com // exception level 18212955Sgabeblack@google.com MiscRegIndex getFaultAddrReg64() const; 18312955Sgabeblack@google.com 18412955Sgabeblack@google.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 18512955Sgabeblack@google.com StaticInst::nullStaticInstPtr); 18612955Sgabeblack@google.com void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 18712955Sgabeblack@google.com StaticInst::nullStaticInstPtr); 188 virtual void annotate(AnnotationIDs id, uint64_t val) {} 189 virtual FaultStat& countStat() = 0; 190 virtual FaultOffset offset(ThreadContext *tc) = 0; 191 virtual FaultOffset offset64() = 0; 192 virtual OperatingMode nextMode() = 0; 193 virtual bool routeToMonitor(ThreadContext *tc) const = 0; 194 virtual bool routeToHyp(ThreadContext *tc) const { return false; } 195 virtual uint8_t armPcOffset(bool isHyp) = 0; 196 virtual uint8_t thumbPcOffset(bool isHyp) = 0; 197 virtual uint8_t armPcElrOffset() = 0; 198 virtual uint8_t thumbPcElrOffset() = 0; 199 virtual bool abortDisable(ThreadContext *tc) = 0; 200 virtual bool fiqDisable(ThreadContext *tc) = 0; 201 virtual ExceptionClass ec(ThreadContext *tc) const = 0; 202 virtual uint32_t iss() const = 0; 203 virtual bool isStage2() const { return false; } 204 virtual FSR getFsr(ThreadContext *tc) { return 0; } 205 virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 206}; 207 208template<typename T> 209class ArmFaultVals : public ArmFault 210{ 211 protected: 212 static FaultVals vals; 213 214 public: 215 ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 216 ArmFault(_machInst, _iss) {} 217 FaultName name() const { return vals.name; } 218 FaultStat & countStat() { return vals.count; } 219 FaultOffset offset(ThreadContext *tc); 220 221 FaultOffset 222 offset64() 223 { 224 if (toEL == fromEL) { 225 if (opModeIsT(fromMode)) 226 return vals.currELTOffset; 227 return vals.currELHOffset; 228 } else { 229 if (from64) 230 return vals.lowerEL64Offset; 231 return vals.lowerEL32Offset; 232 } 233 } 234 235 OperatingMode nextMode() { return vals.nextMode; } 236 virtual bool routeToMonitor(ThreadContext *tc) const { return false; } 237 uint8_t armPcOffset(bool isHyp) { return isHyp ? vals.armPcElrOffset 238 : vals.armPcOffset; } 239 uint8_t thumbPcOffset(bool isHyp) { return isHyp ? vals.thumbPcElrOffset 240 : vals.thumbPcOffset; } 241 uint8_t armPcElrOffset() { return vals.armPcElrOffset; } 242 uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; } 243 virtual bool abortDisable(ThreadContext* tc) { return vals.abortDisable; } 244 virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; } 245 virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; } 246 virtual uint32_t iss() const { return issRaw; } 247}; 248 249class Reset : public ArmFaultVals<Reset> 250{ 251 public: 252 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 253 StaticInst::nullStaticInstPtr); 254}; 255 256class UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 257{ 258 protected: 259 bool unknown; 260 bool disabled; 261 ExceptionClass overrideEc; 262 const char *mnemonic; 263 264 public: 265 UndefinedInstruction(ExtMachInst _machInst, 266 bool _unknown, 267 const char *_mnemonic = NULL, 268 bool _disabled = false) : 269 ArmFaultVals<UndefinedInstruction>(_machInst), 270 unknown(_unknown), disabled(_disabled), 271 overrideEc(EC_INVALID), mnemonic(_mnemonic) 272 {} 273 UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 274 ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 275 ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 276 unknown(false), disabled(true), overrideEc(_overrideEc), 277 mnemonic(_mnemonic) 278 {} 279 280 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 281 StaticInst::nullStaticInstPtr); 282 bool routeToHyp(ThreadContext *tc) const; 283 ExceptionClass ec(ThreadContext *tc) const; 284 uint32_t iss() const; 285}; 286 287class SupervisorCall : public ArmFaultVals<SupervisorCall> 288{ 289 protected: 290 ExceptionClass overrideEc; 291 public: 292 SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 293 ExceptionClass _overrideEc = EC_INVALID) : 294 ArmFaultVals<SupervisorCall>(_machInst, _iss), 295 overrideEc(_overrideEc) 296 {} 297 298 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 299 StaticInst::nullStaticInstPtr); 300 bool routeToHyp(ThreadContext *tc) const; 301 ExceptionClass ec(ThreadContext *tc) const; 302 uint32_t iss() const; 303}; 304 305class SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 306{ 307 public: 308 SecureMonitorCall(ExtMachInst _machInst) : 309 ArmFaultVals<SecureMonitorCall>(_machInst) 310 {} 311 312 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 313 StaticInst::nullStaticInstPtr); 314 ExceptionClass ec(ThreadContext *tc) const; 315 uint32_t iss() const; 316}; 317 318class SupervisorTrap : public ArmFaultVals<SupervisorTrap> 319{ 320 protected: 321 ExtMachInst machInst; 322 ExceptionClass overrideEc; 323 324 public: 325 SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 326 ExceptionClass _overrideEc = EC_INVALID) : 327 ArmFaultVals<SupervisorTrap>(_machInst, _iss), 328 overrideEc(_overrideEc) 329 {} 330 331 ExceptionClass ec(ThreadContext *tc) const; 332}; 333 334class SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 335{ 336 protected: 337 ExtMachInst machInst; 338 ExceptionClass overrideEc; 339 340 public: 341 SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 342 ExceptionClass _overrideEc = EC_INVALID) : 343 ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 344 overrideEc(_overrideEc) 345 {} 346 347 ExceptionClass ec(ThreadContext *tc) const; 348}; 349 350class HypervisorCall : public ArmFaultVals<HypervisorCall> 351{ 352 public: 353 HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 354}; 355 356class HypervisorTrap : public ArmFaultVals<HypervisorTrap> 357{ 358 protected: 359 ExtMachInst machInst; 360 ExceptionClass overrideEc; 361 362 public: 363 HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 364 ExceptionClass _overrideEc = EC_INVALID) : 365 ArmFaultVals<HypervisorTrap>(_machInst, _iss), 366 overrideEc(_overrideEc) 367 {} 368 369 ExceptionClass ec(ThreadContext *tc) const; 370}; 371 372template <class T> 373class AbortFault : public ArmFaultVals<T> 374{ 375 protected: 376 /** 377 * The virtual address the fault occured at. If 2 stages of 378 * translation are being used then this is the intermediate 379 * physical address that is the starting point for the second 380 * stage of translation. 381 */ 382 Addr faultAddr; 383 /** 384 * Original virtual address. If the fault was generated on the 385 * second stage of translation then this variable stores the 386 * virtual address used in the original stage 1 translation. 387 */ 388 Addr OVAddr; 389 bool write; 390 TlbEntry::DomainType domain; 391 uint8_t source; 392 uint8_t srcEncoded; 393 bool stage2; 394 bool s1ptw; 395 ArmFault::TranMethod tranMethod; 396 397 public: 398 AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, 399 bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 400 faultAddr(_faultAddr), write(_write), domain(_domain), source(_source), 401 stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 402 {} 403 404 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 405 StaticInst::nullStaticInstPtr); 406 407 FSR getFsr(ThreadContext *tc); 408 bool abortDisable(ThreadContext *tc); 409 uint32_t iss() const; 410 bool isStage2() const { return stage2; } 411 void annotate(ArmFault::AnnotationIDs id, uint64_t val); 412 bool isMMUFault() const; 413}; 414 415class PrefetchAbort : public AbortFault<PrefetchAbort> 416{ 417 public: 418 static const MiscRegIndex FsrIndex = MISCREG_IFSR; 419 static const MiscRegIndex FarIndex = MISCREG_IFAR; 420 static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 421 422 PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 423 ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 424 AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 425 _source, _stage2, _tranMethod) 426 {} 427 428 ExceptionClass ec(ThreadContext *tc) const; 429 // @todo: external aborts should be routed if SCR.EA == 1 430 bool routeToMonitor(ThreadContext *tc) const; 431 bool routeToHyp(ThreadContext *tc) const; 432}; 433 434class DataAbort : public AbortFault<DataAbort> 435{ 436 public: 437 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 438 static const MiscRegIndex FarIndex = MISCREG_DFAR; 439 static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 440 bool isv; 441 uint8_t sas; 442 uint8_t sse; 443 uint8_t srt; 444 445 // AArch64 only 446 bool sf; 447 bool ar; 448 449 DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 450 bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 451 AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 452 _tranMethod), 453 isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 454 {} 455 456 ExceptionClass ec(ThreadContext *tc) const; 457 // @todo: external aborts should be routed if SCR.EA == 1 458 bool routeToMonitor(ThreadContext *tc) const; 459 bool routeToHyp(ThreadContext *tc) const; 460 uint32_t iss() const; 461 void annotate(AnnotationIDs id, uint64_t val); 462}; 463 464class VirtualDataAbort : public AbortFault<VirtualDataAbort> 465{ 466 public: 467 static const MiscRegIndex FsrIndex = MISCREG_DFSR; 468 static const MiscRegIndex FarIndex = MISCREG_DFAR; 469 static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 470 471 VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 472 uint8_t _source) : 473 AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 474 {} 475 476 void invoke(ThreadContext *tc, const StaticInstPtr &inst); 477}; 478 479class Interrupt : public ArmFaultVals<Interrupt> 480{ 481 public: 482 bool routeToMonitor(ThreadContext *tc) const; 483 bool routeToHyp(ThreadContext *tc) const; 484 bool abortDisable(ThreadContext *tc); 485}; 486 487class VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 488{ 489 public: 490 VirtualInterrupt(); 491}; 492 493class FastInterrupt : public ArmFaultVals<FastInterrupt> 494{ 495 public: 496 bool routeToMonitor(ThreadContext *tc) const; 497 bool routeToHyp(ThreadContext *tc) const; 498 bool abortDisable(ThreadContext *tc); 499 bool fiqDisable(ThreadContext *tc); 500}; 501 502class VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 503{ 504 public: 505 VirtualFastInterrupt(); 506}; 507 508/// PC alignment fault (AArch64 only) 509class PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 510{ 511 protected: 512 /// The unaligned value of the PC 513 Addr faultPC; 514 public: 515 PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 516 {} 517 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 518 StaticInst::nullStaticInstPtr); 519}; 520 521/// Stack pointer alignment fault (AArch64 only) 522class SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 523{ 524 public: 525 SPAlignmentFault(); 526}; 527 528/// System error (AArch64 only) 529class SystemError : public ArmFaultVals<SystemError> 530{ 531 public: 532 SystemError(); 533 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 534 StaticInst::nullStaticInstPtr); 535 bool routeToMonitor(ThreadContext *tc) const; 536 bool routeToHyp(ThreadContext *tc) const; 537}; 538 539// A fault that flushes the pipe, excluding the faulting instructions 540class FlushPipe : public ArmFaultVals<FlushPipe> 541{ 542 public: 543 FlushPipe() {} 544 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 545 StaticInst::nullStaticInstPtr); 546}; 547 548// A fault that flushes the pipe, excluding the faulting instructions 549class ArmSev : public ArmFaultVals<ArmSev> 550{ 551 public: 552 ArmSev () {} 553 void invoke(ThreadContext *tc, const StaticInstPtr &inst = 554 StaticInst::nullStaticInstPtr); 555}; 556 557/// Illegal Instruction Set State fault (AArch64 only) 558class IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 559{ 560 public: 561 IllegalInstSetStateFault(); 562}; 563 564} // namespace ArmISA 565 566#endif // __ARM_FAULTS_HH__ 567