faults.hh revision 8202
16019Shines@cs.fsu.edu/* 27189Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 436019Shines@cs.fsu.edu */ 446019Shines@cs.fsu.edu 456019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 466019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 476019Shines@cs.fsu.edu 487362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 496735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 506735Sgblack@eecs.umich.edu#include "config/full_system.hh" 516019Shines@cs.fsu.edu#include "sim/faults.hh" 527596Sminkyu.jeong@arm.com#include "base/misc.hh" 536019Shines@cs.fsu.edu 546019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 556019Shines@cs.fsu.edu 566019Shines@cs.fsu.edunamespace ArmISA 576019Shines@cs.fsu.edu{ 586735Sgblack@eecs.umich.edutypedef const Addr FaultOffset; 596019Shines@cs.fsu.edu 607362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 616019Shines@cs.fsu.edu{ 626019Shines@cs.fsu.edu protected: 636735Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 646735Sgblack@eecs.umich.edu 656019Shines@cs.fsu.edu public: 667362Sgblack@eecs.umich.edu enum StatusEncoding 677362Sgblack@eecs.umich.edu { 687362Sgblack@eecs.umich.edu // Fault Status register encodings 697362Sgblack@eecs.umich.edu // ARM ARM B3.9.4 707362Sgblack@eecs.umich.edu AlignmentFault = 0x1, 717362Sgblack@eecs.umich.edu DebugEvent = 0x2, 727362Sgblack@eecs.umich.edu AccessFlag0 = 0x3, 737362Sgblack@eecs.umich.edu InstructionCacheMaintenance = 0x4, 747362Sgblack@eecs.umich.edu Translation0 = 0x5, 757362Sgblack@eecs.umich.edu AccessFlag1 = 0x6, 767362Sgblack@eecs.umich.edu Translation1 = 0x7, 777362Sgblack@eecs.umich.edu SynchronousExternalAbort0 = 0x8, 787362Sgblack@eecs.umich.edu Domain0 = 0x9, 797595SGene.Wu@arm.com SynchronousExternalAbort1 = 0x8, 807362Sgblack@eecs.umich.edu Domain1 = 0xb, 817404SAli.Saidi@ARM.com TranslationTableWalkExtAbt0 = 0xc, 827362Sgblack@eecs.umich.edu Permission0 = 0xd, 837404SAli.Saidi@ARM.com TranslationTableWalkExtAbt1 = 0xe, 847362Sgblack@eecs.umich.edu Permission1 = 0xf, 857362Sgblack@eecs.umich.edu AsynchronousExternalAbort = 0x16, 867362Sgblack@eecs.umich.edu MemoryAccessAsynchronousParityError = 0x18, 877362Sgblack@eecs.umich.edu MemoryAccessSynchronousParityError = 0x19, 887404SAli.Saidi@ARM.com TranslationTableWalkPrtyErr0 = 0x1c, 897404SAli.Saidi@ARM.com TranslationTableWalkPrtyErr1 = 0x1e, 907611SGene.Wu@arm.com 917611SGene.Wu@arm.com // not a real fault. This is a status code 927611SGene.Wu@arm.com // to allow the translation function to inform 937611SGene.Wu@arm.com // the memory access function not to proceed 947611SGene.Wu@arm.com // for a Prefetch that misses in the TLB. 957850SMatt.Horsnell@arm.com PrefetchTLBMiss = 0x1f, 967850SMatt.Horsnell@arm.com PrefetchUncacheable = 0x20 977362Sgblack@eecs.umich.edu }; 987362Sgblack@eecs.umich.edu 996735Sgblack@eecs.umich.edu struct FaultVals 1006735Sgblack@eecs.umich.edu { 1016735Sgblack@eecs.umich.edu const FaultName name; 1026735Sgblack@eecs.umich.edu const FaultOffset offset; 1036735Sgblack@eecs.umich.edu const OperatingMode nextMode; 1046735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1056735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 1066735Sgblack@eecs.umich.edu const bool abortDisable; 1076735Sgblack@eecs.umich.edu const bool fiqDisable; 1086735Sgblack@eecs.umich.edu FaultStat count; 1096735Sgblack@eecs.umich.edu }; 1106735Sgblack@eecs.umich.edu 1116019Shines@cs.fsu.edu#if FULL_SYSTEM 1127678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 1137678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1146019Shines@cs.fsu.edu#endif 1156735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 1166735Sgblack@eecs.umich.edu virtual FaultOffset offset() = 0; 1176735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 1186735Sgblack@eecs.umich.edu virtual uint8_t armPcOffset() = 0; 1196735Sgblack@eecs.umich.edu virtual uint8_t thumbPcOffset() = 0; 1206735Sgblack@eecs.umich.edu virtual bool abortDisable() = 0; 1216735Sgblack@eecs.umich.edu virtual bool fiqDisable() = 0; 1226019Shines@cs.fsu.edu}; 1236019Shines@cs.fsu.edu 1246735Sgblack@eecs.umich.edutemplate<typename T> 1257362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 1266019Shines@cs.fsu.edu{ 1276735Sgblack@eecs.umich.edu protected: 1286735Sgblack@eecs.umich.edu static FaultVals vals; 1296735Sgblack@eecs.umich.edu 1306019Shines@cs.fsu.edu public: 1316735Sgblack@eecs.umich.edu FaultName name() const { return vals.name; } 1326735Sgblack@eecs.umich.edu FaultStat & countStat() {return vals.count;} 1336735Sgblack@eecs.umich.edu FaultOffset offset() { return vals.offset; } 1346735Sgblack@eecs.umich.edu OperatingMode nextMode() { return vals.nextMode; } 1356735Sgblack@eecs.umich.edu uint8_t armPcOffset() { return vals.armPcOffset; } 1366735Sgblack@eecs.umich.edu uint8_t thumbPcOffset() { return vals.thumbPcOffset; } 1376735Sgblack@eecs.umich.edu bool abortDisable() { return vals.abortDisable; } 1386735Sgblack@eecs.umich.edu bool fiqDisable() { return vals.fiqDisable; } 1396019Shines@cs.fsu.edu}; 1406019Shines@cs.fsu.edu 1417400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 1427400SAli.Saidi@ARM.com#if FULL_SYSTEM 1437400SAli.Saidi@ARM.com{ 1447400SAli.Saidi@ARM.com public: 1457678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 1467678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1477400SAli.Saidi@ARM.com}; 1487400SAli.Saidi@ARM.com#else 1497400SAli.Saidi@ARM.com{}; 1507400SAli.Saidi@ARM.com#endif //FULL_SYSTEM 1517189Sgblack@eecs.umich.edu 1527362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 1537189Sgblack@eecs.umich.edu{ 1547189Sgblack@eecs.umich.edu#if !FULL_SYSTEM 1557189Sgblack@eecs.umich.edu protected: 1567189Sgblack@eecs.umich.edu ExtMachInst machInst; 1577189Sgblack@eecs.umich.edu bool unknown; 1587189Sgblack@eecs.umich.edu const char *mnemonic; 1597640Sgblack@eecs.umich.edu bool disabled; 1607189Sgblack@eecs.umich.edu 1617189Sgblack@eecs.umich.edu public: 1627189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 1637189Sgblack@eecs.umich.edu bool _unknown, 1647640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 1657640Sgblack@eecs.umich.edu bool _disabled = false) : 1667640Sgblack@eecs.umich.edu machInst(_machInst), unknown(_unknown), 1677640Sgblack@eecs.umich.edu mnemonic(_mnemonic), disabled(_disabled) 1687189Sgblack@eecs.umich.edu { 1697189Sgblack@eecs.umich.edu } 1707189Sgblack@eecs.umich.edu 1717678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 1727678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1737189Sgblack@eecs.umich.edu#endif 1747189Sgblack@eecs.umich.edu}; 1757189Sgblack@eecs.umich.edu 1767362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 1777197Sgblack@eecs.umich.edu{ 1787197Sgblack@eecs.umich.edu#if !FULL_SYSTEM 1797197Sgblack@eecs.umich.edu protected: 1807197Sgblack@eecs.umich.edu ExtMachInst machInst; 1817197Sgblack@eecs.umich.edu 1827197Sgblack@eecs.umich.edu public: 1837197Sgblack@eecs.umich.edu SupervisorCall(ExtMachInst _machInst) : machInst(_machInst) 1847197Sgblack@eecs.umich.edu {} 1857197Sgblack@eecs.umich.edu 1867678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 1877678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 1887197Sgblack@eecs.umich.edu#endif 1897197Sgblack@eecs.umich.edu}; 1907362Sgblack@eecs.umich.edu 1917362Sgblack@eecs.umich.edutemplate <class T> 1927362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 1937362Sgblack@eecs.umich.edu{ 1947362Sgblack@eecs.umich.edu protected: 1957362Sgblack@eecs.umich.edu Addr faultAddr; 1967362Sgblack@eecs.umich.edu bool write; 1977362Sgblack@eecs.umich.edu uint8_t domain; 1987362Sgblack@eecs.umich.edu uint8_t status; 1997362Sgblack@eecs.umich.edu 2007362Sgblack@eecs.umich.edu public: 2017362Sgblack@eecs.umich.edu AbortFault(Addr _faultAddr, bool _write, 2027362Sgblack@eecs.umich.edu uint8_t _domain, uint8_t _status) : 2037362Sgblack@eecs.umich.edu faultAddr(_faultAddr), write(_write), 2047362Sgblack@eecs.umich.edu domain(_domain), status(_status) 2057362Sgblack@eecs.umich.edu {} 2067362Sgblack@eecs.umich.edu 2077678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 2087678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 2097362Sgblack@eecs.umich.edu}; 2107362Sgblack@eecs.umich.edu 2117362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 2127362Sgblack@eecs.umich.edu{ 2137362Sgblack@eecs.umich.edu public: 2147362Sgblack@eecs.umich.edu static const MiscRegIndex FsrIndex = MISCREG_IFSR; 2157362Sgblack@eecs.umich.edu static const MiscRegIndex FarIndex = MISCREG_IFAR; 2167362Sgblack@eecs.umich.edu 2177362Sgblack@eecs.umich.edu PrefetchAbort(Addr _addr, uint8_t _status) : 2187362Sgblack@eecs.umich.edu AbortFault<PrefetchAbort>(_addr, false, 0, _status) 2197362Sgblack@eecs.umich.edu {} 2207362Sgblack@eecs.umich.edu}; 2217362Sgblack@eecs.umich.edu 2227362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 2237362Sgblack@eecs.umich.edu{ 2247362Sgblack@eecs.umich.edu public: 2257362Sgblack@eecs.umich.edu static const MiscRegIndex FsrIndex = MISCREG_DFSR; 2267362Sgblack@eecs.umich.edu static const MiscRegIndex FarIndex = MISCREG_DFAR; 2277362Sgblack@eecs.umich.edu 2287404SAli.Saidi@ARM.com DataAbort(Addr _addr, uint8_t _domain, bool _write, uint8_t _status) : 2297362Sgblack@eecs.umich.edu AbortFault<DataAbort>(_addr, _write, _domain, _status) 2307362Sgblack@eecs.umich.edu {} 2317362Sgblack@eecs.umich.edu}; 2327362Sgblack@eecs.umich.edu 2337362Sgblack@eecs.umich.educlass Interrupt : public ArmFaultVals<Interrupt> {}; 2347362Sgblack@eecs.umich.educlass FastInterrupt : public ArmFaultVals<FastInterrupt> {}; 2356019Shines@cs.fsu.edu 2367652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 2377652Sminkyu.jeong@arm.comclass FlushPipe : public ArmFaultVals<FlushPipe> 2387652Sminkyu.jeong@arm.com{ 2397652Sminkyu.jeong@arm.com public: 2407652Sminkyu.jeong@arm.com FlushPipe() {} 2417678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 2427678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 2437652Sminkyu.jeong@arm.com}; 2447652Sminkyu.jeong@arm.com 2458202SAli.Saidi@ARM.com// A fault that flushes the pipe, including the faulting instructions 2468202SAli.Saidi@ARM.comclass ReExec : public ArmFaultVals<ReExec> 2478202SAli.Saidi@ARM.com{ 2488202SAli.Saidi@ARM.com public: 2498202SAli.Saidi@ARM.com ReExec() {} 2508202SAli.Saidi@ARM.com void invoke(ThreadContext *tc, 2518202SAli.Saidi@ARM.com StaticInstPtr inst = StaticInst::nullStaticInstPtr); 2528202SAli.Saidi@ARM.com}; 2538202SAli.Saidi@ARM.com 2548202SAli.Saidi@ARM.com 2557596Sminkyu.jeong@arm.comstatic inline Fault genMachineCheckFault() 2567596Sminkyu.jeong@arm.com{ 2577596Sminkyu.jeong@arm.com return new Reset(); 2587596Sminkyu.jeong@arm.com} 2596019Shines@cs.fsu.edu 2607811Ssteve.reinhardt@amd.com} // namespace ArmISA 2616019Shines@cs.fsu.edu 2626019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 263