faults.hh revision 12517
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2013, 2016-2018 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 496019Shines@cs.fsu.edu 507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5110037SARM gem5 Developers#include "arch/arm/pagetable.hh" 526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 5312334Sgabeblack@google.com#include "base/logging.hh" 546019Shines@cs.fsu.edu#include "sim/faults.hh" 558782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 6111294Sandreas.hansson@arm.comtypedef Addr FaultOffset; 626019Shines@cs.fsu.edu 637362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 646019Shines@cs.fsu.edu{ 656019Shines@cs.fsu.edu protected: 6610037SARM gem5 Developers ExtMachInst machInst; 6710037SARM gem5 Developers uint32_t issRaw; 6810037SARM gem5 Developers 6910037SARM gem5 Developers // Helper variables for ARMv8 exception handling 7010037SARM gem5 Developers bool from64; // True if the exception is generated from the AArch64 state 7110037SARM gem5 Developers bool to64; // True if the exception is taken in AArch64 state 7210037SARM gem5 Developers ExceptionLevel fromEL; // Source exception level 7310037SARM gem5 Developers ExceptionLevel toEL; // Target exception level 7410037SARM gem5 Developers OperatingMode fromMode; // Source operating mode 7510037SARM gem5 Developers 7612402Sgiacomo.travaglini@arm.com bool hypRouted; // True if the fault has been routed to Hypervisor 7712402Sgiacomo.travaglini@arm.com 786735Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 7910037SARM gem5 Developers Addr getVector64(ThreadContext *tc); 806735Sgblack@eecs.umich.edu 816019Shines@cs.fsu.edu public: 8210037SARM gem5 Developers /// Generic fault source enums used to index into 8310037SARM gem5 Developers /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 8410037SARM gem5 Developers /// on the current register width state and the translation table format in 8510037SARM gem5 Developers /// use 8610037SARM gem5 Developers enum FaultSource 877362Sgblack@eecs.umich.edu { 8810037SARM gem5 Developers AlignmentFault = 0, 8910037SARM gem5 Developers InstructionCacheMaintenance, // Short-desc. format only 9010037SARM gem5 Developers SynchExtAbtOnTranslTableWalkLL, 9110037SARM gem5 Developers SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 9210037SARM gem5 Developers TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 9310037SARM gem5 Developers AccessFlagLL = TranslationLL + 4, 9410037SARM gem5 Developers DomainLL = AccessFlagLL + 4, 9510037SARM gem5 Developers PermissionLL = DomainLL + 4, 9610037SARM gem5 Developers DebugEvent = PermissionLL + 4, 9710037SARM gem5 Developers SynchronousExternalAbort, 9810037SARM gem5 Developers TLBConflictAbort, // Requires LPAE 9910037SARM gem5 Developers SynchPtyErrOnMemoryAccess, 10010037SARM gem5 Developers AsynchronousExternalAbort, 10110037SARM gem5 Developers AsynchPtyErrOnMemoryAccess, 10210037SARM gem5 Developers AddressSizeLL, // AArch64 only 1037611SGene.Wu@arm.com 10410037SARM gem5 Developers // Not real faults. These are faults to allow the translation function 10510037SARM gem5 Developers // to inform the memory access function not to proceed for a prefetch 10610037SARM gem5 Developers // that misses in the TLB or that targets an uncacheable address 10710037SARM gem5 Developers PrefetchTLBMiss = AddressSizeLL + 4, 10810037SARM gem5 Developers PrefetchUncacheable, 10910037SARM gem5 Developers 11010037SARM gem5 Developers NumFaultSources, 11110037SARM gem5 Developers FaultSourceInvalid = 0xff 11210037SARM gem5 Developers }; 11310037SARM gem5 Developers 11410037SARM gem5 Developers /// Encodings of the fault sources when the short-desc. translation table 11510037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11610037SARM gem5 Developers static uint8_t shortDescFaultSources[NumFaultSources]; 11710037SARM gem5 Developers /// Encodings of the fault sources when the long-desc. translation table 11810037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11910037SARM gem5 Developers static uint8_t longDescFaultSources[NumFaultSources]; 12010037SARM gem5 Developers /// Encodings of the fault sources in AArch64 state 12110037SARM gem5 Developers static uint8_t aarch64FaultSources[NumFaultSources]; 12210037SARM gem5 Developers 12310037SARM gem5 Developers enum AnnotationIDs 12410037SARM gem5 Developers { 12510037SARM gem5 Developers S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 12610037SARM gem5 Developers OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 12710037SARM gem5 Developers SAS, // DataAbort: Syndrome Access Size 12810037SARM gem5 Developers SSE, // DataAbort: Syndrome Sign Extend 12910037SARM gem5 Developers SRT, // DataAbort: Syndrome Register Transfer 13010037SARM gem5 Developers 13110037SARM gem5 Developers // AArch64 only 13210037SARM gem5 Developers SF, // DataAbort: width of the accessed register is SixtyFour 13310037SARM gem5 Developers AR // DataAbort: Acquire/Release semantics 13410037SARM gem5 Developers }; 13510037SARM gem5 Developers 13610037SARM gem5 Developers enum TranMethod 13710037SARM gem5 Developers { 13810037SARM gem5 Developers LpaeTran, 13910037SARM gem5 Developers VmsaTran, 14010037SARM gem5 Developers UnknownTran 1417362Sgblack@eecs.umich.edu }; 1427362Sgblack@eecs.umich.edu 1436735Sgblack@eecs.umich.edu struct FaultVals 1446735Sgblack@eecs.umich.edu { 1456735Sgblack@eecs.umich.edu const FaultName name; 14610037SARM gem5 Developers 1476735Sgblack@eecs.umich.edu const FaultOffset offset; 14810037SARM gem5 Developers 14910037SARM gem5 Developers // Offsets used for exceptions taken in AArch64 state 15010037SARM gem5 Developers const uint16_t currELTOffset; 15110037SARM gem5 Developers const uint16_t currELHOffset; 15210037SARM gem5 Developers const uint16_t lowerEL64Offset; 15310037SARM gem5 Developers const uint16_t lowerEL32Offset; 15410037SARM gem5 Developers 1556735Sgblack@eecs.umich.edu const OperatingMode nextMode; 15610037SARM gem5 Developers 1576735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1586735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 15910037SARM gem5 Developers // The following two values are used in place of armPcOffset and 16010037SARM gem5 Developers // thumbPcOffset when the exception return address is saved into ELR 16110037SARM gem5 Developers // registers (exceptions taken in HYP mode or in AArch64 state) 16210037SARM gem5 Developers const uint8_t armPcElrOffset; 16310037SARM gem5 Developers const uint8_t thumbPcElrOffset; 16410037SARM gem5 Developers 16510037SARM gem5 Developers const bool hypTrappable; 1666735Sgblack@eecs.umich.edu const bool abortDisable; 1676735Sgblack@eecs.umich.edu const bool fiqDisable; 16810037SARM gem5 Developers 16910037SARM gem5 Developers // Exception class used to appropriately set the syndrome register 17010037SARM gem5 Developers // (exceptions taken in HYP mode or in AArch64 state) 17110037SARM gem5 Developers const ExceptionClass ec; 17210037SARM gem5 Developers 1736735Sgblack@eecs.umich.edu FaultStat count; 17412517Srekai.gonzalezalberquilla@arm.com FaultVals(const FaultName& name_, const FaultOffset& offset_, 17512517Srekai.gonzalezalberquilla@arm.com const uint16_t& currELTOffset_, const uint16_t& currELHOffset_, 17612517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL64Offset_, 17712517Srekai.gonzalezalberquilla@arm.com const uint16_t& lowerEL32Offset_, 17812517Srekai.gonzalezalberquilla@arm.com const OperatingMode& nextMode_, const uint8_t& armPcOffset_, 17912517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcOffset_, const uint8_t& armPcElrOffset_, 18012517Srekai.gonzalezalberquilla@arm.com const uint8_t& thumbPcElrOffset_, const bool& hypTrappable_, 18112517Srekai.gonzalezalberquilla@arm.com const bool& abortDisable_, const bool& fiqDisable_, 18212517Srekai.gonzalezalberquilla@arm.com const ExceptionClass& ec_) 18312517Srekai.gonzalezalberquilla@arm.com : name(name_), offset(offset_), currELTOffset(currELTOffset_), 18412517Srekai.gonzalezalberquilla@arm.com currELHOffset(currELHOffset_), lowerEL64Offset(lowerEL64Offset_), 18512517Srekai.gonzalezalberquilla@arm.com lowerEL32Offset(lowerEL32Offset_), nextMode(nextMode_), 18612517Srekai.gonzalezalberquilla@arm.com armPcOffset(armPcOffset_), thumbPcOffset(thumbPcOffset_), 18712517Srekai.gonzalezalberquilla@arm.com armPcElrOffset(armPcElrOffset_), thumbPcElrOffset(thumbPcElrOffset_), 18812517Srekai.gonzalezalberquilla@arm.com hypTrappable(hypTrappable_), abortDisable(abortDisable_), 18912517Srekai.gonzalezalberquilla@arm.com fiqDisable(fiqDisable_), ec(ec_) {} 1906735Sgblack@eecs.umich.edu }; 1916735Sgblack@eecs.umich.edu 19210037SARM gem5 Developers ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 19310537Sandreas.hansson@arm.com machInst(_machInst), issRaw(_iss), from64(false), to64(false), 19412402Sgiacomo.travaglini@arm.com fromEL(EL0), toEL(EL0), fromMode(MODE_UNDEFINED), hypRouted(false) {} 19510037SARM gem5 Developers 19610037SARM gem5 Developers // Returns the actual syndrome register to use based on the target 19710037SARM gem5 Developers // exception level 19810037SARM gem5 Developers MiscRegIndex getSyndromeReg64() const; 19910037SARM gem5 Developers // Returns the actual fault address register to use based on the target 20010037SARM gem5 Developers // exception level 20110037SARM gem5 Developers MiscRegIndex getFaultAddrReg64() const; 20210037SARM gem5 Developers 20310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 20412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 20510417Sandreas.hansson@arm.com void invoke64(ThreadContext *tc, const StaticInstPtr &inst = 20610417Sandreas.hansson@arm.com StaticInst::nullStaticInstPtr); 20710037SARM gem5 Developers virtual void annotate(AnnotationIDs id, uint64_t val) {} 2086735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 20910037SARM gem5 Developers virtual FaultOffset offset(ThreadContext *tc) = 0; 21012511Schuan.zhu@arm.com virtual FaultOffset offset64(ThreadContext *tc) = 0; 2116735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 21210037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const = 0; 21310037SARM gem5 Developers virtual bool routeToHyp(ThreadContext *tc) const { return false; } 21410037SARM gem5 Developers virtual uint8_t armPcOffset(bool isHyp) = 0; 21510037SARM gem5 Developers virtual uint8_t thumbPcOffset(bool isHyp) = 0; 21610037SARM gem5 Developers virtual uint8_t armPcElrOffset() = 0; 21710037SARM gem5 Developers virtual uint8_t thumbPcElrOffset() = 0; 21810037SARM gem5 Developers virtual bool abortDisable(ThreadContext *tc) = 0; 21910037SARM gem5 Developers virtual bool fiqDisable(ThreadContext *tc) = 0; 22010037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const = 0; 22110037SARM gem5 Developers virtual uint32_t iss() const = 0; 22210037SARM gem5 Developers virtual bool isStage2() const { return false; } 22310037SARM gem5 Developers virtual FSR getFsr(ThreadContext *tc) { return 0; } 22410037SARM gem5 Developers virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2256019Shines@cs.fsu.edu}; 2266019Shines@cs.fsu.edu 2276735Sgblack@eecs.umich.edutemplate<typename T> 2287362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 2296019Shines@cs.fsu.edu{ 2306735Sgblack@eecs.umich.edu protected: 2316735Sgblack@eecs.umich.edu static FaultVals vals; 2326735Sgblack@eecs.umich.edu 2336019Shines@cs.fsu.edu public: 23410037SARM gem5 Developers ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 23510037SARM gem5 Developers ArmFault(_machInst, _iss) {} 23612176Sandreas.sandberg@arm.com FaultName name() const override { return vals.name; } 23712176Sandreas.sandberg@arm.com FaultStat & countStat() override { return vals.count; } 23812176Sandreas.sandberg@arm.com FaultOffset offset(ThreadContext *tc) override; 23910037SARM gem5 Developers 24012511Schuan.zhu@arm.com FaultOffset offset64(ThreadContext *tc) override; 24110037SARM gem5 Developers 24212176Sandreas.sandberg@arm.com OperatingMode nextMode() override { return vals.nextMode; } 24312176Sandreas.sandberg@arm.com virtual bool routeToMonitor(ThreadContext *tc) const override { 24412176Sandreas.sandberg@arm.com return false; 24512176Sandreas.sandberg@arm.com } 24612176Sandreas.sandberg@arm.com uint8_t armPcOffset(bool isHyp) override { 24712176Sandreas.sandberg@arm.com return isHyp ? vals.armPcElrOffset 24812176Sandreas.sandberg@arm.com : vals.armPcOffset; 24912176Sandreas.sandberg@arm.com } 25012176Sandreas.sandberg@arm.com uint8_t thumbPcOffset(bool isHyp) override { 25112176Sandreas.sandberg@arm.com return isHyp ? vals.thumbPcElrOffset 25212176Sandreas.sandberg@arm.com : vals.thumbPcOffset; 25312176Sandreas.sandberg@arm.com } 25412176Sandreas.sandberg@arm.com uint8_t armPcElrOffset() override { return vals.armPcElrOffset; } 25512176Sandreas.sandberg@arm.com uint8_t thumbPcElrOffset() override { return vals.thumbPcElrOffset; } 25612176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext* tc) override { return vals.abortDisable; } 25712176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext* tc) override { return vals.fiqDisable; } 25812176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override { return vals.ec; } 25912176Sandreas.sandberg@arm.com uint32_t iss() const override { return issRaw; } 2606019Shines@cs.fsu.edu}; 2616019Shines@cs.fsu.edu 2627400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 2637400SAli.Saidi@ARM.com{ 2647400SAli.Saidi@ARM.com public: 26510417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 26612176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 2677400SAli.Saidi@ARM.com}; 2687189Sgblack@eecs.umich.edu 2697362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2707189Sgblack@eecs.umich.edu{ 2717189Sgblack@eecs.umich.edu protected: 2727189Sgblack@eecs.umich.edu bool unknown; 2737640Sgblack@eecs.umich.edu bool disabled; 27410037SARM gem5 Developers ExceptionClass overrideEc; 27510205SAli.Saidi@ARM.com const char *mnemonic; 2767189Sgblack@eecs.umich.edu 2777189Sgblack@eecs.umich.edu public: 2787189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 2797189Sgblack@eecs.umich.edu bool _unknown, 2807640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 2817640Sgblack@eecs.umich.edu bool _disabled = false) : 28210037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst), 28310205SAli.Saidi@ARM.com unknown(_unknown), disabled(_disabled), 28410205SAli.Saidi@ARM.com overrideEc(EC_INVALID), mnemonic(_mnemonic) 28510037SARM gem5 Developers {} 28610205SAli.Saidi@ARM.com UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, 28710205SAli.Saidi@ARM.com ExceptionClass _overrideEc, const char *_mnemonic = NULL) : 28810037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 28910205SAli.Saidi@ARM.com unknown(false), disabled(true), overrideEc(_overrideEc), 29010205SAli.Saidi@ARM.com mnemonic(_mnemonic) 2918782Sgblack@eecs.umich.edu {} 2927189Sgblack@eecs.umich.edu 29310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 29412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 29512176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 29612176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 29712176Sandreas.sandberg@arm.com uint32_t iss() const override; 2987189Sgblack@eecs.umich.edu}; 2997189Sgblack@eecs.umich.edu 3007362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 3017197Sgblack@eecs.umich.edu{ 3027197Sgblack@eecs.umich.edu protected: 30310037SARM gem5 Developers ExceptionClass overrideEc; 3047197Sgblack@eecs.umich.edu public: 30510037SARM gem5 Developers SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 30610037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 30710037SARM gem5 Developers ArmFaultVals<SupervisorCall>(_machInst, _iss), 30810037SARM gem5 Developers overrideEc(_overrideEc) 3098782Sgblack@eecs.umich.edu {} 3107197Sgblack@eecs.umich.edu 31110417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 31212176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 31312176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 31412176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 31512176Sandreas.sandberg@arm.com uint32_t iss() const override; 31610037SARM gem5 Developers}; 31710037SARM gem5 Developers 31810037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 31910037SARM gem5 Developers{ 32010037SARM gem5 Developers public: 32110037SARM gem5 Developers SecureMonitorCall(ExtMachInst _machInst) : 32210037SARM gem5 Developers ArmFaultVals<SecureMonitorCall>(_machInst) 32310037SARM gem5 Developers {} 32410037SARM gem5 Developers 32510417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 32612176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 32712176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 32812176Sandreas.sandberg@arm.com uint32_t iss() const override; 32910037SARM gem5 Developers}; 33010037SARM gem5 Developers 33110037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 33210037SARM gem5 Developers{ 33310037SARM gem5 Developers protected: 33410037SARM gem5 Developers ExtMachInst machInst; 33510037SARM gem5 Developers ExceptionClass overrideEc; 33610037SARM gem5 Developers 33710037SARM gem5 Developers public: 33810037SARM gem5 Developers SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 33910037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 34010037SARM gem5 Developers ArmFaultVals<SupervisorTrap>(_machInst, _iss), 34110037SARM gem5 Developers overrideEc(_overrideEc) 34210037SARM gem5 Developers {} 34310037SARM gem5 Developers 34412509Schuan.zhu@arm.com bool routeToHyp(ThreadContext *tc) const override; 34512509Schuan.zhu@arm.com uint32_t iss() const override; 34612176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 34710037SARM gem5 Developers}; 34810037SARM gem5 Developers 34910037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 35010037SARM gem5 Developers{ 35110037SARM gem5 Developers protected: 35210037SARM gem5 Developers ExtMachInst machInst; 35310037SARM gem5 Developers ExceptionClass overrideEc; 35410037SARM gem5 Developers 35510037SARM gem5 Developers public: 35610037SARM gem5 Developers SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 35710037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 35810037SARM gem5 Developers ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 35910037SARM gem5 Developers overrideEc(_overrideEc) 36010037SARM gem5 Developers {} 36110037SARM gem5 Developers 36212176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 36310037SARM gem5 Developers}; 36410037SARM gem5 Developers 36510037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall> 36610037SARM gem5 Developers{ 36710037SARM gem5 Developers public: 36810037SARM gem5 Developers HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 36911576SDylan.Johnson@ARM.com 37012176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 37110037SARM gem5 Developers}; 37210037SARM gem5 Developers 37310037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 37410037SARM gem5 Developers{ 37510037SARM gem5 Developers protected: 37610037SARM gem5 Developers ExtMachInst machInst; 37710037SARM gem5 Developers ExceptionClass overrideEc; 37810037SARM gem5 Developers 37910037SARM gem5 Developers public: 38010037SARM gem5 Developers HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 38110037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 38210037SARM gem5 Developers ArmFaultVals<HypervisorTrap>(_machInst, _iss), 38310037SARM gem5 Developers overrideEc(_overrideEc) 38410037SARM gem5 Developers {} 38510037SARM gem5 Developers 38612176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 3877197Sgblack@eecs.umich.edu}; 3887362Sgblack@eecs.umich.edu 3897362Sgblack@eecs.umich.edutemplate <class T> 3907362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 3917362Sgblack@eecs.umich.edu{ 3927362Sgblack@eecs.umich.edu protected: 39310037SARM gem5 Developers /** 39410037SARM gem5 Developers * The virtual address the fault occured at. If 2 stages of 39510037SARM gem5 Developers * translation are being used then this is the intermediate 39610037SARM gem5 Developers * physical address that is the starting point for the second 39710037SARM gem5 Developers * stage of translation. 39810037SARM gem5 Developers */ 3997362Sgblack@eecs.umich.edu Addr faultAddr; 40010037SARM gem5 Developers /** 40110037SARM gem5 Developers * Original virtual address. If the fault was generated on the 40210037SARM gem5 Developers * second stage of translation then this variable stores the 40310037SARM gem5 Developers * virtual address used in the original stage 1 translation. 40410037SARM gem5 Developers */ 40510037SARM gem5 Developers Addr OVAddr; 4067362Sgblack@eecs.umich.edu bool write; 40710037SARM gem5 Developers TlbEntry::DomainType domain; 40810037SARM gem5 Developers uint8_t source; 40910037SARM gem5 Developers uint8_t srcEncoded; 41010037SARM gem5 Developers bool stage2; 41110037SARM gem5 Developers bool s1ptw; 41210037SARM gem5 Developers ArmFault::TranMethod tranMethod; 4137362Sgblack@eecs.umich.edu 4147362Sgblack@eecs.umich.edu public: 41510537Sandreas.hansson@arm.com AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, 41610537Sandreas.hansson@arm.com uint8_t _source, bool _stage2, 41710537Sandreas.hansson@arm.com ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 41810537Sandreas.hansson@arm.com faultAddr(_faultAddr), OVAddr(0), write(_write), 41910537Sandreas.hansson@arm.com domain(_domain), source(_source), srcEncoded(0), 42010037SARM gem5 Developers stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4217362Sgblack@eecs.umich.edu {} 4227362Sgblack@eecs.umich.edu 42310417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 42412176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 42510037SARM gem5 Developers 42612176Sandreas.sandberg@arm.com FSR getFsr(ThreadContext *tc) override; 42712176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 42812176Sandreas.sandberg@arm.com uint32_t iss() const override; 42912176Sandreas.sandberg@arm.com bool isStage2() const override { return stage2; } 43012176Sandreas.sandberg@arm.com void annotate(ArmFault::AnnotationIDs id, uint64_t val) override; 43110037SARM gem5 Developers bool isMMUFault() const; 4327362Sgblack@eecs.umich.edu}; 4337362Sgblack@eecs.umich.edu 4347362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 4357362Sgblack@eecs.umich.edu{ 4367362Sgblack@eecs.umich.edu public: 43710037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_IFSR; 43810037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_IFAR; 43910037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4407362Sgblack@eecs.umich.edu 44110037SARM gem5 Developers PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 44210037SARM gem5 Developers ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 44310037SARM gem5 Developers AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 44410037SARM gem5 Developers _source, _stage2, _tranMethod) 4457362Sgblack@eecs.umich.edu {} 44610037SARM gem5 Developers 44712176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 44810037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 44912176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 45012176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 4517362Sgblack@eecs.umich.edu}; 4527362Sgblack@eecs.umich.edu 4537362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 4547362Sgblack@eecs.umich.edu{ 4557362Sgblack@eecs.umich.edu public: 45610037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 45710037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 45810037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 45910037SARM gem5 Developers bool isv; 46010037SARM gem5 Developers uint8_t sas; 46110037SARM gem5 Developers uint8_t sse; 46210037SARM gem5 Developers uint8_t srt; 4637362Sgblack@eecs.umich.edu 46410037SARM gem5 Developers // AArch64 only 46510037SARM gem5 Developers bool sf; 46610037SARM gem5 Developers bool ar; 46710037SARM gem5 Developers 46810037SARM gem5 Developers DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 46910037SARM gem5 Developers bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 47010037SARM gem5 Developers AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 47110037SARM gem5 Developers _tranMethod), 47210037SARM gem5 Developers isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4737362Sgblack@eecs.umich.edu {} 47410037SARM gem5 Developers 47512176Sandreas.sandberg@arm.com ExceptionClass ec(ThreadContext *tc) const override; 47610037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 47712176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 47812176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 47912176Sandreas.sandberg@arm.com uint32_t iss() const override; 48012176Sandreas.sandberg@arm.com void annotate(AnnotationIDs id, uint64_t val) override; 4817362Sgblack@eecs.umich.edu}; 4827362Sgblack@eecs.umich.edu 48310037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 48410037SARM gem5 Developers{ 48510037SARM gem5 Developers public: 48610037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 48710037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 48810037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 48910037SARM gem5 Developers 49010037SARM gem5 Developers VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 49110037SARM gem5 Developers uint8_t _source) : 49210037SARM gem5 Developers AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 49310037SARM gem5 Developers {} 49410037SARM gem5 Developers 49512176Sandreas.sandberg@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst) override; 49610037SARM gem5 Developers}; 49710037SARM gem5 Developers 49810037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt> 49910037SARM gem5 Developers{ 50010037SARM gem5 Developers public: 50112176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 50212176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 50312176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 50410037SARM gem5 Developers}; 50510037SARM gem5 Developers 50610037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 50710037SARM gem5 Developers{ 50810037SARM gem5 Developers public: 50910037SARM gem5 Developers VirtualInterrupt(); 51010037SARM gem5 Developers}; 51110037SARM gem5 Developers 51210037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt> 51310037SARM gem5 Developers{ 51410037SARM gem5 Developers public: 51512176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 51612176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 51712176Sandreas.sandberg@arm.com bool abortDisable(ThreadContext *tc) override; 51812176Sandreas.sandberg@arm.com bool fiqDisable(ThreadContext *tc) override; 51910037SARM gem5 Developers}; 52010037SARM gem5 Developers 52110037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 52210037SARM gem5 Developers{ 52310037SARM gem5 Developers public: 52410037SARM gem5 Developers VirtualFastInterrupt(); 52510037SARM gem5 Developers}; 52610037SARM gem5 Developers 52710037SARM gem5 Developers/// PC alignment fault (AArch64 only) 52810037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 52910037SARM gem5 Developers{ 53010037SARM gem5 Developers protected: 53110037SARM gem5 Developers /// The unaligned value of the PC 53210037SARM gem5 Developers Addr faultPC; 53310037SARM gem5 Developers public: 53410037SARM gem5 Developers PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 53510037SARM gem5 Developers {} 53610417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 53712176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 53810037SARM gem5 Developers}; 53910037SARM gem5 Developers 54010037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only) 54110037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 54210037SARM gem5 Developers{ 54310037SARM gem5 Developers public: 54410037SARM gem5 Developers SPAlignmentFault(); 54510037SARM gem5 Developers}; 54610037SARM gem5 Developers 54710037SARM gem5 Developers/// System error (AArch64 only) 54810037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError> 54910037SARM gem5 Developers{ 55010037SARM gem5 Developers public: 55110037SARM gem5 Developers SystemError(); 55210417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 55312176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 55412176Sandreas.sandberg@arm.com bool routeToMonitor(ThreadContext *tc) const override; 55512176Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 55610037SARM gem5 Developers}; 5576019Shines@cs.fsu.edu 55812299Sandreas.sandberg@arm.com/// System error (AArch64 only) 55912299Sandreas.sandberg@arm.comclass SoftwareBreakpoint : public ArmFaultVals<SoftwareBreakpoint> 56012299Sandreas.sandberg@arm.com{ 56112299Sandreas.sandberg@arm.com public: 56212299Sandreas.sandberg@arm.com SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss); 56312299Sandreas.sandberg@arm.com 56412299Sandreas.sandberg@arm.com bool routeToHyp(ThreadContext *tc) const override; 56512299Sandreas.sandberg@arm.com}; 56612299Sandreas.sandberg@arm.com 5677652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5688518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev> 5698518Sgeoffrey.blake@arm.com{ 5708518Sgeoffrey.blake@arm.com public: 5718518Sgeoffrey.blake@arm.com ArmSev () {} 57210417Sandreas.hansson@arm.com void invoke(ThreadContext *tc, const StaticInstPtr &inst = 57312176Sandreas.sandberg@arm.com StaticInst::nullStaticInstPtr) override; 5748518Sgeoffrey.blake@arm.com}; 5758518Sgeoffrey.blake@arm.com 57610037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only) 57710037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 57810037SARM gem5 Developers{ 57910037SARM gem5 Developers public: 58010037SARM gem5 Developers IllegalInstSetStateFault(); 58110037SARM gem5 Developers}; 58210037SARM gem5 Developers 58311929SMatteo.Andreozzi@arm.com/* 58412032Sandreas.sandberg@arm.com * Explicitly declare template static member variables to avoid warnings 58512032Sandreas.sandberg@arm.com * in some clang versions 58611929SMatteo.Andreozzi@arm.com */ 58711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals; 58811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals; 58911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals; 59011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals; 59111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals; 59211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals; 59311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals; 59411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals; 59511929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals; 59611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals; 59711929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals; 59811929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals; 59911929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals; 60011929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals; 60111929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals; 60211929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals; 60311929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals; 60411929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals; 60512299Sandreas.sandberg@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals; 60611929SMatteo.Andreozzi@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals; 60711929SMatteo.Andreozzi@arm.com 60811929SMatteo.Andreozzi@arm.com 6097811Ssteve.reinhardt@amd.com} // namespace ArmISA 6106019Shines@cs.fsu.edu 6116019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 612