faults.hh revision 10037
16019Shines@cs.fsu.edu/* 210037SARM gem5 Developers * Copyright (c) 2010, 2012-2013 ARM Limited 37189Sgblack@eecs.umich.edu * All rights reserved 47189Sgblack@eecs.umich.edu * 57189Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67189Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77189Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87189Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97189Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107189Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117189Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127189Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137189Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#ifndef __ARM_FAULTS_HH__ 486019Shines@cs.fsu.edu#define __ARM_FAULTS_HH__ 496019Shines@cs.fsu.edu 507362Sgblack@eecs.umich.edu#include "arch/arm/miscregs.hh" 5110037SARM gem5 Developers#include "arch/arm/pagetable.hh" 526735Sgblack@eecs.umich.edu#include "arch/arm/types.hh" 538229Snate@binkert.org#include "base/misc.hh" 546019Shines@cs.fsu.edu#include "sim/faults.hh" 558782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 566019Shines@cs.fsu.edu 576019Shines@cs.fsu.edu// The design of the "name" and "vect" functions is in sim/faults.hh 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616735Sgblack@eecs.umich.edutypedef const Addr FaultOffset; 626019Shines@cs.fsu.edu 637362Sgblack@eecs.umich.educlass ArmFault : public FaultBase 646019Shines@cs.fsu.edu{ 656019Shines@cs.fsu.edu protected: 6610037SARM gem5 Developers ExtMachInst machInst; 6710037SARM gem5 Developers uint32_t issRaw; 6810037SARM gem5 Developers 6910037SARM gem5 Developers // Helper variables for ARMv8 exception handling 7010037SARM gem5 Developers bool from64; // True if the exception is generated from the AArch64 state 7110037SARM gem5 Developers bool to64; // True if the exception is taken in AArch64 state 7210037SARM gem5 Developers ExceptionLevel fromEL; // Source exception level 7310037SARM gem5 Developers ExceptionLevel toEL; // Target exception level 7410037SARM gem5 Developers OperatingMode fromMode; // Source operating mode 7510037SARM gem5 Developers 766735Sgblack@eecs.umich.edu Addr getVector(ThreadContext *tc); 7710037SARM gem5 Developers Addr getVector64(ThreadContext *tc); 786735Sgblack@eecs.umich.edu 796019Shines@cs.fsu.edu public: 8010037SARM gem5 Developers /// Generic fault source enums used to index into 8110037SARM gem5 Developers /// {short/long/aarch64}DescFaultSources[] to get the actual encodings based 8210037SARM gem5 Developers /// on the current register width state and the translation table format in 8310037SARM gem5 Developers /// use 8410037SARM gem5 Developers enum FaultSource 857362Sgblack@eecs.umich.edu { 8610037SARM gem5 Developers AlignmentFault = 0, 8710037SARM gem5 Developers InstructionCacheMaintenance, // Short-desc. format only 8810037SARM gem5 Developers SynchExtAbtOnTranslTableWalkLL, 8910037SARM gem5 Developers SynchPtyErrOnTranslTableWalkLL = SynchExtAbtOnTranslTableWalkLL + 4, 9010037SARM gem5 Developers TranslationLL = SynchPtyErrOnTranslTableWalkLL + 4, 9110037SARM gem5 Developers AccessFlagLL = TranslationLL + 4, 9210037SARM gem5 Developers DomainLL = AccessFlagLL + 4, 9310037SARM gem5 Developers PermissionLL = DomainLL + 4, 9410037SARM gem5 Developers DebugEvent = PermissionLL + 4, 9510037SARM gem5 Developers SynchronousExternalAbort, 9610037SARM gem5 Developers TLBConflictAbort, // Requires LPAE 9710037SARM gem5 Developers SynchPtyErrOnMemoryAccess, 9810037SARM gem5 Developers AsynchronousExternalAbort, 9910037SARM gem5 Developers AsynchPtyErrOnMemoryAccess, 10010037SARM gem5 Developers AddressSizeLL, // AArch64 only 1017611SGene.Wu@arm.com 10210037SARM gem5 Developers // Not real faults. These are faults to allow the translation function 10310037SARM gem5 Developers // to inform the memory access function not to proceed for a prefetch 10410037SARM gem5 Developers // that misses in the TLB or that targets an uncacheable address 10510037SARM gem5 Developers PrefetchTLBMiss = AddressSizeLL + 4, 10610037SARM gem5 Developers PrefetchUncacheable, 10710037SARM gem5 Developers 10810037SARM gem5 Developers NumFaultSources, 10910037SARM gem5 Developers FaultSourceInvalid = 0xff 11010037SARM gem5 Developers }; 11110037SARM gem5 Developers 11210037SARM gem5 Developers /// Encodings of the fault sources when the short-desc. translation table 11310037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11410037SARM gem5 Developers static uint8_t shortDescFaultSources[NumFaultSources]; 11510037SARM gem5 Developers /// Encodings of the fault sources when the long-desc. translation table 11610037SARM gem5 Developers /// format is in use (ARM ARM Issue C B3.13.3) 11710037SARM gem5 Developers static uint8_t longDescFaultSources[NumFaultSources]; 11810037SARM gem5 Developers /// Encodings of the fault sources in AArch64 state 11910037SARM gem5 Developers static uint8_t aarch64FaultSources[NumFaultSources]; 12010037SARM gem5 Developers 12110037SARM gem5 Developers enum AnnotationIDs 12210037SARM gem5 Developers { 12310037SARM gem5 Developers S1PTW, // DataAbort, PrefetchAbort: Stage 1 Page Table Walk, 12410037SARM gem5 Developers OVA, // DataAbort, PrefetchAbort: stage 1 Virtual Address for stage 2 faults 12510037SARM gem5 Developers SAS, // DataAbort: Syndrome Access Size 12610037SARM gem5 Developers SSE, // DataAbort: Syndrome Sign Extend 12710037SARM gem5 Developers SRT, // DataAbort: Syndrome Register Transfer 12810037SARM gem5 Developers 12910037SARM gem5 Developers // AArch64 only 13010037SARM gem5 Developers SF, // DataAbort: width of the accessed register is SixtyFour 13110037SARM gem5 Developers AR // DataAbort: Acquire/Release semantics 13210037SARM gem5 Developers }; 13310037SARM gem5 Developers 13410037SARM gem5 Developers enum TranMethod 13510037SARM gem5 Developers { 13610037SARM gem5 Developers LpaeTran, 13710037SARM gem5 Developers VmsaTran, 13810037SARM gem5 Developers UnknownTran 1397362Sgblack@eecs.umich.edu }; 1407362Sgblack@eecs.umich.edu 1416735Sgblack@eecs.umich.edu struct FaultVals 1426735Sgblack@eecs.umich.edu { 1436735Sgblack@eecs.umich.edu const FaultName name; 14410037SARM gem5 Developers 1456735Sgblack@eecs.umich.edu const FaultOffset offset; 14610037SARM gem5 Developers 14710037SARM gem5 Developers // Offsets used for exceptions taken in AArch64 state 14810037SARM gem5 Developers const uint16_t currELTOffset; 14910037SARM gem5 Developers const uint16_t currELHOffset; 15010037SARM gem5 Developers const uint16_t lowerEL64Offset; 15110037SARM gem5 Developers const uint16_t lowerEL32Offset; 15210037SARM gem5 Developers 1536735Sgblack@eecs.umich.edu const OperatingMode nextMode; 15410037SARM gem5 Developers 1556735Sgblack@eecs.umich.edu const uint8_t armPcOffset; 1566735Sgblack@eecs.umich.edu const uint8_t thumbPcOffset; 15710037SARM gem5 Developers // The following two values are used in place of armPcOffset and 15810037SARM gem5 Developers // thumbPcOffset when the exception return address is saved into ELR 15910037SARM gem5 Developers // registers (exceptions taken in HYP mode or in AArch64 state) 16010037SARM gem5 Developers const uint8_t armPcElrOffset; 16110037SARM gem5 Developers const uint8_t thumbPcElrOffset; 16210037SARM gem5 Developers 16310037SARM gem5 Developers const bool hypTrappable; 1646735Sgblack@eecs.umich.edu const bool abortDisable; 1656735Sgblack@eecs.umich.edu const bool fiqDisable; 16610037SARM gem5 Developers 16710037SARM gem5 Developers // Exception class used to appropriately set the syndrome register 16810037SARM gem5 Developers // (exceptions taken in HYP mode or in AArch64 state) 16910037SARM gem5 Developers const ExceptionClass ec; 17010037SARM gem5 Developers 1716735Sgblack@eecs.umich.edu FaultStat count; 1726735Sgblack@eecs.umich.edu }; 1736735Sgblack@eecs.umich.edu 17410037SARM gem5 Developers ArmFault(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 17510037SARM gem5 Developers machInst(_machInst), issRaw(_iss), from64(false), to64(false) {} 17610037SARM gem5 Developers 17710037SARM gem5 Developers // Returns the actual syndrome register to use based on the target 17810037SARM gem5 Developers // exception level 17910037SARM gem5 Developers MiscRegIndex getSyndromeReg64() const; 18010037SARM gem5 Developers // Returns the actual fault address register to use based on the target 18110037SARM gem5 Developers // exception level 18210037SARM gem5 Developers MiscRegIndex getFaultAddrReg64() const; 18310037SARM gem5 Developers 1847678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 1857678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 18610037SARM gem5 Developers void invoke64(ThreadContext *tc, 18710037SARM gem5 Developers StaticInstPtr inst = StaticInst::nullStaticInstPtr); 18810037SARM gem5 Developers virtual void annotate(AnnotationIDs id, uint64_t val) {} 1896735Sgblack@eecs.umich.edu virtual FaultStat& countStat() = 0; 19010037SARM gem5 Developers virtual FaultOffset offset(ThreadContext *tc) = 0; 19110037SARM gem5 Developers virtual FaultOffset offset64() = 0; 1926735Sgblack@eecs.umich.edu virtual OperatingMode nextMode() = 0; 19310037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const = 0; 19410037SARM gem5 Developers virtual bool routeToHyp(ThreadContext *tc) const { return false; } 19510037SARM gem5 Developers virtual uint8_t armPcOffset(bool isHyp) = 0; 19610037SARM gem5 Developers virtual uint8_t thumbPcOffset(bool isHyp) = 0; 19710037SARM gem5 Developers virtual uint8_t armPcElrOffset() = 0; 19810037SARM gem5 Developers virtual uint8_t thumbPcElrOffset() = 0; 19910037SARM gem5 Developers virtual bool abortDisable(ThreadContext *tc) = 0; 20010037SARM gem5 Developers virtual bool fiqDisable(ThreadContext *tc) = 0; 20110037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const = 0; 20210037SARM gem5 Developers virtual uint32_t iss() const = 0; 20310037SARM gem5 Developers virtual bool isStage2() const { return false; } 20410037SARM gem5 Developers virtual FSR getFsr(ThreadContext *tc) { return 0; } 20510037SARM gem5 Developers virtual void setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg); 2066019Shines@cs.fsu.edu}; 2076019Shines@cs.fsu.edu 2086735Sgblack@eecs.umich.edutemplate<typename T> 2097362Sgblack@eecs.umich.educlass ArmFaultVals : public ArmFault 2106019Shines@cs.fsu.edu{ 2116735Sgblack@eecs.umich.edu protected: 2126735Sgblack@eecs.umich.edu static FaultVals vals; 2136735Sgblack@eecs.umich.edu 2146019Shines@cs.fsu.edu public: 21510037SARM gem5 Developers ArmFaultVals<T>(ExtMachInst _machInst = 0, uint32_t _iss = 0) : 21610037SARM gem5 Developers ArmFault(_machInst, _iss) {} 2176735Sgblack@eecs.umich.edu FaultName name() const { return vals.name; } 21810037SARM gem5 Developers FaultStat & countStat() { return vals.count; } 21910037SARM gem5 Developers FaultOffset offset(ThreadContext *tc); 22010037SARM gem5 Developers 22110037SARM gem5 Developers FaultOffset 22210037SARM gem5 Developers offset64() 22310037SARM gem5 Developers { 22410037SARM gem5 Developers if (toEL == fromEL) { 22510037SARM gem5 Developers if (opModeIsT(fromMode)) 22610037SARM gem5 Developers return vals.currELTOffset; 22710037SARM gem5 Developers return vals.currELHOffset; 22810037SARM gem5 Developers } else { 22910037SARM gem5 Developers if (from64) 23010037SARM gem5 Developers return vals.lowerEL64Offset; 23110037SARM gem5 Developers return vals.lowerEL32Offset; 23210037SARM gem5 Developers } 23310037SARM gem5 Developers } 23410037SARM gem5 Developers 2356735Sgblack@eecs.umich.edu OperatingMode nextMode() { return vals.nextMode; } 23610037SARM gem5 Developers virtual bool routeToMonitor(ThreadContext *tc) const { return false; } 23710037SARM gem5 Developers uint8_t armPcOffset(bool isHyp) { return isHyp ? vals.armPcElrOffset 23810037SARM gem5 Developers : vals.armPcOffset; } 23910037SARM gem5 Developers uint8_t thumbPcOffset(bool isHyp) { return isHyp ? vals.thumbPcElrOffset 24010037SARM gem5 Developers : vals.thumbPcOffset; } 24110037SARM gem5 Developers uint8_t armPcElrOffset() { return vals.armPcElrOffset; } 24210037SARM gem5 Developers uint8_t thumbPcElrOffset() { return vals.thumbPcElrOffset; } 24310037SARM gem5 Developers virtual bool abortDisable(ThreadContext* tc) { return vals.abortDisable; } 24410037SARM gem5 Developers virtual bool fiqDisable(ThreadContext* tc) { return vals.fiqDisable; } 24510037SARM gem5 Developers virtual ExceptionClass ec(ThreadContext *tc) const { return vals.ec; } 24610037SARM gem5 Developers virtual uint32_t iss() const { return issRaw; } 2476019Shines@cs.fsu.edu}; 2486019Shines@cs.fsu.edu 2497400SAli.Saidi@ARM.comclass Reset : public ArmFaultVals<Reset> 2507400SAli.Saidi@ARM.com{ 2517400SAli.Saidi@ARM.com public: 2527678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 2537678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 2547400SAli.Saidi@ARM.com}; 2557189Sgblack@eecs.umich.edu 2567362Sgblack@eecs.umich.educlass UndefinedInstruction : public ArmFaultVals<UndefinedInstruction> 2577189Sgblack@eecs.umich.edu{ 2587189Sgblack@eecs.umich.edu protected: 2597189Sgblack@eecs.umich.edu bool unknown; 2607189Sgblack@eecs.umich.edu const char *mnemonic; 2617640Sgblack@eecs.umich.edu bool disabled; 26210037SARM gem5 Developers ExceptionClass overrideEc; 2637189Sgblack@eecs.umich.edu 2647189Sgblack@eecs.umich.edu public: 2657189Sgblack@eecs.umich.edu UndefinedInstruction(ExtMachInst _machInst, 2667189Sgblack@eecs.umich.edu bool _unknown, 2677640Sgblack@eecs.umich.edu const char *_mnemonic = NULL, 2687640Sgblack@eecs.umich.edu bool _disabled = false) : 26910037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst), 27010037SARM gem5 Developers unknown(_unknown), mnemonic(_mnemonic), disabled(_disabled), 27110037SARM gem5 Developers overrideEc(EC_INVALID) 27210037SARM gem5 Developers {} 27310037SARM gem5 Developers UndefinedInstruction(ExtMachInst _machInst, uint32_t _iss, ExceptionClass _overrideEc) : 27410037SARM gem5 Developers ArmFaultVals<UndefinedInstruction>(_machInst, _iss), 27510037SARM gem5 Developers overrideEc(_overrideEc) 2768782Sgblack@eecs.umich.edu {} 2777189Sgblack@eecs.umich.edu 2787678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 2797678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 28010037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 28110037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 28210037SARM gem5 Developers uint32_t iss() const; 2837189Sgblack@eecs.umich.edu}; 2847189Sgblack@eecs.umich.edu 2857362Sgblack@eecs.umich.educlass SupervisorCall : public ArmFaultVals<SupervisorCall> 2867197Sgblack@eecs.umich.edu{ 2877197Sgblack@eecs.umich.edu protected: 28810037SARM gem5 Developers ExceptionClass overrideEc; 2897197Sgblack@eecs.umich.edu public: 29010037SARM gem5 Developers SupervisorCall(ExtMachInst _machInst, uint32_t _iss, 29110037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 29210037SARM gem5 Developers ArmFaultVals<SupervisorCall>(_machInst, _iss), 29310037SARM gem5 Developers overrideEc(_overrideEc) 2948782Sgblack@eecs.umich.edu {} 2957197Sgblack@eecs.umich.edu 2967678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 2977678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 29810037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 29910037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 30010037SARM gem5 Developers uint32_t iss() const; 30110037SARM gem5 Developers}; 30210037SARM gem5 Developers 30310037SARM gem5 Developersclass SecureMonitorCall : public ArmFaultVals<SecureMonitorCall> 30410037SARM gem5 Developers{ 30510037SARM gem5 Developers public: 30610037SARM gem5 Developers SecureMonitorCall(ExtMachInst _machInst) : 30710037SARM gem5 Developers ArmFaultVals<SecureMonitorCall>(_machInst) 30810037SARM gem5 Developers {} 30910037SARM gem5 Developers 31010037SARM gem5 Developers void invoke(ThreadContext *tc, 31110037SARM gem5 Developers StaticInstPtr inst = StaticInst::nullStaticInstPtr); 31210037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 31310037SARM gem5 Developers uint32_t iss() const; 31410037SARM gem5 Developers}; 31510037SARM gem5 Developers 31610037SARM gem5 Developersclass SupervisorTrap : public ArmFaultVals<SupervisorTrap> 31710037SARM gem5 Developers{ 31810037SARM gem5 Developers protected: 31910037SARM gem5 Developers ExtMachInst machInst; 32010037SARM gem5 Developers ExceptionClass overrideEc; 32110037SARM gem5 Developers 32210037SARM gem5 Developers public: 32310037SARM gem5 Developers SupervisorTrap(ExtMachInst _machInst, uint32_t _iss, 32410037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 32510037SARM gem5 Developers ArmFaultVals<SupervisorTrap>(_machInst, _iss), 32610037SARM gem5 Developers overrideEc(_overrideEc) 32710037SARM gem5 Developers {} 32810037SARM gem5 Developers 32910037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 33010037SARM gem5 Developers}; 33110037SARM gem5 Developers 33210037SARM gem5 Developersclass SecureMonitorTrap : public ArmFaultVals<SecureMonitorTrap> 33310037SARM gem5 Developers{ 33410037SARM gem5 Developers protected: 33510037SARM gem5 Developers ExtMachInst machInst; 33610037SARM gem5 Developers ExceptionClass overrideEc; 33710037SARM gem5 Developers 33810037SARM gem5 Developers public: 33910037SARM gem5 Developers SecureMonitorTrap(ExtMachInst _machInst, uint32_t _iss, 34010037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 34110037SARM gem5 Developers ArmFaultVals<SecureMonitorTrap>(_machInst, _iss), 34210037SARM gem5 Developers overrideEc(_overrideEc) 34310037SARM gem5 Developers {} 34410037SARM gem5 Developers 34510037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 34610037SARM gem5 Developers}; 34710037SARM gem5 Developers 34810037SARM gem5 Developersclass HypervisorCall : public ArmFaultVals<HypervisorCall> 34910037SARM gem5 Developers{ 35010037SARM gem5 Developers public: 35110037SARM gem5 Developers HypervisorCall(ExtMachInst _machInst, uint32_t _imm); 35210037SARM gem5 Developers}; 35310037SARM gem5 Developers 35410037SARM gem5 Developersclass HypervisorTrap : public ArmFaultVals<HypervisorTrap> 35510037SARM gem5 Developers{ 35610037SARM gem5 Developers protected: 35710037SARM gem5 Developers ExtMachInst machInst; 35810037SARM gem5 Developers ExceptionClass overrideEc; 35910037SARM gem5 Developers 36010037SARM gem5 Developers public: 36110037SARM gem5 Developers HypervisorTrap(ExtMachInst _machInst, uint32_t _iss, 36210037SARM gem5 Developers ExceptionClass _overrideEc = EC_INVALID) : 36310037SARM gem5 Developers ArmFaultVals<HypervisorTrap>(_machInst, _iss), 36410037SARM gem5 Developers overrideEc(_overrideEc) 36510037SARM gem5 Developers {} 36610037SARM gem5 Developers 36710037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 3687197Sgblack@eecs.umich.edu}; 3697362Sgblack@eecs.umich.edu 3707362Sgblack@eecs.umich.edutemplate <class T> 3717362Sgblack@eecs.umich.educlass AbortFault : public ArmFaultVals<T> 3727362Sgblack@eecs.umich.edu{ 3737362Sgblack@eecs.umich.edu protected: 37410037SARM gem5 Developers /** 37510037SARM gem5 Developers * The virtual address the fault occured at. If 2 stages of 37610037SARM gem5 Developers * translation are being used then this is the intermediate 37710037SARM gem5 Developers * physical address that is the starting point for the second 37810037SARM gem5 Developers * stage of translation. 37910037SARM gem5 Developers */ 3807362Sgblack@eecs.umich.edu Addr faultAddr; 38110037SARM gem5 Developers /** 38210037SARM gem5 Developers * Original virtual address. If the fault was generated on the 38310037SARM gem5 Developers * second stage of translation then this variable stores the 38410037SARM gem5 Developers * virtual address used in the original stage 1 translation. 38510037SARM gem5 Developers */ 38610037SARM gem5 Developers Addr OVAddr; 3877362Sgblack@eecs.umich.edu bool write; 38810037SARM gem5 Developers TlbEntry::DomainType domain; 38910037SARM gem5 Developers uint8_t source; 39010037SARM gem5 Developers uint8_t srcEncoded; 39110037SARM gem5 Developers bool stage2; 39210037SARM gem5 Developers bool s1ptw; 39310037SARM gem5 Developers ArmFault::TranMethod tranMethod; 3947362Sgblack@eecs.umich.edu 3957362Sgblack@eecs.umich.edu public: 39610037SARM gem5 Developers AbortFault(Addr _faultAddr, bool _write, TlbEntry::DomainType _domain, uint8_t _source, 39710037SARM gem5 Developers bool _stage2, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 39810037SARM gem5 Developers faultAddr(_faultAddr), write(_write), domain(_domain), source(_source), 39910037SARM gem5 Developers stage2(_stage2), s1ptw(false), tranMethod(_tranMethod) 4007362Sgblack@eecs.umich.edu {} 4017362Sgblack@eecs.umich.edu 4027678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 4037678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 40410037SARM gem5 Developers 40510037SARM gem5 Developers FSR getFsr(ThreadContext *tc); 40610037SARM gem5 Developers bool abortDisable(ThreadContext *tc); 40710037SARM gem5 Developers uint32_t iss() const; 40810037SARM gem5 Developers bool isStage2() const { return stage2; } 40910037SARM gem5 Developers void annotate(ArmFault::AnnotationIDs id, uint64_t val); 41010037SARM gem5 Developers bool isMMUFault() const; 4117362Sgblack@eecs.umich.edu}; 4127362Sgblack@eecs.umich.edu 4137362Sgblack@eecs.umich.educlass PrefetchAbort : public AbortFault<PrefetchAbort> 4147362Sgblack@eecs.umich.edu{ 4157362Sgblack@eecs.umich.edu public: 41610037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_IFSR; 41710037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_IFAR; 41810037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HIFAR; 4197362Sgblack@eecs.umich.edu 42010037SARM gem5 Developers PrefetchAbort(Addr _addr, uint8_t _source, bool _stage2 = false, 42110037SARM gem5 Developers ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 42210037SARM gem5 Developers AbortFault<PrefetchAbort>(_addr, false, TlbEntry::DomainType::NoAccess, 42310037SARM gem5 Developers _source, _stage2, _tranMethod) 4247362Sgblack@eecs.umich.edu {} 42510037SARM gem5 Developers 42610037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 42710037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 42810037SARM gem5 Developers bool routeToMonitor(ThreadContext *tc) const; 42910037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 4307362Sgblack@eecs.umich.edu}; 4317362Sgblack@eecs.umich.edu 4327362Sgblack@eecs.umich.educlass DataAbort : public AbortFault<DataAbort> 4337362Sgblack@eecs.umich.edu{ 4347362Sgblack@eecs.umich.edu public: 43510037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 43610037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 43710037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 43810037SARM gem5 Developers bool isv; 43910037SARM gem5 Developers uint8_t sas; 44010037SARM gem5 Developers uint8_t sse; 44110037SARM gem5 Developers uint8_t srt; 4427362Sgblack@eecs.umich.edu 44310037SARM gem5 Developers // AArch64 only 44410037SARM gem5 Developers bool sf; 44510037SARM gem5 Developers bool ar; 44610037SARM gem5 Developers 44710037SARM gem5 Developers DataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, uint8_t _source, 44810037SARM gem5 Developers bool _stage2 = false, ArmFault::TranMethod _tranMethod = ArmFault::UnknownTran) : 44910037SARM gem5 Developers AbortFault<DataAbort>(_addr, _write, _domain, _source, _stage2, 45010037SARM gem5 Developers _tranMethod), 45110037SARM gem5 Developers isv(false), sas (0), sse(0), srt(0), sf(false), ar(false) 4527362Sgblack@eecs.umich.edu {} 45310037SARM gem5 Developers 45410037SARM gem5 Developers ExceptionClass ec(ThreadContext *tc) const; 45510037SARM gem5 Developers // @todo: external aborts should be routed if SCR.EA == 1 45610037SARM gem5 Developers bool routeToMonitor(ThreadContext *tc) const; 45710037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 45810037SARM gem5 Developers uint32_t iss() const; 45910037SARM gem5 Developers void annotate(AnnotationIDs id, uint64_t val); 4607362Sgblack@eecs.umich.edu}; 4617362Sgblack@eecs.umich.edu 46210037SARM gem5 Developersclass VirtualDataAbort : public AbortFault<VirtualDataAbort> 46310037SARM gem5 Developers{ 46410037SARM gem5 Developers public: 46510037SARM gem5 Developers static const MiscRegIndex FsrIndex = MISCREG_DFSR; 46610037SARM gem5 Developers static const MiscRegIndex FarIndex = MISCREG_DFAR; 46710037SARM gem5 Developers static const MiscRegIndex HFarIndex = MISCREG_HDFAR; 46810037SARM gem5 Developers 46910037SARM gem5 Developers VirtualDataAbort(Addr _addr, TlbEntry::DomainType _domain, bool _write, 47010037SARM gem5 Developers uint8_t _source) : 47110037SARM gem5 Developers AbortFault<VirtualDataAbort>(_addr, _write, _domain, _source, false) 47210037SARM gem5 Developers {} 47310037SARM gem5 Developers 47410037SARM gem5 Developers void invoke(ThreadContext *tc, StaticInstPtr inst); 47510037SARM gem5 Developers}; 47610037SARM gem5 Developers 47710037SARM gem5 Developersclass Interrupt : public ArmFaultVals<Interrupt> 47810037SARM gem5 Developers{ 47910037SARM gem5 Developers public: 48010037SARM gem5 Developers bool routeToMonitor(ThreadContext *tc) const; 48110037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 48210037SARM gem5 Developers bool abortDisable(ThreadContext *tc); 48310037SARM gem5 Developers}; 48410037SARM gem5 Developers 48510037SARM gem5 Developersclass VirtualInterrupt : public ArmFaultVals<VirtualInterrupt> 48610037SARM gem5 Developers{ 48710037SARM gem5 Developers public: 48810037SARM gem5 Developers VirtualInterrupt(); 48910037SARM gem5 Developers}; 49010037SARM gem5 Developers 49110037SARM gem5 Developersclass FastInterrupt : public ArmFaultVals<FastInterrupt> 49210037SARM gem5 Developers{ 49310037SARM gem5 Developers public: 49410037SARM gem5 Developers bool routeToMonitor(ThreadContext *tc) const; 49510037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 49610037SARM gem5 Developers bool abortDisable(ThreadContext *tc); 49710037SARM gem5 Developers bool fiqDisable(ThreadContext *tc); 49810037SARM gem5 Developers}; 49910037SARM gem5 Developers 50010037SARM gem5 Developersclass VirtualFastInterrupt : public ArmFaultVals<VirtualFastInterrupt> 50110037SARM gem5 Developers{ 50210037SARM gem5 Developers public: 50310037SARM gem5 Developers VirtualFastInterrupt(); 50410037SARM gem5 Developers}; 50510037SARM gem5 Developers 50610037SARM gem5 Developers/// PC alignment fault (AArch64 only) 50710037SARM gem5 Developersclass PCAlignmentFault : public ArmFaultVals<PCAlignmentFault> 50810037SARM gem5 Developers{ 50910037SARM gem5 Developers protected: 51010037SARM gem5 Developers /// The unaligned value of the PC 51110037SARM gem5 Developers Addr faultPC; 51210037SARM gem5 Developers public: 51310037SARM gem5 Developers PCAlignmentFault(Addr _faultPC) : faultPC(_faultPC) 51410037SARM gem5 Developers {} 51510037SARM gem5 Developers void invoke(ThreadContext *tc, 51610037SARM gem5 Developers StaticInstPtr inst = StaticInst::nullStaticInstPtr); 51710037SARM gem5 Developers}; 51810037SARM gem5 Developers 51910037SARM gem5 Developers/// Stack pointer alignment fault (AArch64 only) 52010037SARM gem5 Developersclass SPAlignmentFault : public ArmFaultVals<SPAlignmentFault> 52110037SARM gem5 Developers{ 52210037SARM gem5 Developers public: 52310037SARM gem5 Developers SPAlignmentFault(); 52410037SARM gem5 Developers}; 52510037SARM gem5 Developers 52610037SARM gem5 Developers/// System error (AArch64 only) 52710037SARM gem5 Developersclass SystemError : public ArmFaultVals<SystemError> 52810037SARM gem5 Developers{ 52910037SARM gem5 Developers public: 53010037SARM gem5 Developers SystemError(); 53110037SARM gem5 Developers void invoke(ThreadContext *tc, 53210037SARM gem5 Developers StaticInstPtr inst = StaticInst::nullStaticInstPtr); 53310037SARM gem5 Developers bool routeToMonitor(ThreadContext *tc) const; 53410037SARM gem5 Developers bool routeToHyp(ThreadContext *tc) const; 53510037SARM gem5 Developers}; 5366019Shines@cs.fsu.edu 5377652Sminkyu.jeong@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5387652Sminkyu.jeong@arm.comclass FlushPipe : public ArmFaultVals<FlushPipe> 5397652Sminkyu.jeong@arm.com{ 5407652Sminkyu.jeong@arm.com public: 5417652Sminkyu.jeong@arm.com FlushPipe() {} 5427678Sgblack@eecs.umich.edu void invoke(ThreadContext *tc, 5437678Sgblack@eecs.umich.edu StaticInstPtr inst = StaticInst::nullStaticInstPtr); 5447652Sminkyu.jeong@arm.com}; 5457652Sminkyu.jeong@arm.com 5468518Sgeoffrey.blake@arm.com// A fault that flushes the pipe, excluding the faulting instructions 5478518Sgeoffrey.blake@arm.comclass ArmSev : public ArmFaultVals<ArmSev> 5488518Sgeoffrey.blake@arm.com{ 5498518Sgeoffrey.blake@arm.com public: 5508518Sgeoffrey.blake@arm.com ArmSev () {} 5518518Sgeoffrey.blake@arm.com void invoke(ThreadContext *tc, 5528518Sgeoffrey.blake@arm.com StaticInstPtr inst = StaticInst::nullStaticInstPtr); 5538518Sgeoffrey.blake@arm.com}; 5548518Sgeoffrey.blake@arm.com 55510037SARM gem5 Developers/// Illegal Instruction Set State fault (AArch64 only) 55610037SARM gem5 Developersclass IllegalInstSetStateFault : public ArmFaultVals<IllegalInstSetStateFault> 55710037SARM gem5 Developers{ 55810037SARM gem5 Developers public: 55910037SARM gem5 Developers IllegalInstSetStateFault(); 56010037SARM gem5 Developers}; 56110037SARM gem5 Developers 5627811Ssteve.reinhardt@amd.com} // namespace ArmISA 5636019Shines@cs.fsu.edu 5646019Shines@cs.fsu.edu#endif // __ARM_FAULTS_HH__ 565