faults.cc revision 8545:a3992291e230 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50
51namespace ArmISA
52{
53
54template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
55    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
56
57template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
58    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
59
60template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
61    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
62
63template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
64    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65
66template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
67    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68
69template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
70    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
71
72template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
73    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74
75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
76    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
77
78template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals =
79    {"ArmSev Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
80Addr
81ArmFault::getVector(ThreadContext *tc)
82{
83    // ARM ARM B1-3
84
85    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
86
87    // panic if SCTLR.VE because I have no idea what to do with vectored
88    // interrupts
89    assert(!sctlr.ve);
90
91    if (!sctlr.v)
92        return offset();
93    return offset() + HighVecs;
94
95}
96
97#if FULL_SYSTEM
98
99void
100ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
101{
102    // ARM ARM B1.6.3
103    FaultBase::invoke(tc);
104    countStat()++;
105
106    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
107    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
108    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
109    saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
110    saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
111    saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
112    saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
113
114    Addr curPc M5_VAR_USED = tc->pcState().pc();
115    ITSTATE it = tc->pcState().itstate();
116    saved_cpsr.it2 = it.top6;
117    saved_cpsr.it1 = it.bottom2;
118
119    cpsr.mode = nextMode();
120    cpsr.it1 = cpsr.it2 = 0;
121    cpsr.j = 0;
122
123    cpsr.t = sctlr.te;
124    cpsr.a = cpsr.a | abortDisable();
125    cpsr.f = cpsr.f | fiqDisable();
126    cpsr.i = 1;
127    cpsr.e = sctlr.ee;
128    tc->setMiscReg(MISCREG_CPSR, cpsr);
129    // Make sure mailbox sets to one always
130    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
131    tc->setIntReg(INTREG_LR, curPc +
132            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
133
134    switch (nextMode()) {
135      case MODE_FIQ:
136        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
137        break;
138      case MODE_IRQ:
139        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
140        break;
141      case MODE_SVC:
142        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
143        break;
144      case MODE_UNDEFINED:
145        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
146        break;
147      case MODE_ABORT:
148        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
149        break;
150      default:
151        panic("unknown Mode\n");
152    }
153
154    Addr newPc = getVector(tc);
155    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
156            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
157    PCState pc(newPc);
158    pc.thumb(cpsr.t);
159    pc.nextThumb(pc.thumb());
160    pc.jazelle(cpsr.j);
161    pc.nextJazelle(pc.jazelle());
162    tc->pcState(pc);
163}
164
165void
166Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
167{
168    tc->getCpuPtr()->clearInterrupts();
169    tc->clearArchRegs();
170    ArmFault::invoke(tc, inst);
171}
172
173#else
174
175void
176UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
177{
178    // If the mnemonic isn't defined this has to be an unknown instruction.
179    assert(unknown || mnemonic != NULL);
180    if (disabled) {
181        panic("Attempted to execute disabled instruction "
182                "'%s' (inst 0x%08x)", mnemonic, machInst);
183    } else if (unknown) {
184        panic("Attempted to execute unknown instruction (inst 0x%08x)",
185              machInst);
186    } else {
187        panic("Attempted to execute unimplemented instruction "
188                "'%s' (inst 0x%08x)", mnemonic, machInst);
189    }
190}
191
192void
193SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
194{
195    // As of now, there isn't a 32 bit thumb version of this instruction.
196    assert(!machInst.bigThumb);
197    uint32_t callNum;
198    callNum = tc->readIntReg(INTREG_R7);
199    tc->syscall(callNum);
200
201    // Advance the PC since that won't happen automatically.
202    PCState pc = tc->pcState();
203    assert(inst);
204    inst->advancePC(pc);
205    tc->pcState(pc);
206}
207
208#endif // FULL_SYSTEM
209
210template<class T>
211void
212AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
213{
214    ArmFaultVals<T>::invoke(tc, inst);
215    FSR fsr = 0;
216    fsr.fsLow = bits(status, 3, 0);
217    fsr.fsHigh = bits(status, 4);
218    fsr.domain = domain;
219    fsr.wnr = (write ? 1 : 0);
220    fsr.ext = 0;
221    tc->setMiscReg(T::FsrIndex, fsr);
222    tc->setMiscReg(T::FarIndex, faultAddr);
223
224    DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr);
225}
226
227void
228FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
229    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
230
231    // Set the PC to the next instruction of the faulting instruction.
232    // Net effect is simply squashing all instructions behind and
233    // start refetching from the next instruction.
234    PCState pc = tc->pcState();
235    assert(inst);
236    inst->advancePC(pc);
237    tc->pcState(pc);
238}
239
240template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
241                                                StaticInstPtr inst);
242template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
243                                            StaticInstPtr inst);
244
245void
246ArmSev::invoke(ThreadContext *tc, StaticInstPtr inst) {
247    DPRINTF(Faults, "Invoking ArmSev Fault\n");
248#if FULL_SYSTEM
249    // Set sev_mailbox to 1, clear the pending interrupt from remote
250    // SEV execution and let pipeline continue as pcState is still
251    // valid.
252    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
253    tc->getCpuPtr()->clearInterrupt(INT_SEV, 0);
254#endif
255}
256
257// return via SUBS pc, lr, xxx; rfe, movs, ldm
258
259} // namespace ArmISA
260