faults.cc revision 8314:13ac7b9939ef 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 */
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/base.hh"
48#include "cpu/thread_context.hh"
49#include "debug/Faults.hh"
50
51namespace ArmISA
52{
53
54template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
55    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
56
57template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
58    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
59
60template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
61    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
62
63template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
64    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
65
66template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
67    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
68
69template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
70    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
71
72template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
73    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
74
75template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
76    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
77
78template<> ArmFault::FaultVals ArmFaultVals<ReExec>::vals =
79    {"ReExec Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
80
81Addr
82ArmFault::getVector(ThreadContext *tc)
83{
84    // ARM ARM B1-3
85
86    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
87
88    // panic if SCTLR.VE because I have no idea what to do with vectored
89    // interrupts
90    assert(!sctlr.ve);
91
92    if (!sctlr.v)
93        return offset();
94    return offset() + HighVecs;
95
96}
97
98#if FULL_SYSTEM
99
100void
101ArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
102{
103    // ARM ARM B1.6.3
104    FaultBase::invoke(tc);
105    countStat()++;
106
107    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
108    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
109    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
110    saved_cpsr.nz = tc->readIntReg(INTREG_CONDCODES_NZ);
111    saved_cpsr.c = tc->readIntReg(INTREG_CONDCODES_C);
112    saved_cpsr.v = tc->readIntReg(INTREG_CONDCODES_V);
113    saved_cpsr.ge = tc->readIntReg(INTREG_CONDCODES_GE);
114
115    Addr curPc M5_VAR_USED = tc->pcState().pc();
116    ITSTATE it = tc->pcState().itstate();
117    saved_cpsr.it2 = it.top6;
118    saved_cpsr.it1 = it.bottom2;
119
120    cpsr.mode = nextMode();
121    cpsr.it1 = cpsr.it2 = 0;
122    cpsr.j = 0;
123
124    cpsr.t = sctlr.te;
125    cpsr.a = cpsr.a | abortDisable();
126    cpsr.f = cpsr.f | fiqDisable();
127    cpsr.i = 1;
128    cpsr.e = sctlr.ee;
129    tc->setMiscReg(MISCREG_CPSR, cpsr);
130    tc->setIntReg(INTREG_LR, curPc +
131            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
132
133    switch (nextMode()) {
134      case MODE_FIQ:
135        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
136        break;
137      case MODE_IRQ:
138        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
139        break;
140      case MODE_SVC:
141        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
142        break;
143      case MODE_UNDEFINED:
144        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
145        break;
146      case MODE_ABORT:
147        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
148        break;
149      default:
150        panic("unknown Mode\n");
151    }
152
153    Addr newPc = getVector(tc);
154    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
155            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
156    PCState pc(newPc);
157    pc.thumb(cpsr.t);
158    pc.nextThumb(pc.thumb());
159    pc.jazelle(cpsr.j);
160    pc.nextJazelle(pc.jazelle());
161    tc->pcState(pc);
162}
163
164void
165Reset::invoke(ThreadContext *tc, StaticInstPtr inst)
166{
167    tc->getCpuPtr()->clearInterrupts();
168    tc->clearArchRegs();
169    ArmFault::invoke(tc, inst);
170}
171
172#else
173
174void
175UndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
176{
177    // If the mnemonic isn't defined this has to be an unknown instruction.
178    assert(unknown || mnemonic != NULL);
179    if (disabled) {
180        panic("Attempted to execute disabled instruction "
181                "'%s' (inst 0x%08x)", mnemonic, machInst);
182    } else if (unknown) {
183        panic("Attempted to execute unknown instruction (inst 0x%08x)",
184              machInst);
185    } else {
186        panic("Attempted to execute unimplemented instruction "
187                "'%s' (inst 0x%08x)", mnemonic, machInst);
188    }
189}
190
191void
192SupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
193{
194    // As of now, there isn't a 32 bit thumb version of this instruction.
195    assert(!machInst.bigThumb);
196    uint32_t callNum;
197    callNum = tc->readIntReg(INTREG_R7);
198    tc->syscall(callNum);
199
200    // Advance the PC since that won't happen automatically.
201    PCState pc = tc->pcState();
202    assert(inst);
203    inst->advancePC(pc);
204    tc->pcState(pc);
205}
206
207#endif // FULL_SYSTEM
208
209template<class T>
210void
211AbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
212{
213    ArmFaultVals<T>::invoke(tc, inst);
214    FSR fsr = 0;
215    fsr.fsLow = bits(status, 3, 0);
216    fsr.fsHigh = bits(status, 4);
217    fsr.domain = domain;
218    fsr.wnr = (write ? 1 : 0);
219    fsr.ext = 0;
220    tc->setMiscReg(T::FsrIndex, fsr);
221    tc->setMiscReg(T::FarIndex, faultAddr);
222
223    DPRINTF(Faults, "Abort Fault fsr=%#x faultAddr=%#x\n", fsr, faultAddr);
224}
225
226void
227FlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
228    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
229
230    // Set the PC to the next instruction of the faulting instruction.
231    // Net effect is simply squashing all instructions behind and
232    // start refetching from the next instruction.
233    PCState pc = tc->pcState();
234    assert(inst);
235    inst->advancePC(pc);
236    tc->pcState(pc);
237}
238
239void
240ReExec::invoke(ThreadContext *tc, StaticInstPtr inst) {
241    DPRINTF(Faults, "Invoking ReExec Fault\n");
242
243    // Set the PC to then the faulting instruction.
244    // Net effect is simply squashing all instructions including this
245    // instruction and refetching/rexecuting current instruction
246    PCState pc = tc->pcState();
247    tc->pcState(pc);
248}
249
250template void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
251                                                StaticInstPtr inst);
252template void AbortFault<DataAbort>::invoke(ThreadContext *tc,
253                                            StaticInstPtr inst);
254
255// return via SUBS pc, lr, xxx; rfe, movs, ldm
256
257} // namespace ArmISA
258