faults.cc revision 13396
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 *          Giacomo Gabrielli
44 *          Thomas Grocutt
45 */
46
47#include "arch/arm/faults.hh"
48
49#include "arch/arm/insts/static_inst.hh"
50#include "arch/arm/system.hh"
51#include "arch/arm/utility.hh"
52#include "base/compiler.hh"
53#include "base/trace.hh"
54#include "cpu/base.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Faults.hh"
57#include "sim/full_system.hh"
58
59namespace ArmISA
60{
61
62uint8_t ArmFault::shortDescFaultSources[] = {
63    0x01,  // AlignmentFault
64    0x04,  // InstructionCacheMaintenance
65    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66    0x0c,  // SynchExtAbtOnTranslTableWalkL1
67    0x0e,  // SynchExtAbtOnTranslTableWalkL2
68    0xff,  // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70    0x1c,  // SynchPtyErrOnTranslTableWalkL1
71    0x1e,  // SynchPtyErrOnTranslTableWalkL2
72    0xff,  // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73    0xff,  // TranslationL0 (INVALID)
74    0x05,  // TranslationL1
75    0x07,  // TranslationL2
76    0xff,  // TranslationL3 (INVALID)
77    0xff,  // AccessFlagL0 (INVALID)
78    0x03,  // AccessFlagL1
79    0x06,  // AccessFlagL2
80    0xff,  // AccessFlagL3 (INVALID)
81    0xff,  // DomainL0 (INVALID)
82    0x09,  // DomainL1
83    0x0b,  // DomainL2
84    0xff,  // DomainL3 (INVALID)
85    0xff,  // PermissionL0 (INVALID)
86    0x0d,  // PermissionL1
87    0x0f,  // PermissionL2
88    0xff,  // PermissionL3 (INVALID)
89    0x02,  // DebugEvent
90    0x08,  // SynchronousExternalAbort
91    0x10,  // TLBConflictAbort
92    0x19,  // SynchPtyErrOnMemoryAccess
93    0x16,  // AsynchronousExternalAbort
94    0x18,  // AsynchPtyErrOnMemoryAccess
95    0xff,  // AddressSizeL0 (INVALID)
96    0xff,  // AddressSizeL1 (INVALID)
97    0xff,  // AddressSizeL2 (INVALID)
98    0xff,  // AddressSizeL3 (INVALID)
99    0x40,  // PrefetchTLBMiss
100    0x80   // PrefetchUncacheable
101};
102
103static_assert(sizeof(ArmFault::shortDescFaultSources) ==
104              ArmFault::NumFaultSources,
105              "Invalid size of ArmFault::shortDescFaultSources[]");
106
107uint8_t ArmFault::longDescFaultSources[] = {
108    0x21,  // AlignmentFault
109    0xff,  // InstructionCacheMaintenance (INVALID)
110    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111    0x15,  // SynchExtAbtOnTranslTableWalkL1
112    0x16,  // SynchExtAbtOnTranslTableWalkL2
113    0x17,  // SynchExtAbtOnTranslTableWalkL3
114    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115    0x1d,  // SynchPtyErrOnTranslTableWalkL1
116    0x1e,  // SynchPtyErrOnTranslTableWalkL2
117    0x1f,  // SynchPtyErrOnTranslTableWalkL3
118    0xff,  // TranslationL0 (INVALID)
119    0x05,  // TranslationL1
120    0x06,  // TranslationL2
121    0x07,  // TranslationL3
122    0xff,  // AccessFlagL0 (INVALID)
123    0x09,  // AccessFlagL1
124    0x0a,  // AccessFlagL2
125    0x0b,  // AccessFlagL3
126    0xff,  // DomainL0 (INVALID)
127    0x3d,  // DomainL1
128    0x3e,  // DomainL2
129    0xff,  // DomainL3 (RESERVED)
130    0xff,  // PermissionL0 (INVALID)
131    0x0d,  // PermissionL1
132    0x0e,  // PermissionL2
133    0x0f,  // PermissionL3
134    0x22,  // DebugEvent
135    0x10,  // SynchronousExternalAbort
136    0x30,  // TLBConflictAbort
137    0x18,  // SynchPtyErrOnMemoryAccess
138    0x11,  // AsynchronousExternalAbort
139    0x19,  // AsynchPtyErrOnMemoryAccess
140    0xff,  // AddressSizeL0 (INVALID)
141    0xff,  // AddressSizeL1 (INVALID)
142    0xff,  // AddressSizeL2 (INVALID)
143    0xff,  // AddressSizeL3 (INVALID)
144    0x40,  // PrefetchTLBMiss
145    0x80   // PrefetchUncacheable
146};
147
148static_assert(sizeof(ArmFault::longDescFaultSources) ==
149              ArmFault::NumFaultSources,
150              "Invalid size of ArmFault::longDescFaultSources[]");
151
152uint8_t ArmFault::aarch64FaultSources[] = {
153    0x21,  // AlignmentFault
154    0xff,  // InstructionCacheMaintenance (INVALID)
155    0x14,  // SynchExtAbtOnTranslTableWalkL0
156    0x15,  // SynchExtAbtOnTranslTableWalkL1
157    0x16,  // SynchExtAbtOnTranslTableWalkL2
158    0x17,  // SynchExtAbtOnTranslTableWalkL3
159    0x1c,  // SynchPtyErrOnTranslTableWalkL0
160    0x1d,  // SynchPtyErrOnTranslTableWalkL1
161    0x1e,  // SynchPtyErrOnTranslTableWalkL2
162    0x1f,  // SynchPtyErrOnTranslTableWalkL3
163    0x04,  // TranslationL0
164    0x05,  // TranslationL1
165    0x06,  // TranslationL2
166    0x07,  // TranslationL3
167    0x08,  // AccessFlagL0
168    0x09,  // AccessFlagL1
169    0x0a,  // AccessFlagL2
170    0x0b,  // AccessFlagL3
171    // @todo: Section & Page Domain Fault in AArch64?
172    0xff,  // DomainL0 (INVALID)
173    0xff,  // DomainL1 (INVALID)
174    0xff,  // DomainL2 (INVALID)
175    0xff,  // DomainL3 (INVALID)
176    0x0c,  // PermissionL0
177    0x0d,  // PermissionL1
178    0x0e,  // PermissionL2
179    0x0f,  // PermissionL3
180    0x22,  // DebugEvent
181    0x10,  // SynchronousExternalAbort
182    0x30,  // TLBConflictAbort
183    0x18,  // SynchPtyErrOnMemoryAccess
184    0xff,  // AsynchronousExternalAbort (INVALID)
185    0xff,  // AsynchPtyErrOnMemoryAccess (INVALID)
186    0x00,  // AddressSizeL0
187    0x01,  // AddressSizeL1
188    0x02,  // AddressSizeL2
189    0x03,  // AddressSizeL3
190    0x40,  // PrefetchTLBMiss
191    0x80   // PrefetchUncacheable
192};
193
194static_assert(sizeof(ArmFault::aarch64FaultSources) ==
195              ArmFault::NumFaultSources,
196              "Invalid size of ArmFault::aarch64FaultSources[]");
197
198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199//         {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200//         {A, F} disable, class, stat
201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals(
202    // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203    // location in AArch64)
204    "Reset",                 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
205    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
206);
207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals(
208    "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
209    4, 2, 0, 0, true,  false, false, EC_UNKNOWN
210);
211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals(
212    "Supervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
213    4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP
214);
215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals(
216    "Secure Monitor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
217    4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP
218);
219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals(
220    "Hypervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
221    4, 4, 4, 4, true,  false, false, EC_HVC
222);
223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals(
224    "Prefetch Abort",        0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
225    4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP
226);
227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals(
228    "Data Abort",            0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
229    8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP
230);
231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals(
232    "Virtual Data Abort",    0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
233    8, 8, 0, 0, true,  true,  false, EC_INVALID
234);
235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals(
236    // @todo: double check these values
237    "Hypervisor Trap",       0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
238    0, 0, 0, 0, false, false, false, EC_UNKNOWN
239);
240template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals(
241    "Secure Monitor Trap",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
242    4, 2, 0, 0, false, false, false, EC_UNKNOWN
243);
244template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals(
245    "IRQ",                   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
246    4, 4, 0, 0, false, true,  false, EC_UNKNOWN
247);
248template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals(
249    "Virtual IRQ",           0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
250    4, 4, 0, 0, false, true,  false, EC_INVALID
251);
252template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals(
253    "FIQ",                   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
254    4, 4, 0, 0, false, true,  true,  EC_UNKNOWN
255);
256template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals(
257    "Virtual FIQ",           0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
258    4, 4, 0, 0, false, true,  true,  EC_INVALID
259);
260template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals(
261    "Illegal Inst Set State Fault",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
262    4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
263);
264template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals(
265    // Some dummy values (SupervisorTrap is AArch64-only)
266    "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
267    0, 0, 0, 0, false, false, false, EC_UNKNOWN
268);
269template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals(
270    // Some dummy values (PCAlignmentFault is AArch64-only)
271    "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
272    0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
273);
274template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals(
275    // Some dummy values (SPAlignmentFault is AArch64-only)
276    "SP Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
277    0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
278);
279template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals(
280    // Some dummy values (SError is AArch64-only)
281    "SError",                0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
282    0, 0, 0, 0, false, true,  true,  EC_SERROR
283);
284template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals(
285    // Some dummy values (SoftwareBreakpoint is AArch64-only)
286    "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
287    0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT
288);
289template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals(
290    // Some dummy values
291    "ArmSev Flush",          0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
292    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
293);
294
295Addr
296ArmFault::getVector(ThreadContext *tc)
297{
298    Addr base;
299
300    // Check for invalid modes
301    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
302    assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
303    assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
304
305    switch (cpsr.mode)
306    {
307      case MODE_MON:
308        base = tc->readMiscReg(MISCREG_MVBAR);
309        break;
310      case MODE_HYP:
311        base = tc->readMiscReg(MISCREG_HVBAR);
312        break;
313      default:
314        SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
315        if (sctlr.v) {
316            base = HighVecs;
317        } else {
318            base = ArmSystem::haveSecurity(tc) ?
319                tc->readMiscReg(MISCREG_VBAR) : 0;
320        }
321        break;
322    }
323
324    return base + offset(tc);
325}
326
327Addr
328ArmFault::getVector64(ThreadContext *tc)
329{
330    Addr vbar;
331    switch (toEL) {
332      case EL3:
333        assert(ArmSystem::haveSecurity(tc));
334        vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
335        break;
336      case EL2:
337        assert(ArmSystem::haveVirtualization(tc));
338        vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
339        break;
340      case EL1:
341        vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
342        break;
343      default:
344        panic("Invalid target exception level");
345        break;
346    }
347    return vbar + offset64(tc);
348}
349
350MiscRegIndex
351ArmFault::getSyndromeReg64() const
352{
353    switch (toEL) {
354      case EL1:
355        return MISCREG_ESR_EL1;
356      case EL2:
357        return MISCREG_ESR_EL2;
358      case EL3:
359        return MISCREG_ESR_EL3;
360      default:
361        panic("Invalid exception level");
362        break;
363    }
364}
365
366MiscRegIndex
367ArmFault::getFaultAddrReg64() const
368{
369    switch (toEL) {
370      case EL1:
371        return MISCREG_FAR_EL1;
372      case EL2:
373        return MISCREG_FAR_EL2;
374      case EL3:
375        return MISCREG_FAR_EL3;
376      default:
377        panic("Invalid exception level");
378        break;
379    }
380}
381
382void
383ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
384{
385    uint32_t value;
386    uint32_t exc_class = (uint32_t) ec(tc);
387    uint32_t issVal = iss();
388
389    assert(!from64 || ArmSystem::highestELIs64(tc));
390
391    value = exc_class << 26;
392
393    // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
394    // 0x25) for which the ISS information is not valid (ARMv7).
395    // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
396    // valid it is treated as RES1.
397    if (to64) {
398        value |= 1 << 25;
399    } else if ((bits(exc_class, 5, 3) != 4) ||
400               (bits(exc_class, 2) && bits(issVal, 24))) {
401        if (!machInst.thumb || machInst.bigThumb)
402            value |= 1 << 25;
403    }
404    // Condition code valid for EC[5:4] nonzero
405    if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
406                    (bits(exc_class, 3, 0) != 0))) {
407        if (!machInst.thumb) {
408            uint32_t      cond;
409            ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
410            // If its on unconditional instruction report with a cond code of
411            // 0xE, ie the unconditional code
412            cond  = (condCode == COND_UC) ? COND_AL : condCode;
413            value |= cond << 20;
414            value |= 1    << 24;
415        }
416        value |= bits(issVal, 19, 0);
417    } else {
418        value |= issVal;
419    }
420    tc->setMiscReg(syndrome_reg, value);
421}
422
423void
424ArmFault::update(ThreadContext *tc)
425{
426    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
427
428    // Determine source exception level and mode
429    fromMode = (OperatingMode) (uint8_t) cpsr.mode;
430    fromEL = opModeToEL(fromMode);
431    if (opModeIs64(fromMode))
432        from64 = true;
433
434    // Determine target exception level (aarch64) or target execution
435    // mode (aarch32).
436    if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
437        toMode = MODE_MON;
438        toEL = EL3;
439    } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
440        toMode = MODE_HYP;
441        toEL = EL2;
442        hypRouted = true;
443    } else {
444        toMode = nextMode();
445        toEL = opModeToEL(toMode);
446    }
447
448    if (fromEL > toEL)
449        toEL = fromEL;
450
451    to64 = ELIs64(tc, toEL);
452
453    // The fault specific informations have been updated; it is
454    // now possible to use them inside the fault.
455    faultUpdated = true;
456}
457
458void
459ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
460{
461
462    // Update fault state informations, like the starting mode (aarch32)
463    // or EL (aarch64) and the ending mode or EL.
464    // From the update function we are also evaluating if the fault must
465    // be handled in AArch64 mode (to64).
466    update(tc);
467
468    if (to64) {
469        // Invoke exception handler in AArch64 state
470        invoke64(tc, inst);
471        return;
472    }
473
474    // ARMv7 (ARM ARM issue C B1.9)
475
476    bool have_security       = ArmSystem::haveSecurity(tc);
477
478    FaultBase::invoke(tc);
479    if (!FullSystem)
480        return;
481    countStat()++;
482
483    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
484    SCR scr = tc->readMiscReg(MISCREG_SCR);
485    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
486    saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
487    saved_cpsr.c = tc->readCCReg(CCREG_C);
488    saved_cpsr.v = tc->readCCReg(CCREG_V);
489    saved_cpsr.ge = tc->readCCReg(CCREG_GE);
490
491    Addr curPc M5_VAR_USED = tc->pcState().pc();
492    ITSTATE it = tc->pcState().itstate();
493    saved_cpsr.it2 = it.top6;
494    saved_cpsr.it1 = it.bottom2;
495
496    // if we have a valid instruction then use it to annotate this fault with
497    // extra information. This is used to generate the correct fault syndrome
498    // information
499    if (inst) {
500        ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
501        armInst->annotateFault(this);
502    }
503
504    // Ensure Secure state if initially in Monitor mode
505    if (have_security && saved_cpsr.mode == MODE_MON) {
506        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
507        if (scr.ns) {
508            scr.ns = 0;
509            tc->setMiscRegNoEffect(MISCREG_SCR, scr);
510        }
511    }
512
513    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
514    cpsr.mode = toMode;
515
516    // some bits are set differently if we have been routed to hyp mode
517    if (cpsr.mode == MODE_HYP) {
518        SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
519        cpsr.t = hsctlr.te;
520        cpsr.e = hsctlr.ee;
521        if (!scr.ea)  {cpsr.a = 1;}
522        if (!scr.fiq) {cpsr.f = 1;}
523        if (!scr.irq) {cpsr.i = 1;}
524    } else if (cpsr.mode == MODE_MON) {
525        // Special case handling when entering monitor mode
526        cpsr.t = sctlr.te;
527        cpsr.e = sctlr.ee;
528        cpsr.a = 1;
529        cpsr.f = 1;
530        cpsr.i = 1;
531    } else {
532        cpsr.t = sctlr.te;
533        cpsr.e = sctlr.ee;
534
535        // The *Disable functions are virtual and different per fault
536        cpsr.a = cpsr.a | abortDisable(tc);
537        cpsr.f = cpsr.f | fiqDisable(tc);
538        cpsr.i = 1;
539    }
540    cpsr.it1 = cpsr.it2 = 0;
541    cpsr.j = 0;
542    tc->setMiscReg(MISCREG_CPSR, cpsr);
543
544    // Make sure mailbox sets to one always
545    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
546
547    // Clear the exclusive monitor
548    tc->setMiscReg(MISCREG_LOCKFLAG, 0);
549
550    if (cpsr.mode == MODE_HYP) {
551        tc->setMiscReg(MISCREG_ELR_HYP, curPc +
552                (saved_cpsr.t ? thumbPcOffset(true)  : armPcOffset(true)));
553    } else {
554        tc->setIntReg(INTREG_LR, curPc +
555                (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
556    }
557
558    switch (cpsr.mode) {
559      case MODE_FIQ:
560        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
561        break;
562      case MODE_IRQ:
563        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
564        break;
565      case MODE_SVC:
566        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
567        break;
568      case MODE_MON:
569        assert(have_security);
570        tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
571        break;
572      case MODE_ABORT:
573        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
574        break;
575      case MODE_UNDEFINED:
576        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
577        if (ec(tc) != EC_UNKNOWN)
578            setSyndrome(tc, MISCREG_HSR);
579        break;
580      case MODE_HYP:
581        assert(ArmSystem::haveVirtualization(tc));
582        tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
583        setSyndrome(tc, MISCREG_HSR);
584        break;
585      default:
586        panic("unknown Mode\n");
587    }
588
589    Addr newPc = getVector(tc);
590    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
591            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
592    PCState pc(newPc);
593    pc.thumb(cpsr.t);
594    pc.nextThumb(pc.thumb());
595    pc.jazelle(cpsr.j);
596    pc.nextJazelle(pc.jazelle());
597    pc.aarch64(!cpsr.width);
598    pc.nextAArch64(!cpsr.width);
599    pc.illegalExec(false);
600    tc->pcState(pc);
601}
602
603void
604ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
605{
606    // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
607    MiscRegIndex elr_idx, spsr_idx;
608    switch (toEL) {
609      case EL1:
610        elr_idx = MISCREG_ELR_EL1;
611        spsr_idx = MISCREG_SPSR_EL1;
612        break;
613      case EL2:
614        assert(ArmSystem::haveVirtualization(tc));
615        elr_idx = MISCREG_ELR_EL2;
616        spsr_idx = MISCREG_SPSR_EL2;
617        break;
618      case EL3:
619        assert(ArmSystem::haveSecurity(tc));
620        elr_idx = MISCREG_ELR_EL3;
621        spsr_idx = MISCREG_SPSR_EL3;
622        break;
623      default:
624        panic("Invalid target exception level");
625        break;
626    }
627
628    // Save process state into SPSR_ELx
629    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
630    CPSR spsr = cpsr;
631    spsr.nz = tc->readCCReg(CCREG_NZ);
632    spsr.c = tc->readCCReg(CCREG_C);
633    spsr.v = tc->readCCReg(CCREG_V);
634    if (from64) {
635        // Force some bitfields to 0
636        spsr.q = 0;
637        spsr.it1 = 0;
638        spsr.j = 0;
639        spsr.res0_23_22 = 0;
640        spsr.ge = 0;
641        spsr.it2 = 0;
642        spsr.t = 0;
643    } else {
644        spsr.ge = tc->readCCReg(CCREG_GE);
645        ITSTATE it = tc->pcState().itstate();
646        spsr.it2 = it.top6;
647        spsr.it1 = it.bottom2;
648        // Force some bitfields to 0
649        spsr.res0_23_22 = 0;
650        spsr.ss = 0;
651    }
652    tc->setMiscReg(spsr_idx, spsr);
653
654    // Save preferred return address into ELR_ELx
655    Addr curr_pc = tc->pcState().pc();
656    Addr ret_addr = curr_pc;
657    if (from64)
658        ret_addr += armPcElrOffset();
659    else
660        ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
661    tc->setMiscReg(elr_idx, ret_addr);
662
663    Addr vec_address = getVector64(tc);
664
665    // Update process state
666    OperatingMode64 mode = 0;
667    mode.spX = 1;
668    mode.el = toEL;
669    mode.width = 0;
670    cpsr.mode = mode;
671    cpsr.daif = 0xf;
672    cpsr.il = 0;
673    cpsr.ss = 0;
674    tc->setMiscReg(MISCREG_CPSR, cpsr);
675
676    // Set PC to start of exception handler
677    Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
678    DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
679            "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
680    PCState pc(new_pc);
681    pc.aarch64(!cpsr.width);
682    pc.nextAArch64(!cpsr.width);
683    pc.illegalExec(false);
684    tc->pcState(pc);
685
686    // If we have a valid instruction then use it to annotate this fault with
687    // extra information. This is used to generate the correct fault syndrome
688    // information
689    if (inst)
690        static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
691    // Save exception syndrome
692    if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
693        setSyndrome(tc, getSyndromeReg64());
694}
695
696Addr
697Reset::getVector(ThreadContext *tc)
698{
699    Addr base;
700
701    // Check for invalid modes
702    CPSR M5_VAR_USED cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
703    assert(ArmSystem::haveSecurity(tc) || cpsr.mode != MODE_MON);
704    assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
705
706    // RVBAR is aliased (implemented as) MVBAR in gem5, since the two
707    // are mutually exclusive; there is no need to check here for
708    // which register to use since they hold the same value
709    base = tc->readMiscReg(MISCREG_MVBAR);
710
711    return base + offset(tc);
712}
713
714void
715Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
716{
717    if (FullSystem) {
718        tc->getCpuPtr()->clearInterrupts(tc->threadId());
719        tc->clearArchRegs();
720    }
721    if (!ArmSystem::highestELIs64(tc)) {
722        ArmFault::invoke(tc, inst);
723        tc->setMiscReg(MISCREG_VMPIDR,
724                       getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
725
726        // Unless we have SMC code to get us there, boot in HYP!
727        if (ArmSystem::haveVirtualization(tc) &&
728            !ArmSystem::haveSecurity(tc)) {
729            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
730            cpsr.mode = MODE_HYP;
731            tc->setMiscReg(MISCREG_CPSR, cpsr);
732        }
733    } else {
734        // Advance the PC to the IMPLEMENTATION DEFINED reset value
735        PCState pc = ArmSystem::resetAddr(tc);
736        pc.aarch64(true);
737        pc.nextAArch64(true);
738        tc->pcState(pc);
739    }
740}
741
742void
743UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
744{
745    if (FullSystem) {
746        ArmFault::invoke(tc, inst);
747        return;
748    }
749
750    // If the mnemonic isn't defined this has to be an unknown instruction.
751    assert(unknown || mnemonic != NULL);
752    if (disabled) {
753        panic("Attempted to execute disabled instruction "
754                "'%s' (inst 0x%08x)", mnemonic, machInst);
755    } else if (unknown) {
756        panic("Attempted to execute unknown instruction (inst 0x%08x)",
757              machInst);
758    } else {
759        panic("Attempted to execute unimplemented instruction "
760                "'%s' (inst 0x%08x)", mnemonic, machInst);
761    }
762}
763
764bool
765UndefinedInstruction::routeToHyp(ThreadContext *tc) const
766{
767    bool toHyp;
768
769    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
770    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
771    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
772
773    // if in Hyp mode then stay in Hyp mode
774    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
775    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
776    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
777    return toHyp;
778}
779
780uint32_t
781UndefinedInstruction::iss() const
782{
783
784    // If UndefinedInstruction is routed to hypervisor, iss field is 0.
785    if (hypRouted) {
786        return 0;
787    }
788
789    if (overrideEc == EC_INVALID)
790        return issRaw;
791
792    uint32_t new_iss = 0;
793    uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
794
795    dir = bits(machInst, 21, 21);
796    op0 = bits(machInst, 20, 19);
797    op1 = bits(machInst, 18, 16);
798    CRn = bits(machInst, 15, 12);
799    CRm = bits(machInst, 11, 8);
800    op2 = bits(machInst, 7, 5);
801    Rt = bits(machInst, 4, 0);
802
803    new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
804            Rt << 5 | CRm << 1 | dir;
805
806    return new_iss;
807}
808
809void
810SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
811{
812    if (FullSystem) {
813        ArmFault::invoke(tc, inst);
814        return;
815    }
816
817    // As of now, there isn't a 32 bit thumb version of this instruction.
818    assert(!machInst.bigThumb);
819    uint32_t callNum;
820    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
821    OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
822    if (opModeIs64(mode))
823        callNum = tc->readIntReg(INTREG_X8);
824    else
825        callNum = tc->readIntReg(INTREG_R7);
826    Fault fault;
827    tc->syscall(callNum, &fault);
828
829    // Advance the PC since that won't happen automatically.
830    PCState pc = tc->pcState();
831    assert(inst);
832    inst->advancePC(pc);
833    tc->pcState(pc);
834}
835
836bool
837SupervisorCall::routeToHyp(ThreadContext *tc) const
838{
839    bool toHyp;
840
841    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
842    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
843    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
844
845    // if in Hyp mode then stay in Hyp mode
846    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
847    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
848    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
849    return toHyp;
850}
851
852ExceptionClass
853SupervisorCall::ec(ThreadContext *tc) const
854{
855    return (overrideEc != EC_INVALID) ? overrideEc :
856        (from64 ? EC_SVC_64 : vals.ec);
857}
858
859uint32_t
860SupervisorCall::iss() const
861{
862    // Even if we have a 24 bit imm from an arm32 instruction then we only use
863    // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
864    return issRaw & 0xFFFF;
865}
866
867uint32_t
868SecureMonitorCall::iss() const
869{
870    if (from64)
871        return bits(machInst, 20, 5);
872    return 0;
873}
874
875ExceptionClass
876UndefinedInstruction::ec(ThreadContext *tc) const
877{
878    // If UndefinedInstruction is routed to hypervisor,
879    // HSR.EC field is 0.
880    if (hypRouted)
881        return EC_UNKNOWN;
882    else
883        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
884}
885
886
887HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
888        ArmFaultVals<HypervisorCall>(_machInst, _imm)
889{}
890
891ExceptionClass
892HypervisorCall::ec(ThreadContext *tc) const
893{
894    return from64 ? EC_HVC_64 : vals.ec;
895}
896
897ExceptionClass
898HypervisorTrap::ec(ThreadContext *tc) const
899{
900    return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
901}
902
903template<class T>
904FaultOffset
905ArmFaultVals<T>::offset(ThreadContext *tc)
906{
907    bool isHypTrap = false;
908
909    // Normally we just use the exception vector from the table at the top if
910    // this file, however if this exception has caused a transition to hype
911    // mode, and its an exception type that would only do this if it has been
912    // trapped then we use the hyp trap vector instead of the normal vector
913    if (vals.hypTrappable) {
914        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
915        if (cpsr.mode == MODE_HYP) {
916            CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
917            isHypTrap = spsr.mode != MODE_HYP;
918        }
919    }
920    return isHypTrap ? 0x14 : vals.offset;
921}
922
923template<class T>
924FaultOffset
925ArmFaultVals<T>::offset64(ThreadContext *tc)
926{
927    if (toEL == fromEL) {
928        if (opModeIsT(fromMode))
929            return vals.currELTOffset;
930        return vals.currELHOffset;
931    } else {
932        bool lower_32 = false;
933        if (toEL == EL3) {
934            if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
935                lower_32 = ELIs32(tc, EL2);
936            else
937                lower_32 = ELIs32(tc, EL1);
938        } else {
939            lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
940        }
941
942        if (lower_32)
943            return vals.lowerEL32Offset;
944        return vals.lowerEL64Offset;
945    }
946}
947
948// void
949// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
950// {
951//     ESR esr = 0;
952//     esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
953//     esr.il = !machInst.thumb;
954//     if (machInst.aarch64)
955//         esr.imm16 = bits(machInst.instBits, 20, 5);
956//     else if (machInst.thumb)
957//         esr.imm16 = bits(machInst.instBits, 7, 0);
958//     else
959//         esr.imm16 = bits(machInst.instBits, 15, 0);
960//     tc->setMiscReg(esr_idx, esr);
961// }
962
963void
964SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
965{
966    if (FullSystem) {
967        ArmFault::invoke(tc, inst);
968        return;
969    }
970}
971
972ExceptionClass
973SecureMonitorCall::ec(ThreadContext *tc) const
974{
975    return (from64 ? EC_SMC_64 : vals.ec);
976}
977
978bool
979SupervisorTrap::routeToHyp(ThreadContext *tc) const
980{
981    bool toHyp = false;
982
983    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
984    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
985    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
986
987    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
988    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
989    return toHyp;
990}
991
992uint32_t
993SupervisorTrap::iss() const
994{
995    // If SupervisorTrap is routed to hypervisor, iss field is 0.
996    if (hypRouted) {
997        return 0;
998    }
999    return issRaw;
1000}
1001
1002ExceptionClass
1003SupervisorTrap::ec(ThreadContext *tc) const
1004{
1005    if (hypRouted)
1006        return EC_UNKNOWN;
1007    else
1008        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
1009}
1010
1011ExceptionClass
1012SecureMonitorTrap::ec(ThreadContext *tc) const
1013{
1014    return (overrideEc != EC_INVALID) ? overrideEc :
1015        (from64 ? EC_SMC_64 : vals.ec);
1016}
1017
1018template<class T>
1019void
1020AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1021{
1022    if (tranMethod == ArmFault::UnknownTran) {
1023        tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1024                                             : ArmFault::VmsaTran;
1025
1026        if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1027            // See ARM ARM B3-1416
1028            bool override_LPAE = false;
1029            TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1030            TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
1031            if (ttbcr_s.eae) {
1032                override_LPAE = true;
1033            } else {
1034                // Unimplemented code option, not seen in testing.  May need
1035                // extension according to the manual exceprt above.
1036                DPRINTF(Faults, "Warning: Incomplete translation method "
1037                        "override detected.\n");
1038            }
1039            if (override_LPAE)
1040                tranMethod = ArmFault::LpaeTran;
1041        }
1042    }
1043
1044    if (source == ArmFault::AsynchronousExternalAbort) {
1045        tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1046    }
1047    // Get effective fault source encoding
1048    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1049
1050    // source must be determined BEFORE invoking generic routines which will
1051    // try to set hsr etc. and are based upon source!
1052    ArmFaultVals<T>::invoke(tc, inst);
1053
1054    if (!this->to64) {  // AArch32
1055        FSR  fsr  = getFsr(tc);
1056        if (cpsr.mode == MODE_HYP) {
1057            tc->setMiscReg(T::HFarIndex, faultAddr);
1058        } else if (stage2) {
1059            tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1060            tc->setMiscReg(T::HFarIndex,  OVAddr);
1061        } else {
1062            tc->setMiscReg(T::FsrIndex, fsr);
1063            tc->setMiscReg(T::FarIndex, faultAddr);
1064        }
1065        DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1066                "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1067    } else {  // AArch64
1068        // Set the FAR register.  Nothing else to do if we are in AArch64 state
1069        // because the syndrome register has already been set inside invoke64()
1070        if (stage2) {
1071            // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1072            // and FAR_EL2 to the Original VA
1073            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
1074            tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1075
1076            DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1077                    OVAddr, faultAddr);
1078        } else {
1079            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1080        }
1081    }
1082}
1083
1084template<class T>
1085void
1086AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
1087{
1088    srcEncoded = getFaultStatusCode(tc);
1089    if (srcEncoded == ArmFault::FaultSourceInvalid) {
1090        panic("Invalid fault source\n");
1091    }
1092    ArmFault::setSyndrome(tc, syndrome_reg);
1093}
1094
1095template<class T>
1096uint8_t
1097AbortFault<T>::getFaultStatusCode(ThreadContext *tc) const
1098{
1099
1100    panic_if(!this->faultUpdated,
1101             "Trying to use un-updated ArmFault internal variables\n");
1102
1103    uint8_t fsc = 0;
1104
1105    if (!this->to64) {
1106        // AArch32
1107        assert(tranMethod != ArmFault::UnknownTran);
1108        if (tranMethod == ArmFault::LpaeTran) {
1109            fsc = ArmFault::longDescFaultSources[source];
1110        } else {
1111            fsc = ArmFault::shortDescFaultSources[source];
1112        }
1113    } else {
1114        // AArch64
1115        fsc = ArmFault::aarch64FaultSources[source];
1116    }
1117
1118    return fsc;
1119}
1120
1121template<class T>
1122FSR
1123AbortFault<T>::getFsr(ThreadContext *tc) const
1124{
1125    FSR fsr = 0;
1126
1127    auto fsc = getFaultStatusCode(tc);
1128
1129    // AArch32
1130    assert(tranMethod != ArmFault::UnknownTran);
1131    if (tranMethod == ArmFault::LpaeTran) {
1132        fsr.status = fsc;
1133        fsr.lpae   = 1;
1134    } else {
1135        fsr.fsLow  = bits(fsc, 3, 0);
1136        fsr.fsHigh = bits(fsc, 4);
1137        fsr.domain = static_cast<uint8_t>(domain);
1138    }
1139
1140    fsr.wnr = (write ? 1 : 0);
1141    fsr.ext = 0;
1142
1143    return fsr;
1144}
1145
1146template<class T>
1147bool
1148AbortFault<T>::abortDisable(ThreadContext *tc)
1149{
1150    if (ArmSystem::haveSecurity(tc)) {
1151        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1152        return (!scr.ns || scr.aw);
1153    }
1154    return true;
1155}
1156
1157template<class T>
1158void
1159AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val)
1160{
1161    switch (id)
1162    {
1163      case ArmFault::S1PTW:
1164        s1ptw = val;
1165        break;
1166      case ArmFault::OVA:
1167        OVAddr = val;
1168        break;
1169
1170      // Just ignore unknown ID's
1171      default:
1172        break;
1173    }
1174}
1175
1176template<class T>
1177uint32_t
1178AbortFault<T>::iss() const
1179{
1180    uint32_t val;
1181
1182    val  = srcEncoded & 0x3F;
1183    val |= write << 6;
1184    val |= s1ptw << 7;
1185    return (val);
1186}
1187
1188template<class T>
1189bool
1190AbortFault<T>::isMMUFault() const
1191{
1192    // NOTE: Not relying on LL information being aligned to lowest bits here
1193    return
1194         (source == ArmFault::AlignmentFault)     ||
1195        ((source >= ArmFault::TranslationLL) &&
1196         (source <  ArmFault::TranslationLL + 4)) ||
1197        ((source >= ArmFault::AccessFlagLL) &&
1198         (source <  ArmFault::AccessFlagLL + 4))  ||
1199        ((source >= ArmFault::DomainLL) &&
1200         (source <  ArmFault::DomainLL + 4))      ||
1201        ((source >= ArmFault::PermissionLL) &&
1202         (source <  ArmFault::PermissionLL + 4));
1203}
1204
1205ExceptionClass
1206PrefetchAbort::ec(ThreadContext *tc) const
1207{
1208    if (to64) {
1209        // AArch64
1210        if (toEL == fromEL)
1211            return EC_PREFETCH_ABORT_CURR_EL;
1212        else
1213            return EC_PREFETCH_ABORT_LOWER_EL;
1214    } else {
1215        // AArch32
1216        // Abort faults have different EC codes depending on whether
1217        // the fault originated within HYP mode, or not. So override
1218        // the method and add the extra adjustment of the EC value.
1219
1220        ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec;
1221
1222        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1223        if (spsr.mode == MODE_HYP) {
1224            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1225        }
1226        return ec;
1227    }
1228}
1229
1230bool
1231PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1232{
1233    SCR scr = 0;
1234    if (from64)
1235        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1236    else
1237        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1238
1239    return scr.ea && !isMMUFault();
1240}
1241
1242bool
1243PrefetchAbort::routeToHyp(ThreadContext *tc) const
1244{
1245    bool toHyp;
1246
1247    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1248    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1249    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1250    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1251
1252    // if in Hyp mode then stay in Hyp mode
1253    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1254    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1255    toHyp |= (stage2 ||
1256                ( (source ==               DebugEvent) && hdcr.tde && (cpsr.mode !=  MODE_HYP)) ||
1257                ( (source == SynchronousExternalAbort) && hcr.tge  && (cpsr.mode == MODE_USER))
1258             ) && !inSecureState(tc);
1259    return toHyp;
1260}
1261
1262ExceptionClass
1263DataAbort::ec(ThreadContext *tc) const
1264{
1265    if (to64) {
1266        // AArch64
1267        if (source == ArmFault::AsynchronousExternalAbort) {
1268            panic("Asynchronous External Abort should be handled with "
1269                    "SystemErrors (SErrors)!");
1270        }
1271        if (toEL == fromEL)
1272            return EC_DATA_ABORT_CURR_EL;
1273        else
1274            return EC_DATA_ABORT_LOWER_EL;
1275    } else {
1276        // AArch32
1277        // Abort faults have different EC codes depending on whether
1278        // the fault originated within HYP mode, or not. So override
1279        // the method and add the extra adjustment of the EC value.
1280
1281        ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec;
1282
1283        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1284        if (spsr.mode == MODE_HYP) {
1285            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1286        }
1287        return ec;
1288    }
1289}
1290
1291bool
1292DataAbort::routeToMonitor(ThreadContext *tc) const
1293{
1294    SCR scr = 0;
1295    if (from64)
1296        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1297    else
1298        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1299
1300    return scr.ea && !isMMUFault();
1301}
1302
1303bool
1304DataAbort::routeToHyp(ThreadContext *tc) const
1305{
1306    bool toHyp;
1307
1308    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1309    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1310    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1311    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1312
1313    // if in Hyp mode then stay in Hyp mode
1314    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1315    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1316    toHyp |= (stage2 ||
1317                ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1318                                               ((source == DebugEvent) && hdcr.tde) )
1319                ) ||
1320                ( (cpsr.mode == MODE_USER) && hcr.tge &&
1321                  ((source == AlignmentFault)            ||
1322                   (source == SynchronousExternalAbort))
1323                )
1324             ) && !inSecureState(tc);
1325    return toHyp;
1326}
1327
1328uint32_t
1329DataAbort::iss() const
1330{
1331    uint32_t val;
1332
1333    // Add on the data abort specific fields to the generic abort ISS value
1334    val  = AbortFault<DataAbort>::iss();
1335    // ISS is valid if not caused by a stage 1 page table walk, and when taken
1336    // to AArch64 only when directed to EL2
1337    if (!s1ptw && (!to64 || toEL == EL2)) {
1338        val |= isv << 24;
1339        if (isv) {
1340            val |= sas << 22;
1341            val |= sse << 21;
1342            val |= srt << 16;
1343            // AArch64 only. These assignments are safe on AArch32 as well
1344            // because these vars are initialized to false
1345            val |= sf << 15;
1346            val |= ar << 14;
1347        }
1348    }
1349    return (val);
1350}
1351
1352void
1353DataAbort::annotate(AnnotationIDs id, uint64_t val)
1354{
1355    AbortFault<DataAbort>::annotate(id, val);
1356    switch (id)
1357    {
1358      case SAS:
1359        isv = true;
1360        sas = val;
1361        break;
1362      case SSE:
1363        isv = true;
1364        sse = val;
1365        break;
1366      case SRT:
1367        isv = true;
1368        srt = val;
1369        break;
1370      case SF:
1371        isv = true;
1372        sf  = val;
1373        break;
1374      case AR:
1375        isv = true;
1376        ar  = val;
1377        break;
1378      // Just ignore unknown ID's
1379      default:
1380        break;
1381    }
1382}
1383
1384void
1385VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1386{
1387    AbortFault<VirtualDataAbort>::invoke(tc, inst);
1388    HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1389    hcr.va = 0;
1390    tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1391}
1392
1393bool
1394Interrupt::routeToMonitor(ThreadContext *tc) const
1395{
1396    assert(ArmSystem::haveSecurity(tc));
1397    SCR scr = 0;
1398    if (from64)
1399        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1400    else
1401        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1402    return scr.irq;
1403}
1404
1405bool
1406Interrupt::routeToHyp(ThreadContext *tc) const
1407{
1408    bool toHyp;
1409
1410    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1411    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1412    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1413    // Determine whether IRQs are routed to Hyp mode.
1414    toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
1415            (cpsr.mode == MODE_HYP);
1416    return toHyp;
1417}
1418
1419bool
1420Interrupt::abortDisable(ThreadContext *tc)
1421{
1422    if (ArmSystem::haveSecurity(tc)) {
1423        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1424        return (!scr.ns || scr.aw);
1425    }
1426    return true;
1427}
1428
1429VirtualInterrupt::VirtualInterrupt()
1430{}
1431
1432bool
1433FastInterrupt::routeToMonitor(ThreadContext *tc) const
1434{
1435    assert(ArmSystem::haveSecurity(tc));
1436    SCR scr = 0;
1437    if (from64)
1438        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1439    else
1440        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1441    return scr.fiq;
1442}
1443
1444bool
1445FastInterrupt::routeToHyp(ThreadContext *tc) const
1446{
1447    bool toHyp;
1448
1449    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1450    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1451    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1452    // Determine whether IRQs are routed to Hyp mode.
1453    toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
1454            (cpsr.mode == MODE_HYP);
1455    return toHyp;
1456}
1457
1458bool
1459FastInterrupt::abortDisable(ThreadContext *tc)
1460{
1461    if (ArmSystem::haveSecurity(tc)) {
1462        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1463        return (!scr.ns || scr.aw);
1464    }
1465    return true;
1466}
1467
1468bool
1469FastInterrupt::fiqDisable(ThreadContext *tc)
1470{
1471    if (ArmSystem::haveVirtualization(tc)) {
1472        return true;
1473    } else if (ArmSystem::haveSecurity(tc)) {
1474        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1475        return (!scr.ns || scr.fw);
1476    }
1477    return true;
1478}
1479
1480VirtualFastInterrupt::VirtualFastInterrupt()
1481{}
1482
1483void
1484PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1485{
1486    ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1487    assert(from64);
1488    // Set the FAR
1489    tc->setMiscReg(getFaultAddrReg64(), faultPC);
1490}
1491
1492bool
1493PCAlignmentFault::routeToHyp(ThreadContext *tc) const
1494{
1495    bool toHyp = false;
1496
1497    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1498    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1499    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1500
1501    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
1502    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
1503    return toHyp;
1504}
1505
1506SPAlignmentFault::SPAlignmentFault()
1507{}
1508
1509SystemError::SystemError()
1510{}
1511
1512void
1513SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1514{
1515    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1516    ArmFault::invoke(tc, inst);
1517}
1518
1519bool
1520SystemError::routeToMonitor(ThreadContext *tc) const
1521{
1522    assert(ArmSystem::haveSecurity(tc));
1523    assert(from64);
1524    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1525    return scr.ea;
1526}
1527
1528bool
1529SystemError::routeToHyp(ThreadContext *tc) const
1530{
1531    bool toHyp;
1532    assert(from64);
1533
1534    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1535    HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1536
1537    toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
1538            (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
1539    return toHyp;
1540}
1541
1542
1543SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
1544    : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1545{}
1546
1547bool
1548SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1549{
1550    const bool have_el2 = ArmSystem::haveVirtualization(tc);
1551
1552    const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1553    const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1554
1555    return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1556        (hcr.tge || mdcr.tde);
1557}
1558
1559ExceptionClass
1560SoftwareBreakpoint::ec(ThreadContext *tc) const
1561{
1562    return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec;
1563}
1564
1565void
1566ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1567    DPRINTF(Faults, "Invoking ArmSev Fault\n");
1568    if (!FullSystem)
1569        return;
1570
1571    // Set sev_mailbox to 1, clear the pending interrupt from remote
1572    // SEV execution and let pipeline continue as pcState is still
1573    // valid.
1574    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1575    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1576}
1577
1578// Instantiate all the templates to make the linker happy
1579template class ArmFaultVals<Reset>;
1580template class ArmFaultVals<UndefinedInstruction>;
1581template class ArmFaultVals<SupervisorCall>;
1582template class ArmFaultVals<SecureMonitorCall>;
1583template class ArmFaultVals<HypervisorCall>;
1584template class ArmFaultVals<PrefetchAbort>;
1585template class ArmFaultVals<DataAbort>;
1586template class ArmFaultVals<VirtualDataAbort>;
1587template class ArmFaultVals<HypervisorTrap>;
1588template class ArmFaultVals<Interrupt>;
1589template class ArmFaultVals<VirtualInterrupt>;
1590template class ArmFaultVals<FastInterrupt>;
1591template class ArmFaultVals<VirtualFastInterrupt>;
1592template class ArmFaultVals<SupervisorTrap>;
1593template class ArmFaultVals<SecureMonitorTrap>;
1594template class ArmFaultVals<PCAlignmentFault>;
1595template class ArmFaultVals<SPAlignmentFault>;
1596template class ArmFaultVals<SystemError>;
1597template class ArmFaultVals<SoftwareBreakpoint>;
1598template class ArmFaultVals<ArmSev>;
1599template class AbortFault<PrefetchAbort>;
1600template class AbortFault<DataAbort>;
1601template class AbortFault<VirtualDataAbort>;
1602
1603
1604IllegalInstSetStateFault::IllegalInstSetStateFault()
1605{}
1606
1607
1608} // namespace ArmISA
1609