faults.cc revision 12732
1/* 2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 * Giacomo Gabrielli 44 * Thomas Grocutt 45 */ 46 47#include "arch/arm/faults.hh" 48 49#include "arch/arm/insts/static_inst.hh" 50#include "arch/arm/system.hh" 51#include "arch/arm/utility.hh" 52#include "base/compiler.hh" 53#include "base/trace.hh" 54#include "cpu/base.hh" 55#include "cpu/thread_context.hh" 56#include "debug/Faults.hh" 57#include "sim/full_system.hh" 58 59namespace ArmISA 60{ 61 62uint8_t ArmFault::shortDescFaultSources[] = { 63 0x01, // AlignmentFault 64 0x04, // InstructionCacheMaintenance 65 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 66 0x0c, // SynchExtAbtOnTranslTableWalkL1 67 0x0e, // SynchExtAbtOnTranslTableWalkL2 68 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 69 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 70 0x1c, // SynchPtyErrOnTranslTableWalkL1 71 0x1e, // SynchPtyErrOnTranslTableWalkL2 72 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 73 0xff, // TranslationL0 (INVALID) 74 0x05, // TranslationL1 75 0x07, // TranslationL2 76 0xff, // TranslationL3 (INVALID) 77 0xff, // AccessFlagL0 (INVALID) 78 0x03, // AccessFlagL1 79 0x06, // AccessFlagL2 80 0xff, // AccessFlagL3 (INVALID) 81 0xff, // DomainL0 (INVALID) 82 0x09, // DomainL1 83 0x0b, // DomainL2 84 0xff, // DomainL3 (INVALID) 85 0xff, // PermissionL0 (INVALID) 86 0x0d, // PermissionL1 87 0x0f, // PermissionL2 88 0xff, // PermissionL3 (INVALID) 89 0x02, // DebugEvent 90 0x08, // SynchronousExternalAbort 91 0x10, // TLBConflictAbort 92 0x19, // SynchPtyErrOnMemoryAccess 93 0x16, // AsynchronousExternalAbort 94 0x18, // AsynchPtyErrOnMemoryAccess 95 0xff, // AddressSizeL0 (INVALID) 96 0xff, // AddressSizeL1 (INVALID) 97 0xff, // AddressSizeL2 (INVALID) 98 0xff, // AddressSizeL3 (INVALID) 99 0x40, // PrefetchTLBMiss 100 0x80 // PrefetchUncacheable 101}; 102 103static_assert(sizeof(ArmFault::shortDescFaultSources) == 104 ArmFault::NumFaultSources, 105 "Invalid size of ArmFault::shortDescFaultSources[]"); 106 107uint8_t ArmFault::longDescFaultSources[] = { 108 0x21, // AlignmentFault 109 0xff, // InstructionCacheMaintenance (INVALID) 110 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 111 0x15, // SynchExtAbtOnTranslTableWalkL1 112 0x16, // SynchExtAbtOnTranslTableWalkL2 113 0x17, // SynchExtAbtOnTranslTableWalkL3 114 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 115 0x1d, // SynchPtyErrOnTranslTableWalkL1 116 0x1e, // SynchPtyErrOnTranslTableWalkL2 117 0x1f, // SynchPtyErrOnTranslTableWalkL3 118 0xff, // TranslationL0 (INVALID) 119 0x05, // TranslationL1 120 0x06, // TranslationL2 121 0x07, // TranslationL3 122 0xff, // AccessFlagL0 (INVALID) 123 0x09, // AccessFlagL1 124 0x0a, // AccessFlagL2 125 0x0b, // AccessFlagL3 126 0xff, // DomainL0 (INVALID) 127 0x3d, // DomainL1 128 0x3e, // DomainL2 129 0xff, // DomainL3 (RESERVED) 130 0xff, // PermissionL0 (INVALID) 131 0x0d, // PermissionL1 132 0x0e, // PermissionL2 133 0x0f, // PermissionL3 134 0x22, // DebugEvent 135 0x10, // SynchronousExternalAbort 136 0x30, // TLBConflictAbort 137 0x18, // SynchPtyErrOnMemoryAccess 138 0x11, // AsynchronousExternalAbort 139 0x19, // AsynchPtyErrOnMemoryAccess 140 0xff, // AddressSizeL0 (INVALID) 141 0xff, // AddressSizeL1 (INVALID) 142 0xff, // AddressSizeL2 (INVALID) 143 0xff, // AddressSizeL3 (INVALID) 144 0x40, // PrefetchTLBMiss 145 0x80 // PrefetchUncacheable 146}; 147 148static_assert(sizeof(ArmFault::longDescFaultSources) == 149 ArmFault::NumFaultSources, 150 "Invalid size of ArmFault::longDescFaultSources[]"); 151 152uint8_t ArmFault::aarch64FaultSources[] = { 153 0x21, // AlignmentFault 154 0xff, // InstructionCacheMaintenance (INVALID) 155 0x14, // SynchExtAbtOnTranslTableWalkL0 156 0x15, // SynchExtAbtOnTranslTableWalkL1 157 0x16, // SynchExtAbtOnTranslTableWalkL2 158 0x17, // SynchExtAbtOnTranslTableWalkL3 159 0x1c, // SynchPtyErrOnTranslTableWalkL0 160 0x1d, // SynchPtyErrOnTranslTableWalkL1 161 0x1e, // SynchPtyErrOnTranslTableWalkL2 162 0x1f, // SynchPtyErrOnTranslTableWalkL3 163 0x04, // TranslationL0 164 0x05, // TranslationL1 165 0x06, // TranslationL2 166 0x07, // TranslationL3 167 0x08, // AccessFlagL0 168 0x09, // AccessFlagL1 169 0x0a, // AccessFlagL2 170 0x0b, // AccessFlagL3 171 // @todo: Section & Page Domain Fault in AArch64? 172 0xff, // DomainL0 (INVALID) 173 0xff, // DomainL1 (INVALID) 174 0xff, // DomainL2 (INVALID) 175 0xff, // DomainL3 (INVALID) 176 0x0c, // PermissionL0 177 0x0d, // PermissionL1 178 0x0e, // PermissionL2 179 0x0f, // PermissionL3 180 0x22, // DebugEvent 181 0x10, // SynchronousExternalAbort 182 0x30, // TLBConflictAbort 183 0x18, // SynchPtyErrOnMemoryAccess 184 0xff, // AsynchronousExternalAbort (INVALID) 185 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 186 0x00, // AddressSizeL0 187 0x01, // AddressSizeL1 188 0x02, // AddressSizeL2 189 0x03, // AddressSizeL3 190 0x40, // PrefetchTLBMiss 191 0x80 // PrefetchUncacheable 192}; 193 194static_assert(sizeof(ArmFault::aarch64FaultSources) == 195 ArmFault::NumFaultSources, 196 "Invalid size of ArmFault::aarch64FaultSources[]"); 197 198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 199// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 200// {A, F} disable, class, stat 201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals( 202 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 203 // location in AArch64) 204 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 205 0, 0, 0, 0, false, true, true, EC_UNKNOWN 206); 207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals( 208 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 209 4, 2, 0, 0, true, false, false, EC_UNKNOWN 210); 211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals( 212 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 213 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP 214); 215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals( 216 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 217 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP 218); 219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals( 220 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 221 4, 4, 4, 4, true, false, false, EC_HVC 222); 223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals( 224 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 225 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP 226); 227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals( 228 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 229 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP 230); 231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals( 232 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 233 8, 8, 0, 0, true, true, false, EC_INVALID 234); 235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals( 236 // @todo: double check these values 237 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 238 0, 0, 0, 0, false, false, false, EC_UNKNOWN 239); 240template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals( 241 "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 242 4, 2, 0, 0, false, false, false, EC_UNKNOWN 243); 244template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals( 245 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 246 4, 4, 0, 0, false, true, false, EC_UNKNOWN 247); 248template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals( 249 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 250 4, 4, 0, 0, false, true, false, EC_INVALID 251); 252template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals( 253 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 254 4, 4, 0, 0, false, true, true, EC_UNKNOWN 255); 256template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals( 257 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 258 4, 4, 0, 0, false, true, true, EC_INVALID 259); 260template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals( 261 // Some dummy values (SupervisorTrap is AArch64-only) 262 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 263 0, 0, 0, 0, false, false, false, EC_UNKNOWN 264); 265template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals( 266 // Some dummy values (PCAlignmentFault is AArch64-only) 267 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 268 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT 269); 270template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals( 271 // Some dummy values (SPAlignmentFault is AArch64-only) 272 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 273 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT 274); 275template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals( 276 // Some dummy values (SError is AArch64-only) 277 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 278 0, 0, 0, 0, false, true, true, EC_SERROR 279); 280template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals( 281 // Some dummy values (SoftwareBreakpoint is AArch64-only) 282 "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 283 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT 284); 285template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals( 286 // Some dummy values 287 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 288 0, 0, 0, 0, false, true, true, EC_UNKNOWN 289); 290template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals( 291 // Some dummy values (SPAlignmentFault is AArch64-only) 292 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 293 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST 294); 295 296Addr 297ArmFault::getVector(ThreadContext *tc) 298{ 299 Addr base; 300 301 // ARM ARM issue C B1.8.1 302 bool haveSecurity = ArmSystem::haveSecurity(tc); 303 304 // panic if SCTLR.VE because I have no idea what to do with vectored 305 // interrupts 306 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 307 assert(!sctlr.ve); 308 // Check for invalid modes 309 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 310 assert(haveSecurity || cpsr.mode != MODE_MON); 311 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 312 313 switch (cpsr.mode) 314 { 315 case MODE_MON: 316 base = tc->readMiscReg(MISCREG_MVBAR); 317 break; 318 case MODE_HYP: 319 base = tc->readMiscReg(MISCREG_HVBAR); 320 break; 321 default: 322 if (sctlr.v) { 323 base = HighVecs; 324 } else { 325 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 326 } 327 break; 328 } 329 return base + offset(tc); 330} 331 332Addr 333ArmFault::getVector64(ThreadContext *tc) 334{ 335 Addr vbar; 336 switch (toEL) { 337 case EL3: 338 assert(ArmSystem::haveSecurity(tc)); 339 vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 340 break; 341 case EL2: 342 assert(ArmSystem::haveVirtualization(tc)); 343 vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 344 break; 345 case EL1: 346 vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 347 break; 348 default: 349 panic("Invalid target exception level"); 350 break; 351 } 352 return vbar + offset64(tc); 353} 354 355MiscRegIndex 356ArmFault::getSyndromeReg64() const 357{ 358 switch (toEL) { 359 case EL1: 360 return MISCREG_ESR_EL1; 361 case EL2: 362 return MISCREG_ESR_EL2; 363 case EL3: 364 return MISCREG_ESR_EL3; 365 default: 366 panic("Invalid exception level"); 367 break; 368 } 369} 370 371MiscRegIndex 372ArmFault::getFaultAddrReg64() const 373{ 374 switch (toEL) { 375 case EL1: 376 return MISCREG_FAR_EL1; 377 case EL2: 378 return MISCREG_FAR_EL2; 379 case EL3: 380 return MISCREG_FAR_EL3; 381 default: 382 panic("Invalid exception level"); 383 break; 384 } 385} 386 387void 388ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 389{ 390 uint32_t value; 391 uint32_t exc_class = (uint32_t) ec(tc); 392 uint32_t issVal = iss(); 393 394 assert(!from64 || ArmSystem::highestELIs64(tc)); 395 396 value = exc_class << 26; 397 398 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 399 // 0x25) for which the ISS information is not valid (ARMv7). 400 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 401 // valid it is treated as RES1. 402 if (to64) { 403 value |= 1 << 25; 404 } else if ((bits(exc_class, 5, 3) != 4) || 405 (bits(exc_class, 2) && bits(issVal, 24))) { 406 if (!machInst.thumb || machInst.bigThumb) 407 value |= 1 << 25; 408 } 409 // Condition code valid for EC[5:4] nonzero 410 if (!from64 && ((bits(exc_class, 5, 4) == 0) && 411 (bits(exc_class, 3, 0) != 0))) { 412 if (!machInst.thumb) { 413 uint32_t cond; 414 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 415 // If its on unconditional instruction report with a cond code of 416 // 0xE, ie the unconditional code 417 cond = (condCode == COND_UC) ? COND_AL : condCode; 418 value |= cond << 20; 419 value |= 1 << 24; 420 } 421 value |= bits(issVal, 19, 0); 422 } else { 423 value |= issVal; 424 } 425 tc->setMiscReg(syndrome_reg, value); 426} 427 428void 429ArmFault::update(ThreadContext *tc) 430{ 431 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 432 433 // Determine source exception level and mode 434 fromMode = (OperatingMode) (uint8_t) cpsr.mode; 435 fromEL = opModeToEL(fromMode); 436 if (opModeIs64(fromMode)) 437 from64 = true; 438 439 // Determine target exception level (aarch64) or target execution 440 // mode (aarch32). 441 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 442 toMode = MODE_MON; 443 toEL = EL3; 444 } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 445 toMode = MODE_HYP; 446 toEL = EL2; 447 hypRouted = true; 448 } else { 449 toMode = nextMode(); 450 toEL = opModeToEL(toMode); 451 } 452 453 if (fromEL > toEL) 454 toEL = fromEL; 455 456 to64 = ELIs64(tc, toEL); 457 458 // The fault specific informations have been updated; it is 459 // now possible to use them inside the fault. 460 faultUpdated = true; 461} 462 463void 464ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 465{ 466 467 // Update fault state informations, like the starting mode (aarch32) 468 // or EL (aarch64) and the ending mode or EL. 469 // From the update function we are also evaluating if the fault must 470 // be handled in AArch64 mode (to64). 471 update(tc); 472 473 if (to64) { 474 // Invoke exception handler in AArch64 state 475 invoke64(tc, inst); 476 return; 477 } 478 479 // ARMv7 (ARM ARM issue C B1.9) 480 481 bool have_security = ArmSystem::haveSecurity(tc); 482 483 FaultBase::invoke(tc); 484 if (!FullSystem) 485 return; 486 countStat()++; 487 488 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 489 SCR scr = tc->readMiscReg(MISCREG_SCR); 490 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 491 saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 492 saved_cpsr.c = tc->readCCReg(CCREG_C); 493 saved_cpsr.v = tc->readCCReg(CCREG_V); 494 saved_cpsr.ge = tc->readCCReg(CCREG_GE); 495 496 Addr curPc M5_VAR_USED = tc->pcState().pc(); 497 ITSTATE it = tc->pcState().itstate(); 498 saved_cpsr.it2 = it.top6; 499 saved_cpsr.it1 = it.bottom2; 500 501 // if we have a valid instruction then use it to annotate this fault with 502 // extra information. This is used to generate the correct fault syndrome 503 // information 504 if (inst) { 505 ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 506 armInst->annotateFault(this); 507 } 508 509 // Ensure Secure state if initially in Monitor mode 510 if (have_security && saved_cpsr.mode == MODE_MON) { 511 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 512 if (scr.ns) { 513 scr.ns = 0; 514 tc->setMiscRegNoEffect(MISCREG_SCR, scr); 515 } 516 } 517 518 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 519 cpsr.mode = toMode; 520 521 // some bits are set differently if we have been routed to hyp mode 522 if (cpsr.mode == MODE_HYP) { 523 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 524 cpsr.t = hsctlr.te; 525 cpsr.e = hsctlr.ee; 526 if (!scr.ea) {cpsr.a = 1;} 527 if (!scr.fiq) {cpsr.f = 1;} 528 if (!scr.irq) {cpsr.i = 1;} 529 } else if (cpsr.mode == MODE_MON) { 530 // Special case handling when entering monitor mode 531 cpsr.t = sctlr.te; 532 cpsr.e = sctlr.ee; 533 cpsr.a = 1; 534 cpsr.f = 1; 535 cpsr.i = 1; 536 } else { 537 cpsr.t = sctlr.te; 538 cpsr.e = sctlr.ee; 539 540 // The *Disable functions are virtual and different per fault 541 cpsr.a = cpsr.a | abortDisable(tc); 542 cpsr.f = cpsr.f | fiqDisable(tc); 543 cpsr.i = 1; 544 } 545 cpsr.it1 = cpsr.it2 = 0; 546 cpsr.j = 0; 547 tc->setMiscReg(MISCREG_CPSR, cpsr); 548 549 // Make sure mailbox sets to one always 550 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 551 552 // Clear the exclusive monitor 553 tc->setMiscReg(MISCREG_LOCKFLAG, 0); 554 555 if (cpsr.mode == MODE_HYP) { 556 tc->setMiscReg(MISCREG_ELR_HYP, curPc + 557 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 558 } else { 559 tc->setIntReg(INTREG_LR, curPc + 560 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 561 } 562 563 switch (cpsr.mode) { 564 case MODE_FIQ: 565 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 566 break; 567 case MODE_IRQ: 568 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 569 break; 570 case MODE_SVC: 571 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 572 break; 573 case MODE_MON: 574 assert(have_security); 575 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 576 break; 577 case MODE_ABORT: 578 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 579 break; 580 case MODE_UNDEFINED: 581 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 582 if (ec(tc) != EC_UNKNOWN) 583 setSyndrome(tc, MISCREG_HSR); 584 break; 585 case MODE_HYP: 586 assert(ArmSystem::haveVirtualization(tc)); 587 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 588 setSyndrome(tc, MISCREG_HSR); 589 break; 590 default: 591 panic("unknown Mode\n"); 592 } 593 594 Addr newPc = getVector(tc); 595 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 596 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 597 PCState pc(newPc); 598 pc.thumb(cpsr.t); 599 pc.nextThumb(pc.thumb()); 600 pc.jazelle(cpsr.j); 601 pc.nextJazelle(pc.jazelle()); 602 pc.aarch64(!cpsr.width); 603 pc.nextAArch64(!cpsr.width); 604 tc->pcState(pc); 605} 606 607void 608ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 609{ 610 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 611 MiscRegIndex elr_idx, spsr_idx; 612 switch (toEL) { 613 case EL1: 614 elr_idx = MISCREG_ELR_EL1; 615 spsr_idx = MISCREG_SPSR_EL1; 616 break; 617 case EL2: 618 assert(ArmSystem::haveVirtualization(tc)); 619 elr_idx = MISCREG_ELR_EL2; 620 spsr_idx = MISCREG_SPSR_EL2; 621 break; 622 case EL3: 623 assert(ArmSystem::haveSecurity(tc)); 624 elr_idx = MISCREG_ELR_EL3; 625 spsr_idx = MISCREG_SPSR_EL3; 626 break; 627 default: 628 panic("Invalid target exception level"); 629 break; 630 } 631 632 // Save process state into SPSR_ELx 633 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 634 CPSR spsr = cpsr; 635 spsr.nz = tc->readCCReg(CCREG_NZ); 636 spsr.c = tc->readCCReg(CCREG_C); 637 spsr.v = tc->readCCReg(CCREG_V); 638 if (from64) { 639 // Force some bitfields to 0 640 spsr.q = 0; 641 spsr.it1 = 0; 642 spsr.j = 0; 643 spsr.res0_23_22 = 0; 644 spsr.ge = 0; 645 spsr.it2 = 0; 646 spsr.t = 0; 647 } else { 648 spsr.ge = tc->readCCReg(CCREG_GE); 649 ITSTATE it = tc->pcState().itstate(); 650 spsr.it2 = it.top6; 651 spsr.it1 = it.bottom2; 652 // Force some bitfields to 0 653 spsr.res0_23_22 = 0; 654 spsr.ss = 0; 655 } 656 tc->setMiscReg(spsr_idx, spsr); 657 658 // Save preferred return address into ELR_ELx 659 Addr curr_pc = tc->pcState().pc(); 660 Addr ret_addr = curr_pc; 661 if (from64) 662 ret_addr += armPcElrOffset(); 663 else 664 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 665 tc->setMiscReg(elr_idx, ret_addr); 666 667 Addr vec_address = getVector64(tc); 668 669 // Update process state 670 OperatingMode64 mode = 0; 671 mode.spX = 1; 672 mode.el = toEL; 673 mode.width = 0; 674 cpsr.mode = mode; 675 cpsr.daif = 0xf; 676 cpsr.il = 0; 677 cpsr.ss = 0; 678 tc->setMiscReg(MISCREG_CPSR, cpsr); 679 680 // Set PC to start of exception handler 681 Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); 682 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 683 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 684 PCState pc(new_pc); 685 pc.aarch64(!cpsr.width); 686 pc.nextAArch64(!cpsr.width); 687 tc->pcState(pc); 688 689 // If we have a valid instruction then use it to annotate this fault with 690 // extra information. This is used to generate the correct fault syndrome 691 // information 692 if (inst) 693 static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 694 // Save exception syndrome 695 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 696 setSyndrome(tc, getSyndromeReg64()); 697} 698 699void 700Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 701{ 702 if (FullSystem) { 703 tc->getCpuPtr()->clearInterrupts(tc->threadId()); 704 tc->clearArchRegs(); 705 } 706 if (!ArmSystem::highestELIs64(tc)) { 707 ArmFault::invoke(tc, inst); 708 tc->setMiscReg(MISCREG_VMPIDR, 709 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 710 711 // Unless we have SMC code to get us there, boot in HYP! 712 if (ArmSystem::haveVirtualization(tc) && 713 !ArmSystem::haveSecurity(tc)) { 714 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 715 cpsr.mode = MODE_HYP; 716 tc->setMiscReg(MISCREG_CPSR, cpsr); 717 } 718 } else { 719 // Advance the PC to the IMPLEMENTATION DEFINED reset value 720 PCState pc = ArmSystem::resetAddr64(tc); 721 pc.aarch64(true); 722 pc.nextAArch64(true); 723 tc->pcState(pc); 724 } 725} 726 727void 728UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 729{ 730 if (FullSystem) { 731 ArmFault::invoke(tc, inst); 732 return; 733 } 734 735 // If the mnemonic isn't defined this has to be an unknown instruction. 736 assert(unknown || mnemonic != NULL); 737 if (disabled) { 738 panic("Attempted to execute disabled instruction " 739 "'%s' (inst 0x%08x)", mnemonic, machInst); 740 } else if (unknown) { 741 panic("Attempted to execute unknown instruction (inst 0x%08x)", 742 machInst); 743 } else { 744 panic("Attempted to execute unimplemented instruction " 745 "'%s' (inst 0x%08x)", mnemonic, machInst); 746 } 747} 748 749bool 750UndefinedInstruction::routeToHyp(ThreadContext *tc) const 751{ 752 bool toHyp; 753 754 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 755 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 756 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 757 758 // if in Hyp mode then stay in Hyp mode 759 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 760 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 761 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 762 return toHyp; 763} 764 765uint32_t 766UndefinedInstruction::iss() const 767{ 768 769 // If UndefinedInstruction is routed to hypervisor, iss field is 0. 770 if (hypRouted) { 771 return 0; 772 } 773 774 if (overrideEc == EC_INVALID) 775 return issRaw; 776 777 uint32_t new_iss = 0; 778 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 779 780 dir = bits(machInst, 21, 21); 781 op0 = bits(machInst, 20, 19); 782 op1 = bits(machInst, 18, 16); 783 CRn = bits(machInst, 15, 12); 784 CRm = bits(machInst, 11, 8); 785 op2 = bits(machInst, 7, 5); 786 Rt = bits(machInst, 4, 0); 787 788 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 789 Rt << 5 | CRm << 1 | dir; 790 791 return new_iss; 792} 793 794void 795SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 796{ 797 if (FullSystem) { 798 ArmFault::invoke(tc, inst); 799 return; 800 } 801 802 // As of now, there isn't a 32 bit thumb version of this instruction. 803 assert(!machInst.bigThumb); 804 uint32_t callNum; 805 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 806 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 807 if (opModeIs64(mode)) 808 callNum = tc->readIntReg(INTREG_X8); 809 else 810 callNum = tc->readIntReg(INTREG_R7); 811 Fault fault; 812 tc->syscall(callNum, &fault); 813 814 // Advance the PC since that won't happen automatically. 815 PCState pc = tc->pcState(); 816 assert(inst); 817 inst->advancePC(pc); 818 tc->pcState(pc); 819} 820 821bool 822SupervisorCall::routeToHyp(ThreadContext *tc) const 823{ 824 bool toHyp; 825 826 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 827 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 828 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 829 830 // if in Hyp mode then stay in Hyp mode 831 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 832 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 833 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 834 return toHyp; 835} 836 837ExceptionClass 838SupervisorCall::ec(ThreadContext *tc) const 839{ 840 return (overrideEc != EC_INVALID) ? overrideEc : 841 (from64 ? EC_SVC_64 : vals.ec); 842} 843 844uint32_t 845SupervisorCall::iss() const 846{ 847 // Even if we have a 24 bit imm from an arm32 instruction then we only use 848 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 849 return issRaw & 0xFFFF; 850} 851 852uint32_t 853SecureMonitorCall::iss() const 854{ 855 if (from64) 856 return bits(machInst, 20, 5); 857 return 0; 858} 859 860ExceptionClass 861UndefinedInstruction::ec(ThreadContext *tc) const 862{ 863 // If UndefinedInstruction is routed to hypervisor, 864 // HSR.EC field is 0. 865 if (hypRouted) 866 return EC_UNKNOWN; 867 else 868 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 869} 870 871 872HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 873 ArmFaultVals<HypervisorCall>(_machInst, _imm) 874{} 875 876ExceptionClass 877HypervisorCall::ec(ThreadContext *tc) const 878{ 879 return from64 ? EC_HVC_64 : vals.ec; 880} 881 882ExceptionClass 883HypervisorTrap::ec(ThreadContext *tc) const 884{ 885 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 886} 887 888template<class T> 889FaultOffset 890ArmFaultVals<T>::offset(ThreadContext *tc) 891{ 892 bool isHypTrap = false; 893 894 // Normally we just use the exception vector from the table at the top if 895 // this file, however if this exception has caused a transition to hype 896 // mode, and its an exception type that would only do this if it has been 897 // trapped then we use the hyp trap vector instead of the normal vector 898 if (vals.hypTrappable) { 899 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 900 if (cpsr.mode == MODE_HYP) { 901 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 902 isHypTrap = spsr.mode != MODE_HYP; 903 } 904 } 905 return isHypTrap ? 0x14 : vals.offset; 906} 907 908template<class T> 909FaultOffset 910ArmFaultVals<T>::offset64(ThreadContext *tc) 911{ 912 if (toEL == fromEL) { 913 if (opModeIsT(fromMode)) 914 return vals.currELTOffset; 915 return vals.currELHOffset; 916 } else { 917 bool lower_32 = false; 918 if (toEL == EL3) { 919 if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2)) 920 lower_32 = ELIs32(tc, EL2); 921 else 922 lower_32 = ELIs32(tc, EL1); 923 } else { 924 lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1)); 925 } 926 927 if (lower_32) 928 return vals.lowerEL32Offset; 929 return vals.lowerEL64Offset; 930 } 931} 932 933// void 934// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 935// { 936// ESR esr = 0; 937// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 938// esr.il = !machInst.thumb; 939// if (machInst.aarch64) 940// esr.imm16 = bits(machInst.instBits, 20, 5); 941// else if (machInst.thumb) 942// esr.imm16 = bits(machInst.instBits, 7, 0); 943// else 944// esr.imm16 = bits(machInst.instBits, 15, 0); 945// tc->setMiscReg(esr_idx, esr); 946// } 947 948void 949SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 950{ 951 if (FullSystem) { 952 ArmFault::invoke(tc, inst); 953 return; 954 } 955} 956 957ExceptionClass 958SecureMonitorCall::ec(ThreadContext *tc) const 959{ 960 return (from64 ? EC_SMC_64 : vals.ec); 961} 962 963bool 964SupervisorTrap::routeToHyp(ThreadContext *tc) const 965{ 966 bool toHyp = false; 967 968 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 969 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 970 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 971 972 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 973 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 974 return toHyp; 975} 976 977uint32_t 978SupervisorTrap::iss() const 979{ 980 // If SupervisorTrap is routed to hypervisor, iss field is 0. 981 if (hypRouted) { 982 return 0; 983 } 984 return issRaw; 985} 986 987ExceptionClass 988SupervisorTrap::ec(ThreadContext *tc) const 989{ 990 if (hypRouted) 991 return EC_UNKNOWN; 992 else 993 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 994} 995 996ExceptionClass 997SecureMonitorTrap::ec(ThreadContext *tc) const 998{ 999 return (overrideEc != EC_INVALID) ? overrideEc : 1000 (from64 ? EC_SMC_64 : vals.ec); 1001} 1002 1003template<class T> 1004void 1005AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1006{ 1007 if (tranMethod == ArmFault::UnknownTran) { 1008 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 1009 : ArmFault::VmsaTran; 1010 1011 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 1012 // See ARM ARM B3-1416 1013 bool override_LPAE = false; 1014 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 1015 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 1016 if (ttbcr_s.eae) { 1017 override_LPAE = true; 1018 } else { 1019 // Unimplemented code option, not seen in testing. May need 1020 // extension according to the manual exceprt above. 1021 DPRINTF(Faults, "Warning: Incomplete translation method " 1022 "override detected.\n"); 1023 } 1024 if (override_LPAE) 1025 tranMethod = ArmFault::LpaeTran; 1026 } 1027 } 1028 1029 if (source == ArmFault::AsynchronousExternalAbort) { 1030 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1031 } 1032 // Get effective fault source encoding 1033 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1034 1035 // source must be determined BEFORE invoking generic routines which will 1036 // try to set hsr etc. and are based upon source! 1037 ArmFaultVals<T>::invoke(tc, inst); 1038 1039 if (!this->to64) { // AArch32 1040 FSR fsr = getFsr(tc); 1041 if (cpsr.mode == MODE_HYP) { 1042 tc->setMiscReg(T::HFarIndex, faultAddr); 1043 } else if (stage2) { 1044 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 1045 tc->setMiscReg(T::HFarIndex, OVAddr); 1046 } else { 1047 tc->setMiscReg(T::FsrIndex, fsr); 1048 tc->setMiscReg(T::FarIndex, faultAddr); 1049 } 1050 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 1051 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 1052 } else { // AArch64 1053 // Set the FAR register. Nothing else to do if we are in AArch64 state 1054 // because the syndrome register has already been set inside invoke64() 1055 if (stage2) { 1056 // stage 2 fault, set HPFAR_EL2 to the faulting IPA 1057 // and FAR_EL2 to the Original VA 1058 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 1059 tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 1060 1061 DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 1062 OVAddr, faultAddr); 1063 } else { 1064 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 1065 } 1066 } 1067} 1068 1069template<class T> 1070void 1071AbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 1072{ 1073 srcEncoded = getFaultStatusCode(tc); 1074 if (srcEncoded == ArmFault::FaultSourceInvalid) { 1075 panic("Invalid fault source\n"); 1076 } 1077 ArmFault::setSyndrome(tc, syndrome_reg); 1078} 1079 1080template<class T> 1081uint8_t 1082AbortFault<T>::getFaultStatusCode(ThreadContext *tc) const 1083{ 1084 1085 panic_if(!this->faultUpdated, 1086 "Trying to use un-updated ArmFault internal variables\n"); 1087 1088 uint8_t fsc = 0; 1089 1090 if (!this->to64) { 1091 // AArch32 1092 assert(tranMethod != ArmFault::UnknownTran); 1093 if (tranMethod == ArmFault::LpaeTran) { 1094 fsc = ArmFault::longDescFaultSources[source]; 1095 } else { 1096 fsc = ArmFault::shortDescFaultSources[source]; 1097 } 1098 } else { 1099 // AArch64 1100 fsc = ArmFault::aarch64FaultSources[source]; 1101 } 1102 1103 return fsc; 1104} 1105 1106template<class T> 1107FSR 1108AbortFault<T>::getFsr(ThreadContext *tc) const 1109{ 1110 FSR fsr = 0; 1111 1112 auto fsc = getFaultStatusCode(tc); 1113 1114 // AArch32 1115 assert(tranMethod != ArmFault::UnknownTran); 1116 if (tranMethod == ArmFault::LpaeTran) { 1117 fsr.status = fsc; 1118 fsr.lpae = 1; 1119 } else { 1120 fsr.fsLow = bits(fsc, 3, 0); 1121 fsr.fsHigh = bits(fsc, 4); 1122 fsr.domain = static_cast<uint8_t>(domain); 1123 } 1124 1125 fsr.wnr = (write ? 1 : 0); 1126 fsr.ext = 0; 1127 1128 return fsr; 1129} 1130 1131template<class T> 1132bool 1133AbortFault<T>::abortDisable(ThreadContext *tc) 1134{ 1135 if (ArmSystem::haveSecurity(tc)) { 1136 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1137 return (!scr.ns || scr.aw); 1138 } 1139 return true; 1140} 1141 1142template<class T> 1143void 1144AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 1145{ 1146 switch (id) 1147 { 1148 case ArmFault::S1PTW: 1149 s1ptw = val; 1150 break; 1151 case ArmFault::OVA: 1152 OVAddr = val; 1153 break; 1154 1155 // Just ignore unknown ID's 1156 default: 1157 break; 1158 } 1159} 1160 1161template<class T> 1162uint32_t 1163AbortFault<T>::iss() const 1164{ 1165 uint32_t val; 1166 1167 val = srcEncoded & 0x3F; 1168 val |= write << 6; 1169 val |= s1ptw << 7; 1170 return (val); 1171} 1172 1173template<class T> 1174bool 1175AbortFault<T>::isMMUFault() const 1176{ 1177 // NOTE: Not relying on LL information being aligned to lowest bits here 1178 return 1179 (source == ArmFault::AlignmentFault) || 1180 ((source >= ArmFault::TranslationLL) && 1181 (source < ArmFault::TranslationLL + 4)) || 1182 ((source >= ArmFault::AccessFlagLL) && 1183 (source < ArmFault::AccessFlagLL + 4)) || 1184 ((source >= ArmFault::DomainLL) && 1185 (source < ArmFault::DomainLL + 4)) || 1186 ((source >= ArmFault::PermissionLL) && 1187 (source < ArmFault::PermissionLL + 4)); 1188} 1189 1190ExceptionClass 1191PrefetchAbort::ec(ThreadContext *tc) const 1192{ 1193 if (to64) { 1194 // AArch64 1195 if (toEL == fromEL) 1196 return EC_PREFETCH_ABORT_CURR_EL; 1197 else 1198 return EC_PREFETCH_ABORT_LOWER_EL; 1199 } else { 1200 // AArch32 1201 // Abort faults have different EC codes depending on whether 1202 // the fault originated within HYP mode, or not. So override 1203 // the method and add the extra adjustment of the EC value. 1204 1205 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 1206 1207 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1208 if (spsr.mode == MODE_HYP) { 1209 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1210 } 1211 return ec; 1212 } 1213} 1214 1215bool 1216PrefetchAbort::routeToMonitor(ThreadContext *tc) const 1217{ 1218 SCR scr = 0; 1219 if (from64) 1220 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1221 else 1222 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1223 1224 return scr.ea && !isMMUFault(); 1225} 1226 1227bool 1228PrefetchAbort::routeToHyp(ThreadContext *tc) const 1229{ 1230 bool toHyp; 1231 1232 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1233 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1234 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1235 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1236 1237 // if in Hyp mode then stay in Hyp mode 1238 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1239 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1240 toHyp |= (stage2 || 1241 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 1242 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 1243 ) && !inSecureState(tc); 1244 return toHyp; 1245} 1246 1247ExceptionClass 1248DataAbort::ec(ThreadContext *tc) const 1249{ 1250 if (to64) { 1251 // AArch64 1252 if (source == ArmFault::AsynchronousExternalAbort) { 1253 panic("Asynchronous External Abort should be handled with " 1254 "SystemErrors (SErrors)!"); 1255 } 1256 if (toEL == fromEL) 1257 return EC_DATA_ABORT_CURR_EL; 1258 else 1259 return EC_DATA_ABORT_LOWER_EL; 1260 } else { 1261 // AArch32 1262 // Abort faults have different EC codes depending on whether 1263 // the fault originated within HYP mode, or not. So override 1264 // the method and add the extra adjustment of the EC value. 1265 1266 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 1267 1268 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1269 if (spsr.mode == MODE_HYP) { 1270 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1271 } 1272 return ec; 1273 } 1274} 1275 1276bool 1277DataAbort::routeToMonitor(ThreadContext *tc) const 1278{ 1279 SCR scr = 0; 1280 if (from64) 1281 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1282 else 1283 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1284 1285 return scr.ea && !isMMUFault(); 1286} 1287 1288bool 1289DataAbort::routeToHyp(ThreadContext *tc) const 1290{ 1291 bool toHyp; 1292 1293 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1294 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1295 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1296 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1297 1298 // if in Hyp mode then stay in Hyp mode 1299 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1300 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1301 toHyp |= (stage2 || 1302 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 1303 ((source == DebugEvent) && hdcr.tde) ) 1304 ) || 1305 ( (cpsr.mode == MODE_USER) && hcr.tge && 1306 ((source == AlignmentFault) || 1307 (source == SynchronousExternalAbort)) 1308 ) 1309 ) && !inSecureState(tc); 1310 return toHyp; 1311} 1312 1313uint32_t 1314DataAbort::iss() const 1315{ 1316 uint32_t val; 1317 1318 // Add on the data abort specific fields to the generic abort ISS value 1319 val = AbortFault<DataAbort>::iss(); 1320 // ISS is valid if not caused by a stage 1 page table walk, and when taken 1321 // to AArch64 only when directed to EL2 1322 if (!s1ptw && (!to64 || toEL == EL2)) { 1323 val |= isv << 24; 1324 if (isv) { 1325 val |= sas << 22; 1326 val |= sse << 21; 1327 val |= srt << 16; 1328 // AArch64 only. These assignments are safe on AArch32 as well 1329 // because these vars are initialized to false 1330 val |= sf << 15; 1331 val |= ar << 14; 1332 } 1333 } 1334 return (val); 1335} 1336 1337void 1338DataAbort::annotate(AnnotationIDs id, uint64_t val) 1339{ 1340 AbortFault<DataAbort>::annotate(id, val); 1341 switch (id) 1342 { 1343 case SAS: 1344 isv = true; 1345 sas = val; 1346 break; 1347 case SSE: 1348 isv = true; 1349 sse = val; 1350 break; 1351 case SRT: 1352 isv = true; 1353 srt = val; 1354 break; 1355 case SF: 1356 isv = true; 1357 sf = val; 1358 break; 1359 case AR: 1360 isv = true; 1361 ar = val; 1362 break; 1363 // Just ignore unknown ID's 1364 default: 1365 break; 1366 } 1367} 1368 1369void 1370VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1371{ 1372 AbortFault<VirtualDataAbort>::invoke(tc, inst); 1373 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1374 hcr.va = 0; 1375 tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 1376} 1377 1378bool 1379Interrupt::routeToMonitor(ThreadContext *tc) const 1380{ 1381 assert(ArmSystem::haveSecurity(tc)); 1382 SCR scr = 0; 1383 if (from64) 1384 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1385 else 1386 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1387 return scr.irq; 1388} 1389 1390bool 1391Interrupt::routeToHyp(ThreadContext *tc) const 1392{ 1393 bool toHyp; 1394 1395 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1396 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1397 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1398 // Determine whether IRQs are routed to Hyp mode. 1399 toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 1400 (cpsr.mode == MODE_HYP); 1401 return toHyp; 1402} 1403 1404bool 1405Interrupt::abortDisable(ThreadContext *tc) 1406{ 1407 if (ArmSystem::haveSecurity(tc)) { 1408 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1409 return (!scr.ns || scr.aw); 1410 } 1411 return true; 1412} 1413 1414VirtualInterrupt::VirtualInterrupt() 1415{} 1416 1417bool 1418FastInterrupt::routeToMonitor(ThreadContext *tc) const 1419{ 1420 assert(ArmSystem::haveSecurity(tc)); 1421 SCR scr = 0; 1422 if (from64) 1423 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1424 else 1425 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1426 return scr.fiq; 1427} 1428 1429bool 1430FastInterrupt::routeToHyp(ThreadContext *tc) const 1431{ 1432 bool toHyp; 1433 1434 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1435 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1436 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1437 // Determine whether IRQs are routed to Hyp mode. 1438 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 1439 (cpsr.mode == MODE_HYP); 1440 return toHyp; 1441} 1442 1443bool 1444FastInterrupt::abortDisable(ThreadContext *tc) 1445{ 1446 if (ArmSystem::haveSecurity(tc)) { 1447 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1448 return (!scr.ns || scr.aw); 1449 } 1450 return true; 1451} 1452 1453bool 1454FastInterrupt::fiqDisable(ThreadContext *tc) 1455{ 1456 if (ArmSystem::haveVirtualization(tc)) { 1457 return true; 1458 } else if (ArmSystem::haveSecurity(tc)) { 1459 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1460 return (!scr.ns || scr.fw); 1461 } 1462 return true; 1463} 1464 1465VirtualFastInterrupt::VirtualFastInterrupt() 1466{} 1467 1468void 1469PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1470{ 1471 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 1472 assert(from64); 1473 // Set the FAR 1474 tc->setMiscReg(getFaultAddrReg64(), faultPC); 1475} 1476 1477bool 1478PCAlignmentFault::routeToHyp(ThreadContext *tc) const 1479{ 1480 bool toHyp = false; 1481 1482 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1483 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1484 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1485 1486 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 1487 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 1488 return toHyp; 1489} 1490 1491SPAlignmentFault::SPAlignmentFault() 1492{} 1493 1494SystemError::SystemError() 1495{} 1496 1497void 1498SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1499{ 1500 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1501 ArmFault::invoke(tc, inst); 1502} 1503 1504bool 1505SystemError::routeToMonitor(ThreadContext *tc) const 1506{ 1507 assert(ArmSystem::haveSecurity(tc)); 1508 assert(from64); 1509 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1510 return scr.ea; 1511} 1512 1513bool 1514SystemError::routeToHyp(ThreadContext *tc) const 1515{ 1516 bool toHyp; 1517 assert(from64); 1518 1519 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1520 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1521 1522 toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 1523 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 1524 return toHyp; 1525} 1526 1527 1528SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 1529 : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 1530{} 1531 1532bool 1533SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 1534{ 1535 assert(from64); 1536 1537 const bool have_el2 = ArmSystem::haveVirtualization(tc); 1538 1539 const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 1540 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 1541 1542 return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 1543 (hcr.tge || mdcr.tde); 1544} 1545 1546ExceptionClass 1547SoftwareBreakpoint::ec(ThreadContext *tc) const 1548{ 1549 return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec; 1550} 1551 1552void 1553ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1554 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1555 if (!FullSystem) 1556 return; 1557 1558 // Set sev_mailbox to 1, clear the pending interrupt from remote 1559 // SEV execution and let pipeline continue as pcState is still 1560 // valid. 1561 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 1562 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 1563} 1564 1565// Instantiate all the templates to make the linker happy 1566template class ArmFaultVals<Reset>; 1567template class ArmFaultVals<UndefinedInstruction>; 1568template class ArmFaultVals<SupervisorCall>; 1569template class ArmFaultVals<SecureMonitorCall>; 1570template class ArmFaultVals<HypervisorCall>; 1571template class ArmFaultVals<PrefetchAbort>; 1572template class ArmFaultVals<DataAbort>; 1573template class ArmFaultVals<VirtualDataAbort>; 1574template class ArmFaultVals<HypervisorTrap>; 1575template class ArmFaultVals<Interrupt>; 1576template class ArmFaultVals<VirtualInterrupt>; 1577template class ArmFaultVals<FastInterrupt>; 1578template class ArmFaultVals<VirtualFastInterrupt>; 1579template class ArmFaultVals<SupervisorTrap>; 1580template class ArmFaultVals<SecureMonitorTrap>; 1581template class ArmFaultVals<PCAlignmentFault>; 1582template class ArmFaultVals<SPAlignmentFault>; 1583template class ArmFaultVals<SystemError>; 1584template class ArmFaultVals<SoftwareBreakpoint>; 1585template class ArmFaultVals<ArmSev>; 1586template class AbortFault<PrefetchAbort>; 1587template class AbortFault<DataAbort>; 1588template class AbortFault<VirtualDataAbort>; 1589 1590 1591IllegalInstSetStateFault::IllegalInstSetStateFault() 1592{} 1593 1594 1595} // namespace ArmISA 1596