faults.cc revision 12569
1/*
2 * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2003-2005 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Ali Saidi
42 *          Gabe Black
43 *          Giacomo Gabrielli
44 *          Thomas Grocutt
45 */
46
47#include "arch/arm/faults.hh"
48
49#include "arch/arm/insts/static_inst.hh"
50#include "arch/arm/system.hh"
51#include "arch/arm/utility.hh"
52#include "base/compiler.hh"
53#include "base/trace.hh"
54#include "cpu/base.hh"
55#include "cpu/thread_context.hh"
56#include "debug/Faults.hh"
57#include "sim/full_system.hh"
58
59namespace ArmISA
60{
61
62uint8_t ArmFault::shortDescFaultSources[] = {
63    0x01,  // AlignmentFault
64    0x04,  // InstructionCacheMaintenance
65    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
66    0x0c,  // SynchExtAbtOnTranslTableWalkL1
67    0x0e,  // SynchExtAbtOnTranslTableWalkL2
68    0xff,  // SynchExtAbtOnTranslTableWalkL3 (INVALID)
69    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
70    0x1c,  // SynchPtyErrOnTranslTableWalkL1
71    0x1e,  // SynchPtyErrOnTranslTableWalkL2
72    0xff,  // SynchPtyErrOnTranslTableWalkL3 (INVALID)
73    0xff,  // TranslationL0 (INVALID)
74    0x05,  // TranslationL1
75    0x07,  // TranslationL2
76    0xff,  // TranslationL3 (INVALID)
77    0xff,  // AccessFlagL0 (INVALID)
78    0x03,  // AccessFlagL1
79    0x06,  // AccessFlagL2
80    0xff,  // AccessFlagL3 (INVALID)
81    0xff,  // DomainL0 (INVALID)
82    0x09,  // DomainL1
83    0x0b,  // DomainL2
84    0xff,  // DomainL3 (INVALID)
85    0xff,  // PermissionL0 (INVALID)
86    0x0d,  // PermissionL1
87    0x0f,  // PermissionL2
88    0xff,  // PermissionL3 (INVALID)
89    0x02,  // DebugEvent
90    0x08,  // SynchronousExternalAbort
91    0x10,  // TLBConflictAbort
92    0x19,  // SynchPtyErrOnMemoryAccess
93    0x16,  // AsynchronousExternalAbort
94    0x18,  // AsynchPtyErrOnMemoryAccess
95    0xff,  // AddressSizeL0 (INVALID)
96    0xff,  // AddressSizeL1 (INVALID)
97    0xff,  // AddressSizeL2 (INVALID)
98    0xff,  // AddressSizeL3 (INVALID)
99    0x40,  // PrefetchTLBMiss
100    0x80   // PrefetchUncacheable
101};
102
103static_assert(sizeof(ArmFault::shortDescFaultSources) ==
104              ArmFault::NumFaultSources,
105              "Invalid size of ArmFault::shortDescFaultSources[]");
106
107uint8_t ArmFault::longDescFaultSources[] = {
108    0x21,  // AlignmentFault
109    0xff,  // InstructionCacheMaintenance (INVALID)
110    0xff,  // SynchExtAbtOnTranslTableWalkL0 (INVALID)
111    0x15,  // SynchExtAbtOnTranslTableWalkL1
112    0x16,  // SynchExtAbtOnTranslTableWalkL2
113    0x17,  // SynchExtAbtOnTranslTableWalkL3
114    0xff,  // SynchPtyErrOnTranslTableWalkL0 (INVALID)
115    0x1d,  // SynchPtyErrOnTranslTableWalkL1
116    0x1e,  // SynchPtyErrOnTranslTableWalkL2
117    0x1f,  // SynchPtyErrOnTranslTableWalkL3
118    0xff,  // TranslationL0 (INVALID)
119    0x05,  // TranslationL1
120    0x06,  // TranslationL2
121    0x07,  // TranslationL3
122    0xff,  // AccessFlagL0 (INVALID)
123    0x09,  // AccessFlagL1
124    0x0a,  // AccessFlagL2
125    0x0b,  // AccessFlagL3
126    0xff,  // DomainL0 (INVALID)
127    0x3d,  // DomainL1
128    0x3e,  // DomainL2
129    0xff,  // DomainL3 (RESERVED)
130    0xff,  // PermissionL0 (INVALID)
131    0x0d,  // PermissionL1
132    0x0e,  // PermissionL2
133    0x0f,  // PermissionL3
134    0x22,  // DebugEvent
135    0x10,  // SynchronousExternalAbort
136    0x30,  // TLBConflictAbort
137    0x18,  // SynchPtyErrOnMemoryAccess
138    0x11,  // AsynchronousExternalAbort
139    0x19,  // AsynchPtyErrOnMemoryAccess
140    0xff,  // AddressSizeL0 (INVALID)
141    0xff,  // AddressSizeL1 (INVALID)
142    0xff,  // AddressSizeL2 (INVALID)
143    0xff,  // AddressSizeL3 (INVALID)
144    0x40,  // PrefetchTLBMiss
145    0x80   // PrefetchUncacheable
146};
147
148static_assert(sizeof(ArmFault::longDescFaultSources) ==
149              ArmFault::NumFaultSources,
150              "Invalid size of ArmFault::longDescFaultSources[]");
151
152uint8_t ArmFault::aarch64FaultSources[] = {
153    0x21,  // AlignmentFault
154    0xff,  // InstructionCacheMaintenance (INVALID)
155    0x14,  // SynchExtAbtOnTranslTableWalkL0
156    0x15,  // SynchExtAbtOnTranslTableWalkL1
157    0x16,  // SynchExtAbtOnTranslTableWalkL2
158    0x17,  // SynchExtAbtOnTranslTableWalkL3
159    0x1c,  // SynchPtyErrOnTranslTableWalkL0
160    0x1d,  // SynchPtyErrOnTranslTableWalkL1
161    0x1e,  // SynchPtyErrOnTranslTableWalkL2
162    0x1f,  // SynchPtyErrOnTranslTableWalkL3
163    0x04,  // TranslationL0
164    0x05,  // TranslationL1
165    0x06,  // TranslationL2
166    0x07,  // TranslationL3
167    0x08,  // AccessFlagL0
168    0x09,  // AccessFlagL1
169    0x0a,  // AccessFlagL2
170    0x0b,  // AccessFlagL3
171    // @todo: Section & Page Domain Fault in AArch64?
172    0xff,  // DomainL0 (INVALID)
173    0xff,  // DomainL1 (INVALID)
174    0xff,  // DomainL2 (INVALID)
175    0xff,  // DomainL3 (INVALID)
176    0x0c,  // PermissionL0
177    0x0d,  // PermissionL1
178    0x0e,  // PermissionL2
179    0x0f,  // PermissionL3
180    0xff,  // DebugEvent (INVALID)
181    0x10,  // SynchronousExternalAbort
182    0x30,  // TLBConflictAbort
183    0x18,  // SynchPtyErrOnMemoryAccess
184    0xff,  // AsynchronousExternalAbort (INVALID)
185    0xff,  // AsynchPtyErrOnMemoryAccess (INVALID)
186    0x00,  // AddressSizeL0
187    0x01,  // AddressSizeL1
188    0x02,  // AddressSizeL2
189    0x03,  // AddressSizeL3
190    0x40,  // PrefetchTLBMiss
191    0x80   // PrefetchUncacheable
192};
193
194static_assert(sizeof(ArmFault::aarch64FaultSources) ==
195              ArmFault::NumFaultSources,
196              "Invalid size of ArmFault::aarch64FaultSources[]");
197
198// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode,
199//         {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap,
200//         {A, F} disable, class, stat
201template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals(
202    // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
203    // location in AArch64)
204    "Reset",                 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
205    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
206);
207template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals(
208    "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
209    4, 2, 0, 0, true,  false, false, EC_UNKNOWN
210);
211template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals(
212    "Supervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
213    4, 2, 4, 2, true,  false, false, EC_SVC_TO_HYP
214);
215template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals(
216    "Secure Monitor Call",   0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
217    4, 4, 4, 4, false, true,  true,  EC_SMC_TO_HYP
218);
219template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals(
220    "Hypervisor Call",       0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
221    4, 4, 4, 4, true,  false, false, EC_HVC
222);
223template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals(
224    "Prefetch Abort",        0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
225    4, 4, 0, 0, true,  true,  false, EC_PREFETCH_ABORT_TO_HYP
226);
227template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals(
228    "Data Abort",            0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
229    8, 8, 0, 0, true,  true,  false, EC_DATA_ABORT_TO_HYP
230);
231template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals(
232    "Virtual Data Abort",    0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
233    8, 8, 0, 0, true,  true,  false, EC_INVALID
234);
235template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals(
236    // @todo: double check these values
237    "Hypervisor Trap",       0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
238    0, 0, 0, 0, false, false, false, EC_UNKNOWN
239);
240template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals(
241    "Secure Monitor Trap",   0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
242    4, 2, 0, 0, false, false, false, EC_UNKNOWN
243);
244template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals(
245    "IRQ",                   0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
246    4, 4, 0, 0, false, true,  false, EC_UNKNOWN
247);
248template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals(
249    "Virtual IRQ",           0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
250    4, 4, 0, 0, false, true,  false, EC_INVALID
251);
252template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals(
253    "FIQ",                   0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
254    4, 4, 0, 0, false, true,  true,  EC_UNKNOWN
255);
256template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals(
257    "Virtual FIQ",           0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
258    4, 4, 0, 0, false, true,  true,  EC_INVALID
259);
260template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals(
261    // Some dummy values (SupervisorTrap is AArch64-only)
262    "Supervisor Trap",   0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
263    0, 0, 0, 0, false, false, false, EC_UNKNOWN
264);
265template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals(
266    // Some dummy values (PCAlignmentFault is AArch64-only)
267    "PC Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
268    0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
269);
270template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals(
271    // Some dummy values (SPAlignmentFault is AArch64-only)
272    "SP Alignment Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
273    0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
274);
275template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals(
276    // Some dummy values (SError is AArch64-only)
277    "SError",                0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
278    0, 0, 0, 0, false, true,  true,  EC_SERROR
279);
280template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals(
281    // Some dummy values (SoftwareBreakpoint is AArch64-only)
282    "Software Breakpoint",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
283    0, 0, 0, 0, true, false, false,  EC_SOFTWARE_BREAKPOINT
284);
285template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals(
286    // Some dummy values
287    "ArmSev Flush",          0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
288    0, 0, 0, 0, false, true,  true,  EC_UNKNOWN
289);
290template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals(
291    // Some dummy values (SPAlignmentFault is AArch64-only)
292    "Illegal Inst Set State Fault",   0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
293    0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST
294);
295
296Addr
297ArmFault::getVector(ThreadContext *tc)
298{
299    Addr base;
300
301    // ARM ARM issue C B1.8.1
302    bool haveSecurity = ArmSystem::haveSecurity(tc);
303
304    // panic if SCTLR.VE because I have no idea what to do with vectored
305    // interrupts
306    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
307    assert(!sctlr.ve);
308    // Check for invalid modes
309    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
310    assert(haveSecurity                      || cpsr.mode != MODE_MON);
311    assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP);
312
313    switch (cpsr.mode)
314    {
315      case MODE_MON:
316        base = tc->readMiscReg(MISCREG_MVBAR);
317        break;
318      case MODE_HYP:
319        base = tc->readMiscReg(MISCREG_HVBAR);
320        break;
321      default:
322        if (sctlr.v) {
323            base = HighVecs;
324        } else {
325            base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0;
326        }
327        break;
328    }
329    return base + offset(tc);
330}
331
332Addr
333ArmFault::getVector64(ThreadContext *tc)
334{
335    Addr vbar;
336    switch (toEL) {
337      case EL3:
338        assert(ArmSystem::haveSecurity(tc));
339        vbar = tc->readMiscReg(MISCREG_VBAR_EL3);
340        break;
341      case EL2:
342        assert(ArmSystem::haveVirtualization(tc));
343        vbar = tc->readMiscReg(MISCREG_VBAR_EL2);
344        break;
345      case EL1:
346        vbar = tc->readMiscReg(MISCREG_VBAR_EL1);
347        break;
348      default:
349        panic("Invalid target exception level");
350        break;
351    }
352    return vbar + offset64(tc);
353}
354
355MiscRegIndex
356ArmFault::getSyndromeReg64() const
357{
358    switch (toEL) {
359      case EL1:
360        return MISCREG_ESR_EL1;
361      case EL2:
362        return MISCREG_ESR_EL2;
363      case EL3:
364        return MISCREG_ESR_EL3;
365      default:
366        panic("Invalid exception level");
367        break;
368    }
369}
370
371MiscRegIndex
372ArmFault::getFaultAddrReg64() const
373{
374    switch (toEL) {
375      case EL1:
376        return MISCREG_FAR_EL1;
377      case EL2:
378        return MISCREG_FAR_EL2;
379      case EL3:
380        return MISCREG_FAR_EL3;
381      default:
382        panic("Invalid exception level");
383        break;
384    }
385}
386
387void
388ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg)
389{
390    uint32_t value;
391    uint32_t exc_class = (uint32_t) ec(tc);
392    uint32_t issVal = iss();
393
394    assert(!from64 || ArmSystem::highestELIs64(tc));
395
396    value = exc_class << 26;
397
398    // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24,
399    // 0x25) for which the ISS information is not valid (ARMv7).
400    // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not
401    // valid it is treated as RES1.
402    if (to64) {
403        value |= 1 << 25;
404    } else if ((bits(exc_class, 5, 3) != 4) ||
405               (bits(exc_class, 2) && bits(issVal, 24))) {
406        if (!machInst.thumb || machInst.bigThumb)
407            value |= 1 << 25;
408    }
409    // Condition code valid for EC[5:4] nonzero
410    if (!from64 && ((bits(exc_class, 5, 4) == 0) &&
411                    (bits(exc_class, 3, 0) != 0))) {
412        if (!machInst.thumb) {
413            uint32_t      cond;
414            ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode;
415            // If its on unconditional instruction report with a cond code of
416            // 0xE, ie the unconditional code
417            cond  = (condCode == COND_UC) ? COND_AL : condCode;
418            value |= cond << 20;
419            value |= 1    << 24;
420        }
421        value |= bits(issVal, 19, 0);
422    } else {
423        value |= issVal;
424    }
425    tc->setMiscReg(syndrome_reg, value);
426}
427
428void
429ArmFault::update(ThreadContext *tc)
430{
431    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
432
433    // Determine source exception level and mode
434    fromMode = (OperatingMode) (uint8_t) cpsr.mode;
435    fromEL = opModeToEL(fromMode);
436    if (opModeIs64(fromMode))
437        from64 = true;
438
439    // Determine target exception level (aarch64) or target execution
440    // mode (aarch32).
441    if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) {
442        toMode = MODE_MON;
443        toEL = EL3;
444    } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) {
445        toMode = MODE_HYP;
446        toEL = EL2;
447        hypRouted = true;
448    } else {
449        toMode = nextMode();
450        toEL = opModeToEL(toMode);
451    }
452
453    if (fromEL > toEL)
454        toEL = fromEL;
455
456    to64 = ELIs64(tc, toEL);
457
458    // The fault specific informations have been updated; it is
459    // now possible to use them inside the fault.
460    faultUpdated = true;
461}
462
463void
464ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
465{
466
467    // Update fault state informations, like the starting mode (aarch32)
468    // or EL (aarch64) and the ending mode or EL.
469    // From the update function we are also evaluating if the fault must
470    // be handled in AArch64 mode (to64).
471    update(tc);
472
473    if (to64) {
474        // Invoke exception handler in AArch64 state
475        invoke64(tc, inst);
476        return;
477    }
478
479    // ARMv7 (ARM ARM issue C B1.9)
480
481    bool have_security       = ArmSystem::haveSecurity(tc);
482    bool have_virtualization = ArmSystem::haveVirtualization(tc);
483
484    FaultBase::invoke(tc);
485    if (!FullSystem)
486        return;
487    countStat()++;
488
489    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
490    SCR scr = tc->readMiscReg(MISCREG_SCR);
491    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR);
492    saved_cpsr.nz = tc->readCCReg(CCREG_NZ);
493    saved_cpsr.c = tc->readCCReg(CCREG_C);
494    saved_cpsr.v = tc->readCCReg(CCREG_V);
495    saved_cpsr.ge = tc->readCCReg(CCREG_GE);
496
497    Addr curPc M5_VAR_USED = tc->pcState().pc();
498    ITSTATE it = tc->pcState().itstate();
499    saved_cpsr.it2 = it.top6;
500    saved_cpsr.it1 = it.bottom2;
501
502    // if we have a valid instruction then use it to annotate this fault with
503    // extra information. This is used to generate the correct fault syndrome
504    // information
505    if (inst) {
506        ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get());
507        armInst->annotateFault(this);
508    }
509
510    // Ensure Secure state if initially in Monitor mode
511    if (have_security && saved_cpsr.mode == MODE_MON) {
512        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
513        if (scr.ns) {
514            scr.ns = 0;
515            tc->setMiscRegNoEffect(MISCREG_SCR, scr);
516        }
517    }
518
519    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
520    cpsr.mode = toMode;
521
522    // some bits are set differently if we have been routed to hyp mode
523    if (cpsr.mode == MODE_HYP) {
524        SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR);
525        cpsr.t = hsctlr.te;
526        cpsr.e = hsctlr.ee;
527        if (!scr.ea)  {cpsr.a = 1;}
528        if (!scr.fiq) {cpsr.f = 1;}
529        if (!scr.irq) {cpsr.i = 1;}
530    } else if (cpsr.mode == MODE_MON) {
531        // Special case handling when entering monitor mode
532        cpsr.t = sctlr.te;
533        cpsr.e = sctlr.ee;
534        cpsr.a = 1;
535        cpsr.f = 1;
536        cpsr.i = 1;
537    } else {
538        cpsr.t = sctlr.te;
539        cpsr.e = sctlr.ee;
540
541        // The *Disable functions are virtual and different per fault
542        cpsr.a = cpsr.a | abortDisable(tc);
543        cpsr.f = cpsr.f | fiqDisable(tc);
544        cpsr.i = 1;
545    }
546    cpsr.it1 = cpsr.it2 = 0;
547    cpsr.j = 0;
548    tc->setMiscReg(MISCREG_CPSR, cpsr);
549
550    // Make sure mailbox sets to one always
551    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
552
553    // Clear the exclusive monitor
554    tc->setMiscReg(MISCREG_LOCKFLAG, 0);
555
556    if (cpsr.mode == MODE_HYP) {
557        tc->setMiscReg(MISCREG_ELR_HYP, curPc +
558                (saved_cpsr.t ? thumbPcOffset(true)  : armPcOffset(true)));
559    } else {
560        tc->setIntReg(INTREG_LR, curPc +
561                (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
562    }
563
564    switch (cpsr.mode) {
565      case MODE_FIQ:
566        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
567        break;
568      case MODE_IRQ:
569        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
570        break;
571      case MODE_SVC:
572        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
573        break;
574      case MODE_MON:
575        assert(have_security);
576        tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr);
577        break;
578      case MODE_ABORT:
579        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
580        break;
581      case MODE_UNDEFINED:
582        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
583        if (ec(tc) != EC_UNKNOWN)
584            setSyndrome(tc, MISCREG_HSR);
585        break;
586      case MODE_HYP:
587        assert(have_virtualization);
588        tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr);
589        setSyndrome(tc, MISCREG_HSR);
590        break;
591      default:
592        panic("unknown Mode\n");
593    }
594
595    Addr newPc = getVector(tc);
596    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
597            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
598    PCState pc(newPc);
599    pc.thumb(cpsr.t);
600    pc.nextThumb(pc.thumb());
601    pc.jazelle(cpsr.j);
602    pc.nextJazelle(pc.jazelle());
603    pc.aarch64(!cpsr.width);
604    pc.nextAArch64(!cpsr.width);
605    tc->pcState(pc);
606}
607
608void
609ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst)
610{
611    // Determine actual misc. register indices for ELR_ELx and SPSR_ELx
612    MiscRegIndex elr_idx, spsr_idx;
613    switch (toEL) {
614      case EL1:
615        elr_idx = MISCREG_ELR_EL1;
616        spsr_idx = MISCREG_SPSR_EL1;
617        break;
618      case EL2:
619        assert(ArmSystem::haveVirtualization(tc));
620        elr_idx = MISCREG_ELR_EL2;
621        spsr_idx = MISCREG_SPSR_EL2;
622        break;
623      case EL3:
624        assert(ArmSystem::haveSecurity(tc));
625        elr_idx = MISCREG_ELR_EL3;
626        spsr_idx = MISCREG_SPSR_EL3;
627        break;
628      default:
629        panic("Invalid target exception level");
630        break;
631    }
632
633    // Save process state into SPSR_ELx
634    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
635    CPSR spsr = cpsr;
636    spsr.nz = tc->readCCReg(CCREG_NZ);
637    spsr.c = tc->readCCReg(CCREG_C);
638    spsr.v = tc->readCCReg(CCREG_V);
639    if (from64) {
640        // Force some bitfields to 0
641        spsr.q = 0;
642        spsr.it1 = 0;
643        spsr.j = 0;
644        spsr.res0_23_22 = 0;
645        spsr.ge = 0;
646        spsr.it2 = 0;
647        spsr.t = 0;
648    } else {
649        spsr.ge = tc->readCCReg(CCREG_GE);
650        ITSTATE it = tc->pcState().itstate();
651        spsr.it2 = it.top6;
652        spsr.it1 = it.bottom2;
653        // Force some bitfields to 0
654        spsr.res0_23_22 = 0;
655        spsr.ss = 0;
656    }
657    tc->setMiscReg(spsr_idx, spsr);
658
659    // Save preferred return address into ELR_ELx
660    Addr curr_pc = tc->pcState().pc();
661    Addr ret_addr = curr_pc;
662    if (from64)
663        ret_addr += armPcElrOffset();
664    else
665        ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset();
666    tc->setMiscReg(elr_idx, ret_addr);
667
668    Addr vec_address = getVector64(tc);
669
670    // Update process state
671    OperatingMode64 mode = 0;
672    mode.spX = 1;
673    mode.el = toEL;
674    mode.width = 0;
675    cpsr.mode = mode;
676    cpsr.daif = 0xf;
677    cpsr.il = 0;
678    cpsr.ss = 0;
679    tc->setMiscReg(MISCREG_CPSR, cpsr);
680
681    // Set PC to start of exception handler
682    Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL);
683    DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x "
684            "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc);
685    PCState pc(new_pc);
686    pc.aarch64(!cpsr.width);
687    pc.nextAArch64(!cpsr.width);
688    tc->pcState(pc);
689
690    // If we have a valid instruction then use it to annotate this fault with
691    // extra information. This is used to generate the correct fault syndrome
692    // information
693    if (inst)
694        static_cast<ArmStaticInst *>(inst.get())->annotateFault(this);
695    // Save exception syndrome
696    if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ))
697        setSyndrome(tc, getSyndromeReg64());
698}
699
700void
701Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst)
702{
703    if (FullSystem) {
704        tc->getCpuPtr()->clearInterrupts(tc->threadId());
705        tc->clearArchRegs();
706    }
707    if (!ArmSystem::highestELIs64(tc)) {
708        ArmFault::invoke(tc, inst);
709        tc->setMiscReg(MISCREG_VMPIDR,
710                       getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc));
711
712        // Unless we have SMC code to get us there, boot in HYP!
713        if (ArmSystem::haveVirtualization(tc) &&
714            !ArmSystem::haveSecurity(tc)) {
715            CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
716            cpsr.mode = MODE_HYP;
717            tc->setMiscReg(MISCREG_CPSR, cpsr);
718        }
719    } else {
720        // Advance the PC to the IMPLEMENTATION DEFINED reset value
721        PCState pc = ArmSystem::resetAddr64(tc);
722        pc.aarch64(true);
723        pc.nextAArch64(true);
724        tc->pcState(pc);
725    }
726}
727
728void
729UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst)
730{
731    if (FullSystem) {
732        ArmFault::invoke(tc, inst);
733        return;
734    }
735
736    // If the mnemonic isn't defined this has to be an unknown instruction.
737    assert(unknown || mnemonic != NULL);
738    if (disabled) {
739        panic("Attempted to execute disabled instruction "
740                "'%s' (inst 0x%08x)", mnemonic, machInst);
741    } else if (unknown) {
742        panic("Attempted to execute unknown instruction (inst 0x%08x)",
743              machInst);
744    } else {
745        panic("Attempted to execute unimplemented instruction "
746                "'%s' (inst 0x%08x)", mnemonic, machInst);
747    }
748}
749
750bool
751UndefinedInstruction::routeToHyp(ThreadContext *tc) const
752{
753    bool toHyp;
754
755    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
756    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
757    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
758
759    // if in Hyp mode then stay in Hyp mode
760    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
761    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
762    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
763    return toHyp;
764}
765
766uint32_t
767UndefinedInstruction::iss() const
768{
769
770    // If UndefinedInstruction is routed to hypervisor, iss field is 0.
771    if (hypRouted) {
772        return 0;
773    }
774
775    if (overrideEc == EC_INVALID)
776        return issRaw;
777
778    uint32_t new_iss = 0;
779    uint32_t op0, op1, op2, CRn, CRm, Rt, dir;
780
781    dir = bits(machInst, 21, 21);
782    op0 = bits(machInst, 20, 19);
783    op1 = bits(machInst, 18, 16);
784    CRn = bits(machInst, 15, 12);
785    CRm = bits(machInst, 11, 8);
786    op2 = bits(machInst, 7, 5);
787    Rt = bits(machInst, 4, 0);
788
789    new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 |
790            Rt << 5 | CRm << 1 | dir;
791
792    return new_iss;
793}
794
795void
796SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
797{
798    if (FullSystem) {
799        ArmFault::invoke(tc, inst);
800        return;
801    }
802
803    // As of now, there isn't a 32 bit thumb version of this instruction.
804    assert(!machInst.bigThumb);
805    uint32_t callNum;
806    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
807    OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode;
808    if (opModeIs64(mode))
809        callNum = tc->readIntReg(INTREG_X8);
810    else
811        callNum = tc->readIntReg(INTREG_R7);
812    Fault fault;
813    tc->syscall(callNum, &fault);
814
815    // Advance the PC since that won't happen automatically.
816    PCState pc = tc->pcState();
817    assert(inst);
818    inst->advancePC(pc);
819    tc->pcState(pc);
820}
821
822bool
823SupervisorCall::routeToHyp(ThreadContext *tc) const
824{
825    bool toHyp;
826
827    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
828    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
829    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
830
831    // if in Hyp mode then stay in Hyp mode
832    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
833    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
834    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER);
835    return toHyp;
836}
837
838ExceptionClass
839SupervisorCall::ec(ThreadContext *tc) const
840{
841    return (overrideEc != EC_INVALID) ? overrideEc :
842        (from64 ? EC_SVC_64 : vals.ec);
843}
844
845uint32_t
846SupervisorCall::iss() const
847{
848    // Even if we have a 24 bit imm from an arm32 instruction then we only use
849    // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC).
850    return issRaw & 0xFFFF;
851}
852
853uint32_t
854SecureMonitorCall::iss() const
855{
856    if (from64)
857        return bits(machInst, 20, 5);
858    return 0;
859}
860
861ExceptionClass
862UndefinedInstruction::ec(ThreadContext *tc) const
863{
864    // If UndefinedInstruction is routed to hypervisor,
865    // HSR.EC field is 0.
866    if (hypRouted)
867        return EC_UNKNOWN;
868    else
869        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
870}
871
872
873HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) :
874        ArmFaultVals<HypervisorCall>(_machInst, _imm)
875{}
876
877ExceptionClass
878HypervisorCall::ec(ThreadContext *tc) const
879{
880    return from64 ? EC_HVC_64 : vals.ec;
881}
882
883ExceptionClass
884HypervisorTrap::ec(ThreadContext *tc) const
885{
886    return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
887}
888
889template<class T>
890FaultOffset
891ArmFaultVals<T>::offset(ThreadContext *tc)
892{
893    bool isHypTrap = false;
894
895    // Normally we just use the exception vector from the table at the top if
896    // this file, however if this exception has caused a transition to hype
897    // mode, and its an exception type that would only do this if it has been
898    // trapped then we use the hyp trap vector instead of the normal vector
899    if (vals.hypTrappable) {
900        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
901        if (cpsr.mode == MODE_HYP) {
902            CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
903            isHypTrap = spsr.mode != MODE_HYP;
904        }
905    }
906    return isHypTrap ? 0x14 : vals.offset;
907}
908
909template<class T>
910FaultOffset
911ArmFaultVals<T>::offset64(ThreadContext *tc)
912{
913    if (toEL == fromEL) {
914        if (opModeIsT(fromMode))
915            return vals.currELTOffset;
916        return vals.currELHOffset;
917    } else {
918        bool lower_32 = false;
919        if (toEL == EL3) {
920            if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2))
921                lower_32 = ELIs32(tc, EL2);
922            else
923                lower_32 = ELIs32(tc, EL1);
924        } else {
925            lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1));
926        }
927
928        if (lower_32)
929            return vals.lowerEL32Offset;
930        return vals.lowerEL64Offset;
931    }
932}
933
934// void
935// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx)
936// {
937//     ESR esr = 0;
938//     esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32;
939//     esr.il = !machInst.thumb;
940//     if (machInst.aarch64)
941//         esr.imm16 = bits(machInst.instBits, 20, 5);
942//     else if (machInst.thumb)
943//         esr.imm16 = bits(machInst.instBits, 7, 0);
944//     else
945//         esr.imm16 = bits(machInst.instBits, 15, 0);
946//     tc->setMiscReg(esr_idx, esr);
947// }
948
949void
950SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst)
951{
952    if (FullSystem) {
953        ArmFault::invoke(tc, inst);
954        return;
955    }
956}
957
958ExceptionClass
959SecureMonitorCall::ec(ThreadContext *tc) const
960{
961    return (from64 ? EC_SMC_64 : vals.ec);
962}
963
964bool
965SupervisorTrap::routeToHyp(ThreadContext *tc) const
966{
967    bool toHyp = false;
968
969    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
970    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
971    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
972
973    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
974    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
975    return toHyp;
976}
977
978uint32_t
979SupervisorTrap::iss() const
980{
981    // If SupervisorTrap is routed to hypervisor, iss field is 0.
982    if (hypRouted) {
983        return 0;
984    }
985    return issRaw;
986}
987
988ExceptionClass
989SupervisorTrap::ec(ThreadContext *tc) const
990{
991    if (hypRouted)
992        return EC_UNKNOWN;
993    else
994        return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
995}
996
997ExceptionClass
998SecureMonitorTrap::ec(ThreadContext *tc) const
999{
1000    return (overrideEc != EC_INVALID) ? overrideEc :
1001        (from64 ? EC_SMC_64 : vals.ec);
1002}
1003
1004template<class T>
1005void
1006AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1007{
1008    if (tranMethod == ArmFault::UnknownTran) {
1009        tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran
1010                                             : ArmFault::VmsaTran;
1011
1012        if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) {
1013            // See ARM ARM B3-1416
1014            bool override_LPAE = false;
1015            TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S);
1016            TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS);
1017            if (ttbcr_s.eae) {
1018                override_LPAE = true;
1019            } else {
1020                // Unimplemented code option, not seen in testing.  May need
1021                // extension according to the manual exceprt above.
1022                DPRINTF(Faults, "Warning: Incomplete translation method "
1023                        "override detected.\n");
1024            }
1025            if (override_LPAE)
1026                tranMethod = ArmFault::LpaeTran;
1027        }
1028    }
1029
1030    if (source == ArmFault::AsynchronousExternalAbort) {
1031        tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1032    }
1033    // Get effective fault source encoding
1034    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1035    FSR  fsr  = getFsr(tc);
1036
1037    // source must be determined BEFORE invoking generic routines which will
1038    // try to set hsr etc. and are based upon source!
1039    ArmFaultVals<T>::invoke(tc, inst);
1040
1041    if (!this->to64) {  // AArch32
1042        if (cpsr.mode == MODE_HYP) {
1043            tc->setMiscReg(T::HFarIndex, faultAddr);
1044        } else if (stage2) {
1045            tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf);
1046            tc->setMiscReg(T::HFarIndex,  OVAddr);
1047        } else {
1048            tc->setMiscReg(T::FsrIndex, fsr);
1049            tc->setMiscReg(T::FarIndex, faultAddr);
1050        }
1051        DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\
1052                "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod);
1053    } else {  // AArch64
1054        // Set the FAR register.  Nothing else to do if we are in AArch64 state
1055        // because the syndrome register has already been set inside invoke64()
1056        if (stage2) {
1057            // stage 2 fault, set HPFAR_EL2 to the faulting IPA
1058            // and FAR_EL2 to the Original VA
1059            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr);
1060            tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4);
1061
1062            DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n",
1063                    OVAddr, faultAddr);
1064        } else {
1065            tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr);
1066        }
1067    }
1068}
1069
1070template<class T>
1071FSR
1072AbortFault<T>::getFsr(ThreadContext *tc)
1073{
1074    FSR fsr = 0;
1075
1076    if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) {
1077        // AArch32
1078        assert(tranMethod != ArmFault::UnknownTran);
1079        if (tranMethod == ArmFault::LpaeTran) {
1080            srcEncoded = ArmFault::longDescFaultSources[source];
1081            fsr.status = srcEncoded;
1082            fsr.lpae   = 1;
1083        } else {
1084            srcEncoded = ArmFault::shortDescFaultSources[source];
1085            fsr.fsLow  = bits(srcEncoded, 3, 0);
1086            fsr.fsHigh = bits(srcEncoded, 4);
1087            fsr.domain = static_cast<uint8_t>(domain);
1088        }
1089        fsr.wnr = (write ? 1 : 0);
1090        fsr.ext = 0;
1091    } else {
1092        // AArch64
1093        srcEncoded = ArmFault::aarch64FaultSources[source];
1094    }
1095    if (srcEncoded == ArmFault::FaultSourceInvalid) {
1096        panic("Invalid fault source\n");
1097    }
1098    return fsr;
1099}
1100
1101template<class T>
1102bool
1103AbortFault<T>::abortDisable(ThreadContext *tc)
1104{
1105    if (ArmSystem::haveSecurity(tc)) {
1106        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1107        return (!scr.ns || scr.aw);
1108    }
1109    return true;
1110}
1111
1112template<class T>
1113void
1114AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val)
1115{
1116    switch (id)
1117    {
1118      case ArmFault::S1PTW:
1119        s1ptw = val;
1120        break;
1121      case ArmFault::OVA:
1122        OVAddr = val;
1123        break;
1124
1125      // Just ignore unknown ID's
1126      default:
1127        break;
1128    }
1129}
1130
1131template<class T>
1132uint32_t
1133AbortFault<T>::iss() const
1134{
1135    uint32_t val;
1136
1137    val  = srcEncoded & 0x3F;
1138    val |= write << 6;
1139    val |= s1ptw << 7;
1140    return (val);
1141}
1142
1143template<class T>
1144bool
1145AbortFault<T>::isMMUFault() const
1146{
1147    // NOTE: Not relying on LL information being aligned to lowest bits here
1148    return
1149         (source == ArmFault::AlignmentFault)     ||
1150        ((source >= ArmFault::TranslationLL) &&
1151         (source <  ArmFault::TranslationLL + 4)) ||
1152        ((source >= ArmFault::AccessFlagLL) &&
1153         (source <  ArmFault::AccessFlagLL + 4))  ||
1154        ((source >= ArmFault::DomainLL) &&
1155         (source <  ArmFault::DomainLL + 4))      ||
1156        ((source >= ArmFault::PermissionLL) &&
1157         (source <  ArmFault::PermissionLL + 4));
1158}
1159
1160ExceptionClass
1161PrefetchAbort::ec(ThreadContext *tc) const
1162{
1163    if (to64) {
1164        // AArch64
1165        if (toEL == fromEL)
1166            return EC_PREFETCH_ABORT_CURR_EL;
1167        else
1168            return EC_PREFETCH_ABORT_LOWER_EL;
1169    } else {
1170        // AArch32
1171        // Abort faults have different EC codes depending on whether
1172        // the fault originated within HYP mode, or not. So override
1173        // the method and add the extra adjustment of the EC value.
1174
1175        ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec;
1176
1177        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1178        if (spsr.mode == MODE_HYP) {
1179            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1180        }
1181        return ec;
1182    }
1183}
1184
1185bool
1186PrefetchAbort::routeToMonitor(ThreadContext *tc) const
1187{
1188    SCR scr = 0;
1189    if (from64)
1190        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1191    else
1192        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1193
1194    return scr.ea && !isMMUFault();
1195}
1196
1197bool
1198PrefetchAbort::routeToHyp(ThreadContext *tc) const
1199{
1200    bool toHyp;
1201
1202    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1203    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1204    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1205    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1206
1207    // if in Hyp mode then stay in Hyp mode
1208    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1209    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1210    toHyp |= (stage2 ||
1211                ( (source ==               DebugEvent) && hdcr.tde && (cpsr.mode !=  MODE_HYP)) ||
1212                ( (source == SynchronousExternalAbort) && hcr.tge  && (cpsr.mode == MODE_USER))
1213             ) && !inSecureState(tc);
1214    return toHyp;
1215}
1216
1217ExceptionClass
1218DataAbort::ec(ThreadContext *tc) const
1219{
1220    if (to64) {
1221        // AArch64
1222        if (source == ArmFault::AsynchronousExternalAbort) {
1223            panic("Asynchronous External Abort should be handled with "
1224                    "SystemErrors (SErrors)!");
1225        }
1226        if (toEL == fromEL)
1227            return EC_DATA_ABORT_CURR_EL;
1228        else
1229            return EC_DATA_ABORT_LOWER_EL;
1230    } else {
1231        // AArch32
1232        // Abort faults have different EC codes depending on whether
1233        // the fault originated within HYP mode, or not. So override
1234        // the method and add the extra adjustment of the EC value.
1235
1236        ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec;
1237
1238        CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP);
1239        if (spsr.mode == MODE_HYP) {
1240            ec = ((ExceptionClass) (((uint32_t) ec) + 1));
1241        }
1242        return ec;
1243    }
1244}
1245
1246bool
1247DataAbort::routeToMonitor(ThreadContext *tc) const
1248{
1249    SCR scr = 0;
1250    if (from64)
1251        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1252    else
1253        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1254
1255    return scr.ea && !isMMUFault();
1256}
1257
1258bool
1259DataAbort::routeToHyp(ThreadContext *tc) const
1260{
1261    bool toHyp;
1262
1263    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1264    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1265    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1266    HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR);
1267
1268    // if in Hyp mode then stay in Hyp mode
1269    toHyp  = scr.ns && (cpsr.mode == MODE_HYP);
1270    // otherwise, check whether to take to Hyp mode through Hyp Trap vector
1271    toHyp |= (stage2 ||
1272                ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) ||
1273                                               ((source == DebugEvent) && hdcr.tde) )
1274                ) ||
1275                ( (cpsr.mode == MODE_USER) && hcr.tge &&
1276                  ((source == AlignmentFault)            ||
1277                   (source == SynchronousExternalAbort))
1278                )
1279             ) && !inSecureState(tc);
1280    return toHyp;
1281}
1282
1283uint32_t
1284DataAbort::iss() const
1285{
1286    uint32_t val;
1287
1288    // Add on the data abort specific fields to the generic abort ISS value
1289    val  = AbortFault<DataAbort>::iss();
1290    // ISS is valid if not caused by a stage 1 page table walk, and when taken
1291    // to AArch64 only when directed to EL2
1292    if (!s1ptw && (!to64 || toEL == EL2)) {
1293        val |= isv << 24;
1294        if (isv) {
1295            val |= sas << 22;
1296            val |= sse << 21;
1297            val |= srt << 16;
1298            // AArch64 only. These assignments are safe on AArch32 as well
1299            // because these vars are initialized to false
1300            val |= sf << 15;
1301            val |= ar << 14;
1302        }
1303    }
1304    return (val);
1305}
1306
1307void
1308DataAbort::annotate(AnnotationIDs id, uint64_t val)
1309{
1310    AbortFault<DataAbort>::annotate(id, val);
1311    switch (id)
1312    {
1313      case SAS:
1314        isv = true;
1315        sas = val;
1316        break;
1317      case SSE:
1318        isv = true;
1319        sse = val;
1320        break;
1321      case SRT:
1322        isv = true;
1323        srt = val;
1324        break;
1325      case SF:
1326        isv = true;
1327        sf  = val;
1328        break;
1329      case AR:
1330        isv = true;
1331        ar  = val;
1332        break;
1333      // Just ignore unknown ID's
1334      default:
1335        break;
1336    }
1337}
1338
1339void
1340VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1341{
1342    AbortFault<VirtualDataAbort>::invoke(tc, inst);
1343    HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR);
1344    hcr.va = 0;
1345    tc->setMiscRegNoEffect(MISCREG_HCR, hcr);
1346}
1347
1348bool
1349Interrupt::routeToMonitor(ThreadContext *tc) const
1350{
1351    assert(ArmSystem::haveSecurity(tc));
1352    SCR scr = 0;
1353    if (from64)
1354        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1355    else
1356        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1357    return scr.irq;
1358}
1359
1360bool
1361Interrupt::routeToHyp(ThreadContext *tc) const
1362{
1363    bool toHyp;
1364
1365    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1366    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1367    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1368    // Determine whether IRQs are routed to Hyp mode.
1369    toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) ||
1370            (cpsr.mode == MODE_HYP);
1371    return toHyp;
1372}
1373
1374bool
1375Interrupt::abortDisable(ThreadContext *tc)
1376{
1377    if (ArmSystem::haveSecurity(tc)) {
1378        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1379        return (!scr.ns || scr.aw);
1380    }
1381    return true;
1382}
1383
1384VirtualInterrupt::VirtualInterrupt()
1385{}
1386
1387bool
1388FastInterrupt::routeToMonitor(ThreadContext *tc) const
1389{
1390    assert(ArmSystem::haveSecurity(tc));
1391    SCR scr = 0;
1392    if (from64)
1393        scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1394    else
1395        scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1396    return scr.fiq;
1397}
1398
1399bool
1400FastInterrupt::routeToHyp(ThreadContext *tc) const
1401{
1402    bool toHyp;
1403
1404    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR);
1405    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1406    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1407    // Determine whether IRQs are routed to Hyp mode.
1408    toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) ||
1409            (cpsr.mode == MODE_HYP);
1410    return toHyp;
1411}
1412
1413bool
1414FastInterrupt::abortDisable(ThreadContext *tc)
1415{
1416    if (ArmSystem::haveSecurity(tc)) {
1417        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1418        return (!scr.ns || scr.aw);
1419    }
1420    return true;
1421}
1422
1423bool
1424FastInterrupt::fiqDisable(ThreadContext *tc)
1425{
1426    if (ArmSystem::haveVirtualization(tc)) {
1427        return true;
1428    } else if (ArmSystem::haveSecurity(tc)) {
1429        SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR);
1430        return (!scr.ns || scr.fw);
1431    }
1432    return true;
1433}
1434
1435VirtualFastInterrupt::VirtualFastInterrupt()
1436{}
1437
1438void
1439PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1440{
1441    ArmFaultVals<PCAlignmentFault>::invoke(tc, inst);
1442    assert(from64);
1443    // Set the FAR
1444    tc->setMiscReg(getFaultAddrReg64(), faultPC);
1445}
1446
1447bool
1448PCAlignmentFault::routeToHyp(ThreadContext *tc) const
1449{
1450    bool toHyp = false;
1451
1452    SCR  scr  = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1453    HCR  hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1454    CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
1455
1456    // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector
1457    toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0);
1458    return toHyp;
1459}
1460
1461SPAlignmentFault::SPAlignmentFault()
1462{}
1463
1464SystemError::SystemError()
1465{}
1466
1467void
1468SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst)
1469{
1470    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0);
1471    ArmFault::invoke(tc, inst);
1472}
1473
1474bool
1475SystemError::routeToMonitor(ThreadContext *tc) const
1476{
1477    assert(ArmSystem::haveSecurity(tc));
1478    assert(from64);
1479    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1480    return scr.ea;
1481}
1482
1483bool
1484SystemError::routeToHyp(ThreadContext *tc) const
1485{
1486    bool toHyp;
1487    assert(from64);
1488
1489    SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3);
1490    HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR);
1491
1492    toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) ||
1493            (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc));
1494    return toHyp;
1495}
1496
1497
1498SoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss)
1499    : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss)
1500{}
1501
1502bool
1503SoftwareBreakpoint::routeToHyp(ThreadContext *tc) const
1504{
1505    assert(from64);
1506
1507    const bool have_el2 = ArmSystem::haveVirtualization(tc);
1508
1509    const HCR hcr  = tc->readMiscRegNoEffect(MISCREG_HCR_EL2);
1510    const HDCR mdcr  = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
1511
1512    return have_el2 && !inSecureState(tc) && fromEL <= EL1 &&
1513        (hcr.tge || mdcr.tde);
1514}
1515
1516void
1517ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) {
1518    DPRINTF(Faults, "Invoking ArmSev Fault\n");
1519    if (!FullSystem)
1520        return;
1521
1522    // Set sev_mailbox to 1, clear the pending interrupt from remote
1523    // SEV execution and let pipeline continue as pcState is still
1524    // valid.
1525    tc->setMiscReg(MISCREG_SEV_MAILBOX, 1);
1526    tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0);
1527}
1528
1529// Instantiate all the templates to make the linker happy
1530template class ArmFaultVals<Reset>;
1531template class ArmFaultVals<UndefinedInstruction>;
1532template class ArmFaultVals<SupervisorCall>;
1533template class ArmFaultVals<SecureMonitorCall>;
1534template class ArmFaultVals<HypervisorCall>;
1535template class ArmFaultVals<PrefetchAbort>;
1536template class ArmFaultVals<DataAbort>;
1537template class ArmFaultVals<VirtualDataAbort>;
1538template class ArmFaultVals<HypervisorTrap>;
1539template class ArmFaultVals<Interrupt>;
1540template class ArmFaultVals<VirtualInterrupt>;
1541template class ArmFaultVals<FastInterrupt>;
1542template class ArmFaultVals<VirtualFastInterrupt>;
1543template class ArmFaultVals<SupervisorTrap>;
1544template class ArmFaultVals<SecureMonitorTrap>;
1545template class ArmFaultVals<PCAlignmentFault>;
1546template class ArmFaultVals<SPAlignmentFault>;
1547template class ArmFaultVals<SystemError>;
1548template class ArmFaultVals<SoftwareBreakpoint>;
1549template class ArmFaultVals<ArmSev>;
1550template class AbortFault<PrefetchAbort>;
1551template class AbortFault<DataAbort>;
1552template class AbortFault<VirtualDataAbort>;
1553
1554
1555IllegalInstSetStateFault::IllegalInstSetStateFault()
1556{}
1557
1558
1559} // namespace ArmISA
1560