faults.cc revision 8063
16019Shines@cs.fsu.edu/*
27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited
37093Sgblack@eecs.umich.edu * All rights reserved
47093Sgblack@eecs.umich.edu *
57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall
67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual
77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating
87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software
97093Sgblack@eecs.umich.edu * licensed hereunder.  You may use the software subject to the license
107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated
117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software,
127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form.
137093Sgblack@eecs.umich.edu *
146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University
166019Shines@cs.fsu.edu * All rights reserved.
176019Shines@cs.fsu.edu *
186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
276019Shines@cs.fsu.edu * this software without specific prior written permission.
286019Shines@cs.fsu.edu *
296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019Shines@cs.fsu.edu *
416735Sgblack@eecs.umich.edu * Authors: Ali Saidi
426735Sgblack@eecs.umich.edu *          Gabe Black
436019Shines@cs.fsu.edu */
446019Shines@cs.fsu.edu
456019Shines@cs.fsu.edu#include "arch/arm/faults.hh"
466019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
476019Shines@cs.fsu.edu#include "cpu/base.hh"
486019Shines@cs.fsu.edu#include "base/trace.hh"
496019Shines@cs.fsu.edu
506019Shines@cs.fsu.edunamespace ArmISA
516019Shines@cs.fsu.edu{
526019Shines@cs.fsu.edu
537362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals =
546735Sgblack@eecs.umich.edu    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
556019Shines@cs.fsu.edu
567362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals =
576735Sgblack@eecs.umich.edu    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
586019Shines@cs.fsu.edu
597362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals =
606735Sgblack@eecs.umich.edu    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
616019Shines@cs.fsu.edu
627362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals =
636735Sgblack@eecs.umich.edu    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
646019Shines@cs.fsu.edu
657362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals =
666735Sgblack@eecs.umich.edu    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
676019Shines@cs.fsu.edu
687362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals =
696735Sgblack@eecs.umich.edu    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
706019Shines@cs.fsu.edu
717362Sgblack@eecs.umich.edutemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals =
726735Sgblack@eecs.umich.edu    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
736019Shines@cs.fsu.edu
747652Sminkyu.jeong@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals =
757652Sminkyu.jeong@arm.com    {"Pipe Flush", 0x00, MODE_SVC, 0, 0, true, true}; // some dummy values
767652Sminkyu.jeong@arm.com
776735Sgblack@eecs.umich.eduAddr
787362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc)
796735Sgblack@eecs.umich.edu{
806735Sgblack@eecs.umich.edu    // ARM ARM B1-3
816019Shines@cs.fsu.edu
826735Sgblack@eecs.umich.edu    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
837400SAli.Saidi@ARM.com
846735Sgblack@eecs.umich.edu    // panic if SCTLR.VE because I have no idea what to do with vectored
856735Sgblack@eecs.umich.edu    // interrupts
866735Sgblack@eecs.umich.edu    assert(!sctlr.ve);
877400SAli.Saidi@ARM.com
886735Sgblack@eecs.umich.edu    if (!sctlr.v)
896735Sgblack@eecs.umich.edu        return offset();
906735Sgblack@eecs.umich.edu    return offset() + HighVecs;
916019Shines@cs.fsu.edu
926019Shines@cs.fsu.edu}
936019Shines@cs.fsu.edu
946735Sgblack@eecs.umich.edu#if FULL_SYSTEM
956735Sgblack@eecs.umich.edu
966735Sgblack@eecs.umich.eduvoid
977678Sgblack@eecs.umich.eduArmFault::invoke(ThreadContext *tc, StaticInstPtr inst)
986019Shines@cs.fsu.edu{
996735Sgblack@eecs.umich.edu    // ARM ARM B1.6.3
1006735Sgblack@eecs.umich.edu    FaultBase::invoke(tc);
1016735Sgblack@eecs.umich.edu    countStat()++;
1026019Shines@cs.fsu.edu
1036735Sgblack@eecs.umich.edu    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
1046735Sgblack@eecs.umich.edu    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1056735Sgblack@eecs.umich.edu    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
1066735Sgblack@eecs.umich.edu                      tc->readIntReg(INTREG_CONDCODES);
1077720Sgblack@eecs.umich.edu    Addr curPc M5_VAR_USED = tc->pcState().pc();
1086735Sgblack@eecs.umich.edu
1096735Sgblack@eecs.umich.edu
1106735Sgblack@eecs.umich.edu    cpsr.mode = nextMode();
1116735Sgblack@eecs.umich.edu    cpsr.it1 = cpsr.it2 = 0;
1126735Sgblack@eecs.umich.edu    cpsr.j = 0;
1136735Sgblack@eecs.umich.edu
1147093Sgblack@eecs.umich.edu    cpsr.t = sctlr.te;
1156735Sgblack@eecs.umich.edu    cpsr.a = cpsr.a | abortDisable();
1166735Sgblack@eecs.umich.edu    cpsr.f = cpsr.f | fiqDisable();
1176735Sgblack@eecs.umich.edu    cpsr.i = 1;
1187302Sgblack@eecs.umich.edu    cpsr.e = sctlr.ee;
1196735Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CPSR, cpsr);
1207720Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_LR, curPc +
1216735Sgblack@eecs.umich.edu            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
1226735Sgblack@eecs.umich.edu
1236735Sgblack@eecs.umich.edu    switch (nextMode()) {
1246735Sgblack@eecs.umich.edu      case MODE_FIQ:
1256735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
1266735Sgblack@eecs.umich.edu        break;
1276735Sgblack@eecs.umich.edu      case MODE_IRQ:
1286735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
1296735Sgblack@eecs.umich.edu        break;
1306735Sgblack@eecs.umich.edu      case MODE_SVC:
1316735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
1326735Sgblack@eecs.umich.edu        break;
1336735Sgblack@eecs.umich.edu      case MODE_UNDEFINED:
1346735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
1356735Sgblack@eecs.umich.edu        break;
1366735Sgblack@eecs.umich.edu      case MODE_ABORT:
1376735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
1386735Sgblack@eecs.umich.edu        break;
1396735Sgblack@eecs.umich.edu      default:
1406735Sgblack@eecs.umich.edu        panic("unknown Mode\n");
1417093Sgblack@eecs.umich.edu    }
1427093Sgblack@eecs.umich.edu
1437720Sgblack@eecs.umich.edu    Addr newPc = getVector(tc);
1447585SAli.Saidi@arm.com    DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n",
1457720Sgblack@eecs.umich.edu            name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc);
1467720Sgblack@eecs.umich.edu    PCState pc(newPc);
1477720Sgblack@eecs.umich.edu    pc.thumb(cpsr.t);
1487720Sgblack@eecs.umich.edu    pc.nextThumb(pc.thumb());
1497720Sgblack@eecs.umich.edu    pc.jazelle(cpsr.j);
1507720Sgblack@eecs.umich.edu    pc.nextJazelle(pc.jazelle());
1517720Sgblack@eecs.umich.edu    tc->pcState(pc);
1526019Shines@cs.fsu.edu}
1537189Sgblack@eecs.umich.edu
1547400SAli.Saidi@ARM.comvoid
1557678Sgblack@eecs.umich.eduReset::invoke(ThreadContext *tc, StaticInstPtr inst)
1567400SAli.Saidi@ARM.com{
1577400SAli.Saidi@ARM.com    tc->getCpuPtr()->clearInterrupts();
1587400SAli.Saidi@ARM.com    tc->clearArchRegs();
1597400SAli.Saidi@ARM.com    ArmFault::invoke(tc);
1607400SAli.Saidi@ARM.com}
1617400SAli.Saidi@ARM.com
1627189Sgblack@eecs.umich.edu#else
1637189Sgblack@eecs.umich.edu
1647189Sgblack@eecs.umich.eduvoid
1657678Sgblack@eecs.umich.eduUndefinedInstruction::invoke(ThreadContext *tc, StaticInstPtr inst)
1667189Sgblack@eecs.umich.edu{
1677640Sgblack@eecs.umich.edu    // If the mnemonic isn't defined this has to be an unknown instruction.
1687189Sgblack@eecs.umich.edu    assert(unknown || mnemonic != NULL);
1697640Sgblack@eecs.umich.edu    if (disabled) {
1707640Sgblack@eecs.umich.edu        panic("Attempted to execute disabled instruction "
1717640Sgblack@eecs.umich.edu                "'%s' (inst 0x%08x)", mnemonic, machInst);
1727640Sgblack@eecs.umich.edu    } else if (unknown) {
1737426Sgblack@eecs.umich.edu        panic("Attempted to execute unknown instruction (inst 0x%08x)",
1747426Sgblack@eecs.umich.edu              machInst);
1757189Sgblack@eecs.umich.edu    } else {
1767426Sgblack@eecs.umich.edu        panic("Attempted to execute unimplemented instruction "
1777426Sgblack@eecs.umich.edu                "'%s' (inst 0x%08x)", mnemonic, machInst);
1787189Sgblack@eecs.umich.edu    }
1797189Sgblack@eecs.umich.edu}
1807189Sgblack@eecs.umich.edu
1817197Sgblack@eecs.umich.eduvoid
1827678Sgblack@eecs.umich.eduSupervisorCall::invoke(ThreadContext *tc, StaticInstPtr inst)
1837197Sgblack@eecs.umich.edu{
1847197Sgblack@eecs.umich.edu    // As of now, there isn't a 32 bit thumb version of this instruction.
1857197Sgblack@eecs.umich.edu    assert(!machInst.bigThumb);
1867197Sgblack@eecs.umich.edu    uint32_t callNum;
1878063SAli.Saidi@ARM.com    callNum = tc->readIntReg(INTREG_R7);
1887197Sgblack@eecs.umich.edu    tc->syscall(callNum);
1897197Sgblack@eecs.umich.edu
1907197Sgblack@eecs.umich.edu    // Advance the PC since that won't happen automatically.
1917720Sgblack@eecs.umich.edu    PCState pc = tc->pcState();
1927720Sgblack@eecs.umich.edu    assert(inst);
1937720Sgblack@eecs.umich.edu    inst->advancePC(pc);
1947720Sgblack@eecs.umich.edu    tc->pcState(pc);
1957197Sgblack@eecs.umich.edu}
1967197Sgblack@eecs.umich.edu
1976019Shines@cs.fsu.edu#endif // FULL_SYSTEM
1986019Shines@cs.fsu.edu
1997362Sgblack@eecs.umich.edutemplate<class T>
2007362Sgblack@eecs.umich.eduvoid
2017678Sgblack@eecs.umich.eduAbortFault<T>::invoke(ThreadContext *tc, StaticInstPtr inst)
2027362Sgblack@eecs.umich.edu{
2037362Sgblack@eecs.umich.edu    ArmFaultVals<T>::invoke(tc);
2047362Sgblack@eecs.umich.edu    FSR fsr = 0;
2057362Sgblack@eecs.umich.edu    fsr.fsLow = bits(status, 3, 0);
2067362Sgblack@eecs.umich.edu    fsr.fsHigh = bits(status, 4);
2077362Sgblack@eecs.umich.edu    fsr.domain = domain;
2087362Sgblack@eecs.umich.edu    fsr.wnr = (write ? 1 : 0);
2097362Sgblack@eecs.umich.edu    fsr.ext = 0;
2107362Sgblack@eecs.umich.edu    tc->setMiscReg(T::FsrIndex, fsr);
2117362Sgblack@eecs.umich.edu    tc->setMiscReg(T::FarIndex, faultAddr);
2127362Sgblack@eecs.umich.edu}
2137362Sgblack@eecs.umich.edu
2147652Sminkyu.jeong@arm.comvoid
2157678Sgblack@eecs.umich.eduFlushPipe::invoke(ThreadContext *tc, StaticInstPtr inst) {
2167652Sminkyu.jeong@arm.com    DPRINTF(Faults, "Invoking FlushPipe Fault\n");
2177652Sminkyu.jeong@arm.com
2187652Sminkyu.jeong@arm.com    // Set the PC to the next instruction of the faulting instruction.
2197652Sminkyu.jeong@arm.com    // Net effect is simply squashing all instructions behind and
2207652Sminkyu.jeong@arm.com    // start refetching from the next instruction.
2217720Sgblack@eecs.umich.edu    PCState pc = tc->pcState();
2227720Sgblack@eecs.umich.edu    assert(inst);
2237720Sgblack@eecs.umich.edu    inst->advancePC(pc);
2247720Sgblack@eecs.umich.edu    tc->pcState(pc);
2257652Sminkyu.jeong@arm.com}
2267652Sminkyu.jeong@arm.com
2277678Sgblack@eecs.umich.edutemplate void AbortFault<PrefetchAbort>::invoke(ThreadContext *tc,
2287678Sgblack@eecs.umich.edu                                                StaticInstPtr inst);
2297678Sgblack@eecs.umich.edutemplate void AbortFault<DataAbort>::invoke(ThreadContext *tc,
2307678Sgblack@eecs.umich.edu                                            StaticInstPtr inst);
2317362Sgblack@eecs.umich.edu
2326735Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm
2336019Shines@cs.fsu.edu
2346019Shines@cs.fsu.edu} // namespace ArmISA
235