faults.cc revision 7302
16019Shines@cs.fsu.edu/*
27093Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited
37093Sgblack@eecs.umich.edu * All rights reserved
47093Sgblack@eecs.umich.edu *
57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall
67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual
77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating
87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software
97093Sgblack@eecs.umich.edu * licensed hereunder.  You may use the software subject to the license
107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated
117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software,
127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form.
137093Sgblack@eecs.umich.edu *
146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan
156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University
166019Shines@cs.fsu.edu * All rights reserved.
176019Shines@cs.fsu.edu *
186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without
196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are
206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright
216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer;
226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright
236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the
246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution;
256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its
266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from
276019Shines@cs.fsu.edu * this software without specific prior written permission.
286019Shines@cs.fsu.edu *
296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
406019Shines@cs.fsu.edu *
416735Sgblack@eecs.umich.edu * Authors: Ali Saidi
426735Sgblack@eecs.umich.edu *          Gabe Black
436019Shines@cs.fsu.edu */
446019Shines@cs.fsu.edu
456019Shines@cs.fsu.edu#include "arch/arm/faults.hh"
466019Shines@cs.fsu.edu#include "cpu/thread_context.hh"
476019Shines@cs.fsu.edu#include "cpu/base.hh"
486019Shines@cs.fsu.edu#include "base/trace.hh"
496019Shines@cs.fsu.edu
506019Shines@cs.fsu.edunamespace ArmISA
516019Shines@cs.fsu.edu{
526019Shines@cs.fsu.edu
536735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Reset>::vals =
546735Sgblack@eecs.umich.edu    {"reset", 0x00, MODE_SVC, 0, 0, true, true};
556019Shines@cs.fsu.edu
566735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals =
576735Sgblack@eecs.umich.edu    {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ;
586019Shines@cs.fsu.edu
596735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals =
606735Sgblack@eecs.umich.edu    {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false};
616019Shines@cs.fsu.edu
626735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals =
636735Sgblack@eecs.umich.edu    {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false};
646019Shines@cs.fsu.edu
656735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals =
666735Sgblack@eecs.umich.edu    {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false};
676019Shines@cs.fsu.edu
686735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals =
696735Sgblack@eecs.umich.edu    {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false};
706019Shines@cs.fsu.edu
716735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals =
726735Sgblack@eecs.umich.edu    {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true};
736019Shines@cs.fsu.edu
746735Sgblack@eecs.umich.eduAddr
756735Sgblack@eecs.umich.eduArmFaultBase::getVector(ThreadContext *tc)
766735Sgblack@eecs.umich.edu{
776735Sgblack@eecs.umich.edu    // ARM ARM B1-3
786019Shines@cs.fsu.edu
796735Sgblack@eecs.umich.edu    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
806735Sgblack@eecs.umich.edu
816735Sgblack@eecs.umich.edu    // panic if SCTLR.VE because I have no idea what to do with vectored
826735Sgblack@eecs.umich.edu    // interrupts
836735Sgblack@eecs.umich.edu    assert(!sctlr.ve);
846735Sgblack@eecs.umich.edu
856735Sgblack@eecs.umich.edu    if (!sctlr.v)
866735Sgblack@eecs.umich.edu        return offset();
876735Sgblack@eecs.umich.edu    return offset() + HighVecs;
886019Shines@cs.fsu.edu
896019Shines@cs.fsu.edu}
906019Shines@cs.fsu.edu
916735Sgblack@eecs.umich.edu#if FULL_SYSTEM
926735Sgblack@eecs.umich.edu
936735Sgblack@eecs.umich.eduvoid
946735Sgblack@eecs.umich.eduArmFaultBase::invoke(ThreadContext *tc)
956019Shines@cs.fsu.edu{
966735Sgblack@eecs.umich.edu    // ARM ARM B1.6.3
976735Sgblack@eecs.umich.edu    FaultBase::invoke(tc);
986735Sgblack@eecs.umich.edu    countStat()++;
996019Shines@cs.fsu.edu
1006735Sgblack@eecs.umich.edu    SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR);
1016735Sgblack@eecs.umich.edu    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
1026735Sgblack@eecs.umich.edu    CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) |
1036735Sgblack@eecs.umich.edu                      tc->readIntReg(INTREG_CONDCODES);
1046735Sgblack@eecs.umich.edu
1056735Sgblack@eecs.umich.edu
1066735Sgblack@eecs.umich.edu    cpsr.mode = nextMode();
1076735Sgblack@eecs.umich.edu    cpsr.it1 = cpsr.it2 = 0;
1086735Sgblack@eecs.umich.edu    cpsr.j = 0;
1096735Sgblack@eecs.umich.edu
1107093Sgblack@eecs.umich.edu    cpsr.t = sctlr.te;
1116735Sgblack@eecs.umich.edu    cpsr.a = cpsr.a | abortDisable();
1126735Sgblack@eecs.umich.edu    cpsr.f = cpsr.f | fiqDisable();
1136735Sgblack@eecs.umich.edu    cpsr.i = 1;
1147302Sgblack@eecs.umich.edu    cpsr.e = sctlr.ee;
1156735Sgblack@eecs.umich.edu    tc->setMiscReg(MISCREG_CPSR, cpsr);
1166735Sgblack@eecs.umich.edu    tc->setIntReg(INTREG_LR, tc->readPC() +
1176735Sgblack@eecs.umich.edu            (saved_cpsr.t ? thumbPcOffset() : armPcOffset()));
1186735Sgblack@eecs.umich.edu
1196735Sgblack@eecs.umich.edu    switch (nextMode()) {
1206735Sgblack@eecs.umich.edu      case MODE_FIQ:
1216735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr);
1226735Sgblack@eecs.umich.edu        break;
1236735Sgblack@eecs.umich.edu      case MODE_IRQ:
1246735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr);
1256735Sgblack@eecs.umich.edu        break;
1266735Sgblack@eecs.umich.edu      case MODE_SVC:
1276735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr);
1286735Sgblack@eecs.umich.edu        break;
1296735Sgblack@eecs.umich.edu      case MODE_UNDEFINED:
1306735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
1316735Sgblack@eecs.umich.edu        break;
1326735Sgblack@eecs.umich.edu      case MODE_ABORT:
1336735Sgblack@eecs.umich.edu        tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr);
1346735Sgblack@eecs.umich.edu        break;
1356735Sgblack@eecs.umich.edu      default:
1366735Sgblack@eecs.umich.edu        panic("unknown Mode\n");
1377093Sgblack@eecs.umich.edu    }
1387093Sgblack@eecs.umich.edu
1397093Sgblack@eecs.umich.edu    Addr pc = tc->readPC();
1407093Sgblack@eecs.umich.edu    DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n",
1417093Sgblack@eecs.umich.edu            name(), cpsr, pc, tc->readIntReg(INTREG_LR));
1427093Sgblack@eecs.umich.edu    Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0);
1437093Sgblack@eecs.umich.edu    tc->setPC(newPc);
1447093Sgblack@eecs.umich.edu    tc->setNextPC(newPc + cpsr.t ? 2 : 4 );
1457295Sgblack@eecs.umich.edu    tc->setMicroPC(0);
1466019Shines@cs.fsu.edu}
1477189Sgblack@eecs.umich.edu
1487189Sgblack@eecs.umich.edu#else
1497189Sgblack@eecs.umich.edu
1507189Sgblack@eecs.umich.eduvoid
1517189Sgblack@eecs.umich.eduUndefinedInstruction::invoke(ThreadContext *tc)
1527189Sgblack@eecs.umich.edu{
1537189Sgblack@eecs.umich.edu    assert(unknown || mnemonic != NULL);
1547189Sgblack@eecs.umich.edu    if (unknown) {
1557189Sgblack@eecs.umich.edu        panic("Attempted to execute unknown instruction "
1567189Sgblack@eecs.umich.edu              "(inst 0x%08x, opcode 0x%x, binary:%s)",
1577189Sgblack@eecs.umich.edu              machInst, machInst.opcode, inst2string(machInst));
1587189Sgblack@eecs.umich.edu    } else {
1597189Sgblack@eecs.umich.edu        panic("Attempted to execute unimplemented instruction '%s' "
1607189Sgblack@eecs.umich.edu              "(inst 0x%08x, opcode 0x%x, binary:%s)",
1617189Sgblack@eecs.umich.edu              mnemonic, machInst, machInst.opcode, inst2string(machInst));
1627189Sgblack@eecs.umich.edu    }
1637189Sgblack@eecs.umich.edu}
1647189Sgblack@eecs.umich.edu
1657197Sgblack@eecs.umich.eduvoid
1667197Sgblack@eecs.umich.eduSupervisorCall::invoke(ThreadContext *tc)
1677197Sgblack@eecs.umich.edu{
1687197Sgblack@eecs.umich.edu    // As of now, there isn't a 32 bit thumb version of this instruction.
1697197Sgblack@eecs.umich.edu    assert(!machInst.bigThumb);
1707197Sgblack@eecs.umich.edu    uint32_t callNum;
1717197Sgblack@eecs.umich.edu    if (machInst.thumb) {
1727197Sgblack@eecs.umich.edu        callNum = bits(machInst, 7, 0);
1737197Sgblack@eecs.umich.edu    } else {
1747197Sgblack@eecs.umich.edu        callNum = bits(machInst, 23, 0);
1757197Sgblack@eecs.umich.edu    }
1767197Sgblack@eecs.umich.edu    if (callNum == 0) {
1777197Sgblack@eecs.umich.edu        callNum = tc->readIntReg(INTREG_R7);
1787197Sgblack@eecs.umich.edu    }
1797197Sgblack@eecs.umich.edu    tc->syscall(callNum);
1807197Sgblack@eecs.umich.edu
1817197Sgblack@eecs.umich.edu    // Advance the PC since that won't happen automatically.
1827197Sgblack@eecs.umich.edu    tc->setPC(tc->readNextPC());
1837197Sgblack@eecs.umich.edu    tc->setNextPC(tc->readNextNPC());
1847197Sgblack@eecs.umich.edu}
1857197Sgblack@eecs.umich.edu
1866019Shines@cs.fsu.edu#endif // FULL_SYSTEM
1876019Shines@cs.fsu.edu
1886735Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm
1896019Shines@cs.fsu.edu
1906019Shines@cs.fsu.edu
1916019Shines@cs.fsu.edu
1926019Shines@cs.fsu.edu} // namespace ArmISA
1936019Shines@cs.fsu.edu
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