faults.cc revision 7093
12131SN/A/* 25268Sksewell@umich.edu * Copyright (c) 2010 ARM Limited 35254Sksewell@umich.edu * All rights reserved 45254Sksewell@umich.edu * 52131SN/A * The license below extends only to copyright in the software and shall 65254Sksewell@umich.edu * not be construed as granting a license to any other intellectual 75254Sksewell@umich.edu * property including but not limited to intellectual property relating 85254Sksewell@umich.edu * to a hardware implementation of the functionality of the software 95254Sksewell@umich.edu * licensed hereunder. You may use the software subject to the license 105254Sksewell@umich.edu * terms below provided that you ensure that this notice is replicated 115254Sksewell@umich.edu * unmodified and in its entirety in all distributions of the software, 125254Sksewell@umich.edu * modified or unmodified, in source code or in binary form. 135254Sksewell@umich.edu * 145254Sksewell@umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 155254Sksewell@umich.edu * Copyright (c) 2007-2008 The Florida State University 162131SN/A * All rights reserved. 175254Sksewell@umich.edu * 185254Sksewell@umich.edu * Redistribution and use in source and binary forms, with or without 195254Sksewell@umich.edu * modification, are permitted provided that the following conditions are 205254Sksewell@umich.edu * met: redistributions of source code must retain the above copyright 215254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer; 225254Sksewell@umich.edu * redistributions in binary form must reproduce the above copyright 235254Sksewell@umich.edu * notice, this list of conditions and the following disclaimer in the 245254Sksewell@umich.edu * documentation and/or other materials provided with the distribution; 255254Sksewell@umich.edu * neither the name of the copyright holders nor the names of its 265254Sksewell@umich.edu * contributors may be used to endorse or promote products derived from 275254Sksewell@umich.edu * this software without specific prior written permission. 282665Ssaidi@eecs.umich.edu * 295254Sksewell@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 305254Sksewell@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 315222Sksewell@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 322131SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 332131SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 342239SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 357676Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 367676Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 377676Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 382680Sktlim@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 398232Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 407676Snate@binkert.org * 412800Ssaidi@eecs.umich.edu * Authors: Ali Saidi 427676Snate@binkert.org * Gabe Black 432800Ssaidi@eecs.umich.edu */ 442800Ssaidi@eecs.umich.edu 452131SN/A#include "arch/arm/faults.hh" 462447SN/A#include "cpu/thread_context.hh" 472447SN/A#include "cpu/base.hh" 482131SN/A#include "base/trace.hh" 498566Sgblack@eecs.umich.edu 502131SN/Anamespace ArmISA 518578Sgblack@eecs.umich.edu{ 528578Sgblack@eecs.umich.edu 538578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Reset>::vals = 548578Sgblack@eecs.umich.edu {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 558578Sgblack@eecs.umich.edu 568578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals = 578578Sgblack@eecs.umich.edu {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 588578Sgblack@eecs.umich.edu 598578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals = 608578Sgblack@eecs.umich.edu {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 618578Sgblack@eecs.umich.edu 628578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals = 638578Sgblack@eecs.umich.edu {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 648578Sgblack@eecs.umich.edu 658578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals = 668578Sgblack@eecs.umich.edu {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 678578Sgblack@eecs.umich.edu 688578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals = 698578Sgblack@eecs.umich.edu {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 708578Sgblack@eecs.umich.edu 718578Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals = 728566Sgblack@eecs.umich.edu {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 738578Sgblack@eecs.umich.edu 742447SN/AAddr 758566Sgblack@eecs.umich.eduArmFaultBase::getVector(ThreadContext *tc) 768578Sgblack@eecs.umich.edu{ 778578Sgblack@eecs.umich.edu // ARM ARM B1-3 788578Sgblack@eecs.umich.edu 798578Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 808578Sgblack@eecs.umich.edu 818578Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 828578Sgblack@eecs.umich.edu // interrupts 838578Sgblack@eecs.umich.edu assert(!sctlr.ve); 848578Sgblack@eecs.umich.edu 858578Sgblack@eecs.umich.edu if (!sctlr.v) 868578Sgblack@eecs.umich.edu return offset(); 878578Sgblack@eecs.umich.edu return offset() + HighVecs; 888578Sgblack@eecs.umich.edu 892447SN/A} 908566Sgblack@eecs.umich.edu 918578Sgblack@eecs.umich.edu#if FULL_SYSTEM 925222Sksewell@umich.edu 938573Sgblack@eecs.umich.eduvoid 948578Sgblack@eecs.umich.eduArmFaultBase::invoke(ThreadContext *tc) 955222Sksewell@umich.edu{ 968573Sgblack@eecs.umich.edu // ARM ARM B1.6.3 978578Sgblack@eecs.umich.edu FaultBase::invoke(tc); 982447SN/A countStat()++; 998575Sgblack@eecs.umich.edu 1008578Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 1014661Sksewell@umich.edu CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1026378Sgblack@eecs.umich.edu CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 1038566Sgblack@eecs.umich.edu tc->readIntReg(INTREG_CONDCODES); 1045222Sksewell@umich.edu 1056378Sgblack@eecs.umich.edu 1066383Sgblack@eecs.umich.edu cpsr.mode = nextMode(); 1076379Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 1086378Sgblack@eecs.umich.edu cpsr.j = 0; 1096383Sgblack@eecs.umich.edu 1106379Sgblack@eecs.umich.edu cpsr.t = sctlr.te; 1116379Sgblack@eecs.umich.edu cpsr.a = cpsr.a | abortDisable(); 1126383Sgblack@eecs.umich.edu cpsr.f = cpsr.f | fiqDisable(); 1135222Sksewell@umich.edu cpsr.i = 1; 1145222Sksewell@umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 1156378Sgblack@eecs.umich.edu tc->setIntReg(INTREG_LR, tc->readPC() + 1166379Sgblack@eecs.umich.edu (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 1176383Sgblack@eecs.umich.edu 1185222Sksewell@umich.edu switch (nextMode()) { 1196378Sgblack@eecs.umich.edu case MODE_FIQ: 1208574Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 1218574Sgblack@eecs.umich.edu break; 1228574Sgblack@eecs.umich.edu case MODE_IRQ: 1238574Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 1248574Sgblack@eecs.umich.edu break; 1255222Sksewell@umich.edu case MODE_SVC: 1266378Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 1276383Sgblack@eecs.umich.edu break; 1286379Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1298574Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 1306379Sgblack@eecs.umich.edu break; 1316383Sgblack@eecs.umich.edu case MODE_ABORT: 1326378Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 1336378Sgblack@eecs.umich.edu break; 1346378Sgblack@eecs.umich.edu default: 1358578Sgblack@eecs.umich.edu panic("unknown Mode\n"); 1366378Sgblack@eecs.umich.edu } 1378738Sgblack@eecs.umich.edu 1388578Sgblack@eecs.umich.edu Addr pc = tc->readPC(); 1398578Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", 1408578Sgblack@eecs.umich.edu name(), cpsr, pc, tc->readIntReg(INTREG_LR)); 1416378Sgblack@eecs.umich.edu Addr newPc = getVector(tc) | (sctlr.te ? (ULL(1) << PcTBitShift) : 0); 1428578Sgblack@eecs.umich.edu tc->setPC(newPc); 1436378Sgblack@eecs.umich.edu tc->setNextPC(newPc + cpsr.t ? 2 : 4 ); 1446378Sgblack@eecs.umich.edu} 1456378Sgblack@eecs.umich.edu#endif // FULL_SYSTEM 1466378Sgblack@eecs.umich.edu 1477678Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm 1484661Sksewell@umich.edu 1498738Sgblack@eecs.umich.edu 1508578Sgblack@eecs.umich.edu 1518578Sgblack@eecs.umich.edu} // namespace ArmISA 1528578Sgblack@eecs.umich.edu 1538578Sgblack@eecs.umich.edu