faults.cc revision 6735
16019Shines@cs.fsu.edu/* 26019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 36019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 46019Shines@cs.fsu.edu * All rights reserved. 56019Shines@cs.fsu.edu * 66019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 76019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 86019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 96019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 106019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 116019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 126019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 136019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 146019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 156019Shines@cs.fsu.edu * this software without specific prior written permission. 166019Shines@cs.fsu.edu * 176019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 186019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 196019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 206019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 216019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 226019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 236019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 246019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 256019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 266019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 276019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 286019Shines@cs.fsu.edu * 296735Sgblack@eecs.umich.edu * Authors: Ali Saidi 306735Sgblack@eecs.umich.edu * Gabe Black 316019Shines@cs.fsu.edu */ 326019Shines@cs.fsu.edu 336019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 346019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 356019Shines@cs.fsu.edu#include "cpu/base.hh" 366019Shines@cs.fsu.edu#include "base/trace.hh" 376019Shines@cs.fsu.edu 386019Shines@cs.fsu.edunamespace ArmISA 396019Shines@cs.fsu.edu{ 406019Shines@cs.fsu.edu 416735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Reset>::vals = 426735Sgblack@eecs.umich.edu {"reset", 0x00, MODE_SVC, 0, 0, true, true}; 436019Shines@cs.fsu.edu 446735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<UndefinedInstruction>::vals = 456735Sgblack@eecs.umich.edu {"Undefined Instruction", 0x04, MODE_UNDEFINED, 4 ,2, false, false} ; 466019Shines@cs.fsu.edu 476735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<SupervisorCall>::vals = 486735Sgblack@eecs.umich.edu {"Supervisor Call", 0x08, MODE_SVC, 4, 2, false, false}; 496019Shines@cs.fsu.edu 506735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<PrefetchAbort>::vals = 516735Sgblack@eecs.umich.edu {"Prefetch Abort", 0x0C, MODE_ABORT, 4, 4, true, false}; 526019Shines@cs.fsu.edu 536735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<DataAbort>::vals = 546735Sgblack@eecs.umich.edu {"Data Abort", 0x10, MODE_ABORT, 8, 8, true, false}; 556019Shines@cs.fsu.edu 566735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<Interrupt>::vals = 576735Sgblack@eecs.umich.edu {"IRQ", 0x18, MODE_IRQ, 4, 4, true, false}; 586019Shines@cs.fsu.edu 596735Sgblack@eecs.umich.edutemplate<> ArmFaultBase::FaultVals ArmFault<FastInterrupt>::vals = 606735Sgblack@eecs.umich.edu {"FIQ", 0x1C, MODE_FIQ, 4, 4, true, true}; 616019Shines@cs.fsu.edu 626735Sgblack@eecs.umich.eduAddr 636735Sgblack@eecs.umich.eduArmFaultBase::getVector(ThreadContext *tc) 646735Sgblack@eecs.umich.edu{ 656735Sgblack@eecs.umich.edu // ARM ARM B1-3 666019Shines@cs.fsu.edu 676735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 686735Sgblack@eecs.umich.edu 696735Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 706735Sgblack@eecs.umich.edu // interrupts 716735Sgblack@eecs.umich.edu assert(!sctlr.ve); 726735Sgblack@eecs.umich.edu 736735Sgblack@eecs.umich.edu if (!sctlr.v) 746735Sgblack@eecs.umich.edu return offset(); 756735Sgblack@eecs.umich.edu return offset() + HighVecs; 766019Shines@cs.fsu.edu 776019Shines@cs.fsu.edu} 786019Shines@cs.fsu.edu 796735Sgblack@eecs.umich.edu#if FULL_SYSTEM 806735Sgblack@eecs.umich.edu 816735Sgblack@eecs.umich.eduvoid 826735Sgblack@eecs.umich.eduArmFaultBase::invoke(ThreadContext *tc) 836019Shines@cs.fsu.edu{ 846735Sgblack@eecs.umich.edu // ARM ARM B1.6.3 856735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 866735Sgblack@eecs.umich.edu countStat()++; 876019Shines@cs.fsu.edu 886735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 896735Sgblack@eecs.umich.edu CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 906735Sgblack@eecs.umich.edu CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR) | 916735Sgblack@eecs.umich.edu tc->readIntReg(INTREG_CONDCODES); 926735Sgblack@eecs.umich.edu 936735Sgblack@eecs.umich.edu 946735Sgblack@eecs.umich.edu cpsr.mode = nextMode(); 956735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 966735Sgblack@eecs.umich.edu cpsr.j = 0; 976735Sgblack@eecs.umich.edu 986735Sgblack@eecs.umich.edu if (sctlr.te) 996735Sgblack@eecs.umich.edu cpsr.t = 1; 1006735Sgblack@eecs.umich.edu cpsr.a = cpsr.a | abortDisable(); 1016735Sgblack@eecs.umich.edu cpsr.f = cpsr.f | fiqDisable(); 1026735Sgblack@eecs.umich.edu cpsr.i = 1; 1036735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 1046735Sgblack@eecs.umich.edu tc->setIntReg(INTREG_LR, tc->readPC() + 1056735Sgblack@eecs.umich.edu (saved_cpsr.t ? thumbPcOffset() : armPcOffset())); 1066735Sgblack@eecs.umich.edu 1076735Sgblack@eecs.umich.edu switch (nextMode()) { 1086735Sgblack@eecs.umich.edu case MODE_FIQ: 1096735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 1106735Sgblack@eecs.umich.edu break; 1116735Sgblack@eecs.umich.edu case MODE_IRQ: 1126735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 1136735Sgblack@eecs.umich.edu break; 1146735Sgblack@eecs.umich.edu case MODE_SVC: 1156735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 1166735Sgblack@eecs.umich.edu break; 1176735Sgblack@eecs.umich.edu case MODE_UNDEFINED: 1186735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 1196735Sgblack@eecs.umich.edu break; 1206735Sgblack@eecs.umich.edu case MODE_ABORT: 1216735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 1226735Sgblack@eecs.umich.edu break; 1236735Sgblack@eecs.umich.edu default: 1246735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 1256735Sgblack@eecs.umich.edu } 1266735Sgblack@eecs.umich.edu 1276735Sgblack@eecs.umich.edu DPRINTF(Faults, "Invoking Fault: %s cpsr: %#x PC: %#x lr: %#x\n", name(), cpsr, 1286735Sgblack@eecs.umich.edu tc->readPC(), tc->readIntReg(INTREG_LR)); 1296735Sgblack@eecs.umich.edu tc->setPC(getVector(tc)); 1306735Sgblack@eecs.umich.edu tc->setNextPC(getVector(tc) + cpsr.t ? 2 : 4 ); 1316019Shines@cs.fsu.edu} 1326019Shines@cs.fsu.edu#endif // FULL_SYSTEM 1336019Shines@cs.fsu.edu 1346735Sgblack@eecs.umich.edu// return via SUBS pc, lr, xxx; rfe, movs, ldm 1356019Shines@cs.fsu.edu 1366019Shines@cs.fsu.edu 1376019Shines@cs.fsu.edu 1386019Shines@cs.fsu.edu} // namespace ArmISA 1396019Shines@cs.fsu.edu 140