faults.cc revision 12763
16019Shines@cs.fsu.edu/* 212509Schuan.zhu@arm.com * Copyright (c) 2010, 2012-2014, 2016-2018 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 4811793Sbrandon.potter@amd.com 4911793Sbrandon.potter@amd.com#include "arch/arm/insts/static_inst.hh" 5010037SARM gem5 Developers#include "arch/arm/system.hh" 5110037SARM gem5 Developers#include "arch/arm/utility.hh" 5210037SARM gem5 Developers#include "base/compiler.hh" 538229Snate@binkert.org#include "base/trace.hh" 548229Snate@binkert.org#include "cpu/base.hh" 556019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 568232Snate@binkert.org#include "debug/Faults.hh" 578782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 586019Shines@cs.fsu.edu 596019Shines@cs.fsu.edunamespace ArmISA 606019Shines@cs.fsu.edu{ 616019Shines@cs.fsu.edu 6210037SARM gem5 Developersuint8_t ArmFault::shortDescFaultSources[] = { 6310037SARM gem5 Developers 0x01, // AlignmentFault 6410037SARM gem5 Developers 0x04, // InstructionCacheMaintenance 6510037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 6610037SARM gem5 Developers 0x0c, // SynchExtAbtOnTranslTableWalkL1 6710037SARM gem5 Developers 0x0e, // SynchExtAbtOnTranslTableWalkL2 6810037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 6910037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 7010037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL1 7110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 7210037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 7310037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 7410037SARM gem5 Developers 0x05, // TranslationL1 7510037SARM gem5 Developers 0x07, // TranslationL2 7610037SARM gem5 Developers 0xff, // TranslationL3 (INVALID) 7710037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 7810037SARM gem5 Developers 0x03, // AccessFlagL1 7910037SARM gem5 Developers 0x06, // AccessFlagL2 8010037SARM gem5 Developers 0xff, // AccessFlagL3 (INVALID) 8110037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 8210037SARM gem5 Developers 0x09, // DomainL1 8310037SARM gem5 Developers 0x0b, // DomainL2 8410037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 8510037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 8610037SARM gem5 Developers 0x0d, // PermissionL1 8710037SARM gem5 Developers 0x0f, // PermissionL2 8810037SARM gem5 Developers 0xff, // PermissionL3 (INVALID) 8910037SARM gem5 Developers 0x02, // DebugEvent 9010037SARM gem5 Developers 0x08, // SynchronousExternalAbort 9110037SARM gem5 Developers 0x10, // TLBConflictAbort 9210037SARM gem5 Developers 0x19, // SynchPtyErrOnMemoryAccess 9310037SARM gem5 Developers 0x16, // AsynchronousExternalAbort 9410037SARM gem5 Developers 0x18, // AsynchPtyErrOnMemoryAccess 9510037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 9610037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 9710037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 9810037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 9910037SARM gem5 Developers 0x40, // PrefetchTLBMiss 10010037SARM gem5 Developers 0x80 // PrefetchUncacheable 10110037SARM gem5 Developers}; 1026019Shines@cs.fsu.edu 10310037SARM gem5 Developersstatic_assert(sizeof(ArmFault::shortDescFaultSources) == 10410037SARM gem5 Developers ArmFault::NumFaultSources, 10510037SARM gem5 Developers "Invalid size of ArmFault::shortDescFaultSources[]"); 1066019Shines@cs.fsu.edu 10710037SARM gem5 Developersuint8_t ArmFault::longDescFaultSources[] = { 10810037SARM gem5 Developers 0x21, // AlignmentFault 10910037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 11010037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 11110037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 11210037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 11310037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 11410037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 11510037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 11610037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 11710037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 11810037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 11910037SARM gem5 Developers 0x05, // TranslationL1 12010037SARM gem5 Developers 0x06, // TranslationL2 12110037SARM gem5 Developers 0x07, // TranslationL3 12210037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 12310037SARM gem5 Developers 0x09, // AccessFlagL1 12410037SARM gem5 Developers 0x0a, // AccessFlagL2 12510037SARM gem5 Developers 0x0b, // AccessFlagL3 12610037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 12710037SARM gem5 Developers 0x3d, // DomainL1 12810037SARM gem5 Developers 0x3e, // DomainL2 12910037SARM gem5 Developers 0xff, // DomainL3 (RESERVED) 13010037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 13110037SARM gem5 Developers 0x0d, // PermissionL1 13210037SARM gem5 Developers 0x0e, // PermissionL2 13310037SARM gem5 Developers 0x0f, // PermissionL3 13410037SARM gem5 Developers 0x22, // DebugEvent 13510037SARM gem5 Developers 0x10, // SynchronousExternalAbort 13610037SARM gem5 Developers 0x30, // TLBConflictAbort 13710037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 13810037SARM gem5 Developers 0x11, // AsynchronousExternalAbort 13910037SARM gem5 Developers 0x19, // AsynchPtyErrOnMemoryAccess 14010037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 14110037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 14210037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 14310037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 14410037SARM gem5 Developers 0x40, // PrefetchTLBMiss 14510037SARM gem5 Developers 0x80 // PrefetchUncacheable 14610037SARM gem5 Developers}; 1476019Shines@cs.fsu.edu 14810037SARM gem5 Developersstatic_assert(sizeof(ArmFault::longDescFaultSources) == 14910037SARM gem5 Developers ArmFault::NumFaultSources, 15010037SARM gem5 Developers "Invalid size of ArmFault::longDescFaultSources[]"); 1516019Shines@cs.fsu.edu 15210037SARM gem5 Developersuint8_t ArmFault::aarch64FaultSources[] = { 15310037SARM gem5 Developers 0x21, // AlignmentFault 15410037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 15510037SARM gem5 Developers 0x14, // SynchExtAbtOnTranslTableWalkL0 15610037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 15710037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 15810037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 15910037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL0 16010037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 16110037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 16210037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 16310037SARM gem5 Developers 0x04, // TranslationL0 16410037SARM gem5 Developers 0x05, // TranslationL1 16510037SARM gem5 Developers 0x06, // TranslationL2 16610037SARM gem5 Developers 0x07, // TranslationL3 16710037SARM gem5 Developers 0x08, // AccessFlagL0 16810037SARM gem5 Developers 0x09, // AccessFlagL1 16910037SARM gem5 Developers 0x0a, // AccessFlagL2 17010037SARM gem5 Developers 0x0b, // AccessFlagL3 17110037SARM gem5 Developers // @todo: Section & Page Domain Fault in AArch64? 17210037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 17310037SARM gem5 Developers 0xff, // DomainL1 (INVALID) 17410037SARM gem5 Developers 0xff, // DomainL2 (INVALID) 17510037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 17610037SARM gem5 Developers 0x0c, // PermissionL0 17710037SARM gem5 Developers 0x0d, // PermissionL1 17810037SARM gem5 Developers 0x0e, // PermissionL2 17910037SARM gem5 Developers 0x0f, // PermissionL3 18012571Sgiacomo.travaglini@arm.com 0x22, // DebugEvent 18110037SARM gem5 Developers 0x10, // SynchronousExternalAbort 18210037SARM gem5 Developers 0x30, // TLBConflictAbort 18310037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 18410037SARM gem5 Developers 0xff, // AsynchronousExternalAbort (INVALID) 18510037SARM gem5 Developers 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 18610037SARM gem5 Developers 0x00, // AddressSizeL0 18710037SARM gem5 Developers 0x01, // AddressSizeL1 18810037SARM gem5 Developers 0x02, // AddressSizeL2 18910037SARM gem5 Developers 0x03, // AddressSizeL3 19010037SARM gem5 Developers 0x40, // PrefetchTLBMiss 19110037SARM gem5 Developers 0x80 // PrefetchUncacheable 19210037SARM gem5 Developers}; 1936019Shines@cs.fsu.edu 19410037SARM gem5 Developersstatic_assert(sizeof(ArmFault::aarch64FaultSources) == 19510037SARM gem5 Developers ArmFault::NumFaultSources, 19610037SARM gem5 Developers "Invalid size of ArmFault::aarch64FaultSources[]"); 1976019Shines@cs.fsu.edu 19810037SARM gem5 Developers// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 19910037SARM gem5 Developers// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 20010037SARM gem5 Developers// {A, F} disable, class, stat 20112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals( 20210037SARM gem5 Developers // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 20310037SARM gem5 Developers // location in AArch64) 20410037SARM gem5 Developers "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 20512517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 20612517Srekai.gonzalezalberquilla@arm.com); 20712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals( 20810037SARM gem5 Developers "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 20912517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, true, false, false, EC_UNKNOWN 21012517Srekai.gonzalezalberquilla@arm.com); 21112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals( 21210037SARM gem5 Developers "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 21312517Srekai.gonzalezalberquilla@arm.com 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP 21412517Srekai.gonzalezalberquilla@arm.com); 21512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals( 21610037SARM gem5 Developers "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 21712517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP 21812517Srekai.gonzalezalberquilla@arm.com); 21912517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals( 22010037SARM gem5 Developers "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 22112517Srekai.gonzalezalberquilla@arm.com 4, 4, 4, 4, true, false, false, EC_HVC 22212517Srekai.gonzalezalberquilla@arm.com); 22312517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals( 22410037SARM gem5 Developers "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22512517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP 22612517Srekai.gonzalezalberquilla@arm.com); 22712517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals( 22810037SARM gem5 Developers "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22912517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP 23012517Srekai.gonzalezalberquilla@arm.com); 23112517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals( 23210037SARM gem5 Developers "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 23312517Srekai.gonzalezalberquilla@arm.com 8, 8, 0, 0, true, true, false, EC_INVALID 23412517Srekai.gonzalezalberquilla@arm.com); 23512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals( 23610037SARM gem5 Developers // @todo: double check these values 23710037SARM gem5 Developers "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 23812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 23912517Srekai.gonzalezalberquilla@arm.com); 24012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals( 24112512Sgiacomo.travaglini@arm.com "Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON, 24212517Srekai.gonzalezalberquilla@arm.com 4, 2, 0, 0, false, false, false, EC_UNKNOWN 24312517Srekai.gonzalezalberquilla@arm.com); 24412517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals( 24510037SARM gem5 Developers "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24612517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_UNKNOWN 24712517Srekai.gonzalezalberquilla@arm.com); 24812517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals( 24910037SARM gem5 Developers "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 25012517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, false, EC_INVALID 25112517Srekai.gonzalezalberquilla@arm.com); 25212517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals( 25310037SARM gem5 Developers "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25412517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_UNKNOWN 25512517Srekai.gonzalezalberquilla@arm.com); 25612517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals( 25710037SARM gem5 Developers "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25812517Srekai.gonzalezalberquilla@arm.com 4, 4, 0, 0, false, true, true, EC_INVALID 25912517Srekai.gonzalezalberquilla@arm.com); 26012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals( 26110037SARM gem5 Developers // Some dummy values (SupervisorTrap is AArch64-only) 26210037SARM gem5 Developers "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26312517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, false, false, EC_UNKNOWN 26412517Srekai.gonzalezalberquilla@arm.com); 26512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals( 26610037SARM gem5 Developers // Some dummy values (PCAlignmentFault is AArch64-only) 26710037SARM gem5 Developers "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT 26912517Srekai.gonzalezalberquilla@arm.com); 27012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals( 27110037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 27210037SARM gem5 Developers "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27312517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT 27412517Srekai.gonzalezalberquilla@arm.com); 27512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals( 27610037SARM gem5 Developers // Some dummy values (SError is AArch64-only) 27710037SARM gem5 Developers "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 27812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_SERROR 27912517Srekai.gonzalezalberquilla@arm.com); 28012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals( 28112299Sandreas.sandberg@arm.com // Some dummy values (SoftwareBreakpoint is AArch64-only) 28212299Sandreas.sandberg@arm.com "Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 28312517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT 28412517Srekai.gonzalezalberquilla@arm.com); 28512517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals( 28610037SARM gem5 Developers // Some dummy values 28710037SARM gem5 Developers "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 28812517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, false, true, true, EC_UNKNOWN 28912517Srekai.gonzalezalberquilla@arm.com); 29012517Srekai.gonzalezalberquilla@arm.comtemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals( 29110037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 29210037SARM gem5 Developers "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 29312517Srekai.gonzalezalberquilla@arm.com 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST 29412517Srekai.gonzalezalberquilla@arm.com); 2956019Shines@cs.fsu.edu 29610037SARM gem5 DevelopersAddr 2977362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 2986735Sgblack@eecs.umich.edu{ 29910037SARM gem5 Developers Addr base; 3006019Shines@cs.fsu.edu 30110037SARM gem5 Developers // ARM ARM issue C B1.8.1 30210037SARM gem5 Developers bool haveSecurity = ArmSystem::haveSecurity(tc); 3037400SAli.Saidi@ARM.com 3046735Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 3056735Sgblack@eecs.umich.edu // interrupts 30610037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3076735Sgblack@eecs.umich.edu assert(!sctlr.ve); 30810037SARM gem5 Developers // Check for invalid modes 30910037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 31010037SARM gem5 Developers assert(haveSecurity || cpsr.mode != MODE_MON); 31110037SARM gem5 Developers assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 3127400SAli.Saidi@ARM.com 31310037SARM gem5 Developers switch (cpsr.mode) 31410037SARM gem5 Developers { 31510037SARM gem5 Developers case MODE_MON: 31610037SARM gem5 Developers base = tc->readMiscReg(MISCREG_MVBAR); 31710037SARM gem5 Developers break; 31810037SARM gem5 Developers case MODE_HYP: 31910037SARM gem5 Developers base = tc->readMiscReg(MISCREG_HVBAR); 32010037SARM gem5 Developers break; 32110037SARM gem5 Developers default: 32210037SARM gem5 Developers if (sctlr.v) { 32310037SARM gem5 Developers base = HighVecs; 32410037SARM gem5 Developers } else { 32510037SARM gem5 Developers base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 32610037SARM gem5 Developers } 32710037SARM gem5 Developers break; 32810037SARM gem5 Developers } 32910037SARM gem5 Developers return base + offset(tc); 3306019Shines@cs.fsu.edu} 3316019Shines@cs.fsu.edu 33210037SARM gem5 DevelopersAddr 33310037SARM gem5 DevelopersArmFault::getVector64(ThreadContext *tc) 33410037SARM gem5 Developers{ 33510037SARM gem5 Developers Addr vbar; 33610037SARM gem5 Developers switch (toEL) { 33710037SARM gem5 Developers case EL3: 33810037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 33910037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 34010037SARM gem5 Developers break; 34111574SCurtis.Dunham@arm.com case EL2: 34211574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 34311574SCurtis.Dunham@arm.com vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 34411574SCurtis.Dunham@arm.com break; 34510037SARM gem5 Developers case EL1: 34610037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 34710037SARM gem5 Developers break; 34810037SARM gem5 Developers default: 34910037SARM gem5 Developers panic("Invalid target exception level"); 35010037SARM gem5 Developers break; 35110037SARM gem5 Developers } 35212511Schuan.zhu@arm.com return vbar + offset64(tc); 35310037SARM gem5 Developers} 35410037SARM gem5 Developers 35510037SARM gem5 DevelopersMiscRegIndex 35610037SARM gem5 DevelopersArmFault::getSyndromeReg64() const 35710037SARM gem5 Developers{ 35810037SARM gem5 Developers switch (toEL) { 35910037SARM gem5 Developers case EL1: 36010037SARM gem5 Developers return MISCREG_ESR_EL1; 36110037SARM gem5 Developers case EL2: 36210037SARM gem5 Developers return MISCREG_ESR_EL2; 36310037SARM gem5 Developers case EL3: 36410037SARM gem5 Developers return MISCREG_ESR_EL3; 36510037SARM gem5 Developers default: 36610037SARM gem5 Developers panic("Invalid exception level"); 36710037SARM gem5 Developers break; 36810037SARM gem5 Developers } 36910037SARM gem5 Developers} 37010037SARM gem5 Developers 37110037SARM gem5 DevelopersMiscRegIndex 37210037SARM gem5 DevelopersArmFault::getFaultAddrReg64() const 37310037SARM gem5 Developers{ 37410037SARM gem5 Developers switch (toEL) { 37510037SARM gem5 Developers case EL1: 37610037SARM gem5 Developers return MISCREG_FAR_EL1; 37710037SARM gem5 Developers case EL2: 37810037SARM gem5 Developers return MISCREG_FAR_EL2; 37910037SARM gem5 Developers case EL3: 38010037SARM gem5 Developers return MISCREG_FAR_EL3; 38110037SARM gem5 Developers default: 38210037SARM gem5 Developers panic("Invalid exception level"); 38310037SARM gem5 Developers break; 38410037SARM gem5 Developers } 38510037SARM gem5 Developers} 38610037SARM gem5 Developers 38710037SARM gem5 Developersvoid 38810037SARM gem5 DevelopersArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 38910037SARM gem5 Developers{ 39010037SARM gem5 Developers uint32_t value; 39110037SARM gem5 Developers uint32_t exc_class = (uint32_t) ec(tc); 39210037SARM gem5 Developers uint32_t issVal = iss(); 39312402Sgiacomo.travaglini@arm.com 39410037SARM gem5 Developers assert(!from64 || ArmSystem::highestELIs64(tc)); 39510037SARM gem5 Developers 39610037SARM gem5 Developers value = exc_class << 26; 39710037SARM gem5 Developers 39810037SARM gem5 Developers // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 39910037SARM gem5 Developers // 0x25) for which the ISS information is not valid (ARMv7). 40010037SARM gem5 Developers // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 40110037SARM gem5 Developers // valid it is treated as RES1. 40210037SARM gem5 Developers if (to64) { 40310037SARM gem5 Developers value |= 1 << 25; 40410037SARM gem5 Developers } else if ((bits(exc_class, 5, 3) != 4) || 40510037SARM gem5 Developers (bits(exc_class, 2) && bits(issVal, 24))) { 40610037SARM gem5 Developers if (!machInst.thumb || machInst.bigThumb) 40710037SARM gem5 Developers value |= 1 << 25; 40810037SARM gem5 Developers } 40910037SARM gem5 Developers // Condition code valid for EC[5:4] nonzero 41010037SARM gem5 Developers if (!from64 && ((bits(exc_class, 5, 4) == 0) && 41110037SARM gem5 Developers (bits(exc_class, 3, 0) != 0))) { 41210037SARM gem5 Developers if (!machInst.thumb) { 41310037SARM gem5 Developers uint32_t cond; 41410037SARM gem5 Developers ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 41510037SARM gem5 Developers // If its on unconditional instruction report with a cond code of 41610037SARM gem5 Developers // 0xE, ie the unconditional code 41710037SARM gem5 Developers cond = (condCode == COND_UC) ? COND_AL : condCode; 41810037SARM gem5 Developers value |= cond << 20; 41910037SARM gem5 Developers value |= 1 << 24; 42010037SARM gem5 Developers } 42110037SARM gem5 Developers value |= bits(issVal, 19, 0); 42210037SARM gem5 Developers } else { 42310037SARM gem5 Developers value |= issVal; 42410037SARM gem5 Developers } 42510037SARM gem5 Developers tc->setMiscReg(syndrome_reg, value); 42610037SARM gem5 Developers} 42710037SARM gem5 Developers 42810037SARM gem5 Developersvoid 42912569Sgiacomo.travaglini@arm.comArmFault::update(ThreadContext *tc) 4306019Shines@cs.fsu.edu{ 43110037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 43210037SARM gem5 Developers 43312569Sgiacomo.travaglini@arm.com // Determine source exception level and mode 43412569Sgiacomo.travaglini@arm.com fromMode = (OperatingMode) (uint8_t) cpsr.mode; 43512569Sgiacomo.travaglini@arm.com fromEL = opModeToEL(fromMode); 43612569Sgiacomo.travaglini@arm.com if (opModeIs64(fromMode)) 43712569Sgiacomo.travaglini@arm.com from64 = true; 43810037SARM gem5 Developers 43912569Sgiacomo.travaglini@arm.com // Determine target exception level (aarch64) or target execution 44012569Sgiacomo.travaglini@arm.com // mode (aarch32). 44112569Sgiacomo.travaglini@arm.com if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) { 44212569Sgiacomo.travaglini@arm.com toMode = MODE_MON; 44312569Sgiacomo.travaglini@arm.com toEL = EL3; 44412569Sgiacomo.travaglini@arm.com } else if (ArmSystem::haveVirtualization(tc) && routeToHyp(tc)) { 44512569Sgiacomo.travaglini@arm.com toMode = MODE_HYP; 44612569Sgiacomo.travaglini@arm.com toEL = EL2; 44712569Sgiacomo.travaglini@arm.com hypRouted = true; 44812569Sgiacomo.travaglini@arm.com } else { 44912569Sgiacomo.travaglini@arm.com toMode = nextMode(); 45012569Sgiacomo.travaglini@arm.com toEL = opModeToEL(toMode); 45112569Sgiacomo.travaglini@arm.com } 45212402Sgiacomo.travaglini@arm.com 45312569Sgiacomo.travaglini@arm.com if (fromEL > toEL) 45412569Sgiacomo.travaglini@arm.com toEL = fromEL; 45510037SARM gem5 Developers 45612569Sgiacomo.travaglini@arm.com to64 = ELIs64(tc, toEL); 45712569Sgiacomo.travaglini@arm.com 45812569Sgiacomo.travaglini@arm.com // The fault specific informations have been updated; it is 45912569Sgiacomo.travaglini@arm.com // now possible to use them inside the fault. 46012569Sgiacomo.travaglini@arm.com faultUpdated = true; 46112569Sgiacomo.travaglini@arm.com} 46212569Sgiacomo.travaglini@arm.com 46312569Sgiacomo.travaglini@arm.comvoid 46412569Sgiacomo.travaglini@arm.comArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 46512569Sgiacomo.travaglini@arm.com{ 46612569Sgiacomo.travaglini@arm.com 46712569Sgiacomo.travaglini@arm.com // Update fault state informations, like the starting mode (aarch32) 46812569Sgiacomo.travaglini@arm.com // or EL (aarch64) and the ending mode or EL. 46912569Sgiacomo.travaglini@arm.com // From the update function we are also evaluating if the fault must 47012569Sgiacomo.travaglini@arm.com // be handled in AArch64 mode (to64). 47112569Sgiacomo.travaglini@arm.com update(tc); 47212569Sgiacomo.travaglini@arm.com 47312569Sgiacomo.travaglini@arm.com if (to64) { 47412569Sgiacomo.travaglini@arm.com // Invoke exception handler in AArch64 state 47512569Sgiacomo.travaglini@arm.com invoke64(tc, inst); 47612569Sgiacomo.travaglini@arm.com return; 47710037SARM gem5 Developers } 47810037SARM gem5 Developers 47910037SARM gem5 Developers // ARMv7 (ARM ARM issue C B1.9) 48010037SARM gem5 Developers 48110037SARM gem5 Developers bool have_security = ArmSystem::haveSecurity(tc); 48210037SARM gem5 Developers 4836735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 4848782Sgblack@eecs.umich.edu if (!FullSystem) 4858782Sgblack@eecs.umich.edu return; 4866735Sgblack@eecs.umich.edu countStat()++; 4876019Shines@cs.fsu.edu 4886735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 48910037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR); 4908303SAli.Saidi@ARM.com CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 49110338SCurtis.Dunham@arm.com saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 49210338SCurtis.Dunham@arm.com saved_cpsr.c = tc->readCCReg(CCREG_C); 49310338SCurtis.Dunham@arm.com saved_cpsr.v = tc->readCCReg(CCREG_V); 49410338SCurtis.Dunham@arm.com saved_cpsr.ge = tc->readCCReg(CCREG_GE); 4958303SAli.Saidi@ARM.com 4967720Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 4978205SAli.Saidi@ARM.com ITSTATE it = tc->pcState().itstate(); 4988205SAli.Saidi@ARM.com saved_cpsr.it2 = it.top6; 4998205SAli.Saidi@ARM.com saved_cpsr.it1 = it.bottom2; 5006735Sgblack@eecs.umich.edu 50110037SARM gem5 Developers // if we have a valid instruction then use it to annotate this fault with 50210037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 50310037SARM gem5 Developers // information 50410037SARM gem5 Developers if (inst) { 50512398Sgiacomo.travaglini@arm.com ArmStaticInst *armInst = static_cast<ArmStaticInst *>(inst.get()); 50610037SARM gem5 Developers armInst->annotateFault(this); 50710037SARM gem5 Developers } 50810037SARM gem5 Developers 50910037SARM gem5 Developers // Ensure Secure state if initially in Monitor mode 51010037SARM gem5 Developers if (have_security && saved_cpsr.mode == MODE_MON) { 51110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 51210037SARM gem5 Developers if (scr.ns) { 51310037SARM gem5 Developers scr.ns = 0; 51410037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_SCR, scr); 51510037SARM gem5 Developers } 51610037SARM gem5 Developers } 51710037SARM gem5 Developers 51812569Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 51912569Sgiacomo.travaglini@arm.com cpsr.mode = toMode; 52012569Sgiacomo.travaglini@arm.com 52110037SARM gem5 Developers // some bits are set differently if we have been routed to hyp mode 52210037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 52310037SARM gem5 Developers SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 52410037SARM gem5 Developers cpsr.t = hsctlr.te; 52510037SARM gem5 Developers cpsr.e = hsctlr.ee; 52610037SARM gem5 Developers if (!scr.ea) {cpsr.a = 1;} 52710037SARM gem5 Developers if (!scr.fiq) {cpsr.f = 1;} 52810037SARM gem5 Developers if (!scr.irq) {cpsr.i = 1;} 52910037SARM gem5 Developers } else if (cpsr.mode == MODE_MON) { 53010037SARM gem5 Developers // Special case handling when entering monitor mode 53110037SARM gem5 Developers cpsr.t = sctlr.te; 53210037SARM gem5 Developers cpsr.e = sctlr.ee; 53310037SARM gem5 Developers cpsr.a = 1; 53410037SARM gem5 Developers cpsr.f = 1; 53510037SARM gem5 Developers cpsr.i = 1; 53610037SARM gem5 Developers } else { 53710037SARM gem5 Developers cpsr.t = sctlr.te; 53810037SARM gem5 Developers cpsr.e = sctlr.ee; 53910037SARM gem5 Developers 54010037SARM gem5 Developers // The *Disable functions are virtual and different per fault 54110037SARM gem5 Developers cpsr.a = cpsr.a | abortDisable(tc); 54210037SARM gem5 Developers cpsr.f = cpsr.f | fiqDisable(tc); 54310037SARM gem5 Developers cpsr.i = 1; 54410037SARM gem5 Developers } 5456735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 5466735Sgblack@eecs.umich.edu cpsr.j = 0; 5476735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 54810037SARM gem5 Developers 5498518Sgeoffrey.blake@arm.com // Make sure mailbox sets to one always 5508518Sgeoffrey.blake@arm.com tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5516735Sgblack@eecs.umich.edu 55210037SARM gem5 Developers // Clear the exclusive monitor 55310037SARM gem5 Developers tc->setMiscReg(MISCREG_LOCKFLAG, 0); 55410037SARM gem5 Developers 55510037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 55610037SARM gem5 Developers tc->setMiscReg(MISCREG_ELR_HYP, curPc + 55710037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 55810037SARM gem5 Developers } else { 55910037SARM gem5 Developers tc->setIntReg(INTREG_LR, curPc + 56010037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 56110037SARM gem5 Developers } 56210037SARM gem5 Developers 56310037SARM gem5 Developers switch (cpsr.mode) { 5646735Sgblack@eecs.umich.edu case MODE_FIQ: 5656735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 5666735Sgblack@eecs.umich.edu break; 5676735Sgblack@eecs.umich.edu case MODE_IRQ: 5686735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 5696735Sgblack@eecs.umich.edu break; 5706735Sgblack@eecs.umich.edu case MODE_SVC: 5716735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 5726735Sgblack@eecs.umich.edu break; 57310037SARM gem5 Developers case MODE_MON: 57410037SARM gem5 Developers assert(have_security); 57510037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 5766735Sgblack@eecs.umich.edu break; 5776735Sgblack@eecs.umich.edu case MODE_ABORT: 5786735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 5796735Sgblack@eecs.umich.edu break; 58010037SARM gem5 Developers case MODE_UNDEFINED: 58110037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 58210037SARM gem5 Developers if (ec(tc) != EC_UNKNOWN) 58310037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 58410037SARM gem5 Developers break; 58510037SARM gem5 Developers case MODE_HYP: 58612589Snikos.nikoleris@arm.com assert(ArmSystem::haveVirtualization(tc)); 58710037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 58810037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 58910037SARM gem5 Developers break; 5906735Sgblack@eecs.umich.edu default: 5916735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 5927093Sgblack@eecs.umich.edu } 5937093Sgblack@eecs.umich.edu 5947720Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 5957585SAli.Saidi@arm.com DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 5967720Sgblack@eecs.umich.edu name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 5977720Sgblack@eecs.umich.edu PCState pc(newPc); 5987720Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 5997720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 6007720Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 6017720Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 60210037SARM gem5 Developers pc.aarch64(!cpsr.width); 60310037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 60412763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 6057720Sgblack@eecs.umich.edu tc->pcState(pc); 6066019Shines@cs.fsu.edu} 6077189Sgblack@eecs.umich.edu 6087400SAli.Saidi@ARM.comvoid 60910417Sandreas.hansson@arm.comArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 61010037SARM gem5 Developers{ 61110037SARM gem5 Developers // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 61210037SARM gem5 Developers MiscRegIndex elr_idx, spsr_idx; 61310037SARM gem5 Developers switch (toEL) { 61410037SARM gem5 Developers case EL1: 61510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL1; 61610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL1; 61710037SARM gem5 Developers break; 61811574SCurtis.Dunham@arm.com case EL2: 61911574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 62011574SCurtis.Dunham@arm.com elr_idx = MISCREG_ELR_EL2; 62111574SCurtis.Dunham@arm.com spsr_idx = MISCREG_SPSR_EL2; 62211574SCurtis.Dunham@arm.com break; 62310037SARM gem5 Developers case EL3: 62410037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 62510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL3; 62610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL3; 62710037SARM gem5 Developers break; 62810037SARM gem5 Developers default: 62910037SARM gem5 Developers panic("Invalid target exception level"); 63010037SARM gem5 Developers break; 63110037SARM gem5 Developers } 63210037SARM gem5 Developers 63310037SARM gem5 Developers // Save process state into SPSR_ELx 63410037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 63510037SARM gem5 Developers CPSR spsr = cpsr; 63610338SCurtis.Dunham@arm.com spsr.nz = tc->readCCReg(CCREG_NZ); 63710338SCurtis.Dunham@arm.com spsr.c = tc->readCCReg(CCREG_C); 63810338SCurtis.Dunham@arm.com spsr.v = tc->readCCReg(CCREG_V); 63910037SARM gem5 Developers if (from64) { 64010037SARM gem5 Developers // Force some bitfields to 0 64110037SARM gem5 Developers spsr.q = 0; 64210037SARM gem5 Developers spsr.it1 = 0; 64310037SARM gem5 Developers spsr.j = 0; 64410037SARM gem5 Developers spsr.res0_23_22 = 0; 64510037SARM gem5 Developers spsr.ge = 0; 64610037SARM gem5 Developers spsr.it2 = 0; 64710037SARM gem5 Developers spsr.t = 0; 64810037SARM gem5 Developers } else { 64910338SCurtis.Dunham@arm.com spsr.ge = tc->readCCReg(CCREG_GE); 65010037SARM gem5 Developers ITSTATE it = tc->pcState().itstate(); 65110037SARM gem5 Developers spsr.it2 = it.top6; 65210037SARM gem5 Developers spsr.it1 = it.bottom2; 65310037SARM gem5 Developers // Force some bitfields to 0 65410037SARM gem5 Developers spsr.res0_23_22 = 0; 65510037SARM gem5 Developers spsr.ss = 0; 65610037SARM gem5 Developers } 65710037SARM gem5 Developers tc->setMiscReg(spsr_idx, spsr); 65810037SARM gem5 Developers 65910037SARM gem5 Developers // Save preferred return address into ELR_ELx 66010037SARM gem5 Developers Addr curr_pc = tc->pcState().pc(); 66110037SARM gem5 Developers Addr ret_addr = curr_pc; 66210037SARM gem5 Developers if (from64) 66310037SARM gem5 Developers ret_addr += armPcElrOffset(); 66410037SARM gem5 Developers else 66510037SARM gem5 Developers ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 66610037SARM gem5 Developers tc->setMiscReg(elr_idx, ret_addr); 66710037SARM gem5 Developers 66812511Schuan.zhu@arm.com Addr vec_address = getVector64(tc); 66912511Schuan.zhu@arm.com 67010037SARM gem5 Developers // Update process state 67110037SARM gem5 Developers OperatingMode64 mode = 0; 67210037SARM gem5 Developers mode.spX = 1; 67310037SARM gem5 Developers mode.el = toEL; 67410037SARM gem5 Developers mode.width = 0; 67510037SARM gem5 Developers cpsr.mode = mode; 67610037SARM gem5 Developers cpsr.daif = 0xf; 67710037SARM gem5 Developers cpsr.il = 0; 67810037SARM gem5 Developers cpsr.ss = 0; 67910037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 68010037SARM gem5 Developers 68110037SARM gem5 Developers // Set PC to start of exception handler 68212511Schuan.zhu@arm.com Addr new_pc = purifyTaggedAddr(vec_address, tc, toEL); 68310037SARM gem5 Developers DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 68410037SARM gem5 Developers "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 68510037SARM gem5 Developers PCState pc(new_pc); 68610037SARM gem5 Developers pc.aarch64(!cpsr.width); 68710037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 68812763Sgiacomo.travaglini@arm.com pc.illegalExec(false); 68910037SARM gem5 Developers tc->pcState(pc); 69010037SARM gem5 Developers 69110037SARM gem5 Developers // If we have a valid instruction then use it to annotate this fault with 69210037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 69310037SARM gem5 Developers // information 69410037SARM gem5 Developers if (inst) 69512398Sgiacomo.travaglini@arm.com static_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 69610037SARM gem5 Developers // Save exception syndrome 69710037SARM gem5 Developers if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 69810037SARM gem5 Developers setSyndrome(tc, getSyndromeReg64()); 69910037SARM gem5 Developers} 70010037SARM gem5 Developers 70110037SARM gem5 Developersvoid 70210417Sandreas.hansson@arm.comReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7037400SAli.Saidi@ARM.com{ 7048782Sgblack@eecs.umich.edu if (FullSystem) { 70511150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupts(tc->threadId()); 7068782Sgblack@eecs.umich.edu tc->clearArchRegs(); 7078782Sgblack@eecs.umich.edu } 70810037SARM gem5 Developers if (!ArmSystem::highestELIs64(tc)) { 70910037SARM gem5 Developers ArmFault::invoke(tc, inst); 71010037SARM gem5 Developers tc->setMiscReg(MISCREG_VMPIDR, 71110037SARM gem5 Developers getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 71210037SARM gem5 Developers 71310037SARM gem5 Developers // Unless we have SMC code to get us there, boot in HYP! 71410037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc) && 71510037SARM gem5 Developers !ArmSystem::haveSecurity(tc)) { 71610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 71710037SARM gem5 Developers cpsr.mode = MODE_HYP; 71810037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 71910037SARM gem5 Developers } 72010037SARM gem5 Developers } else { 72110037SARM gem5 Developers // Advance the PC to the IMPLEMENTATION DEFINED reset value 72210037SARM gem5 Developers PCState pc = ArmSystem::resetAddr64(tc); 72310037SARM gem5 Developers pc.aarch64(true); 72410037SARM gem5 Developers pc.nextAArch64(true); 72510037SARM gem5 Developers tc->pcState(pc); 72610037SARM gem5 Developers } 7277400SAli.Saidi@ARM.com} 7287400SAli.Saidi@ARM.com 7297189Sgblack@eecs.umich.eduvoid 73010417Sandreas.hansson@arm.comUndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7317189Sgblack@eecs.umich.edu{ 7328782Sgblack@eecs.umich.edu if (FullSystem) { 7338782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7348806Sgblack@eecs.umich.edu return; 7358806Sgblack@eecs.umich.edu } 7368806Sgblack@eecs.umich.edu 7378806Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 7388806Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 7398806Sgblack@eecs.umich.edu if (disabled) { 7408806Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 7418806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7428806Sgblack@eecs.umich.edu } else if (unknown) { 7438806Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 7448806Sgblack@eecs.umich.edu machInst); 7457189Sgblack@eecs.umich.edu } else { 7468806Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 7478806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7487189Sgblack@eecs.umich.edu } 7497189Sgblack@eecs.umich.edu} 7507189Sgblack@eecs.umich.edu 75110037SARM gem5 Developersbool 75210037SARM gem5 DevelopersUndefinedInstruction::routeToHyp(ThreadContext *tc) const 75310037SARM gem5 Developers{ 75410037SARM gem5 Developers bool toHyp; 75510037SARM gem5 Developers 75610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 75710037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 75810037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 75910037SARM gem5 Developers 76010037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 76110037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 76210037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 76310037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 76410037SARM gem5 Developers return toHyp; 76510037SARM gem5 Developers} 76610037SARM gem5 Developers 76710037SARM gem5 Developersuint32_t 76810037SARM gem5 DevelopersUndefinedInstruction::iss() const 76910037SARM gem5 Developers{ 77012402Sgiacomo.travaglini@arm.com 77112402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, iss field is 0. 77212402Sgiacomo.travaglini@arm.com if (hypRouted) { 77312402Sgiacomo.travaglini@arm.com return 0; 77412402Sgiacomo.travaglini@arm.com } 77512402Sgiacomo.travaglini@arm.com 77610037SARM gem5 Developers if (overrideEc == EC_INVALID) 77710037SARM gem5 Developers return issRaw; 77810037SARM gem5 Developers 77910037SARM gem5 Developers uint32_t new_iss = 0; 78010037SARM gem5 Developers uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 78110037SARM gem5 Developers 78210037SARM gem5 Developers dir = bits(machInst, 21, 21); 78310037SARM gem5 Developers op0 = bits(machInst, 20, 19); 78410037SARM gem5 Developers op1 = bits(machInst, 18, 16); 78510037SARM gem5 Developers CRn = bits(machInst, 15, 12); 78610037SARM gem5 Developers CRm = bits(machInst, 11, 8); 78710037SARM gem5 Developers op2 = bits(machInst, 7, 5); 78810037SARM gem5 Developers Rt = bits(machInst, 4, 0); 78910037SARM gem5 Developers 79010037SARM gem5 Developers new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 79110037SARM gem5 Developers Rt << 5 | CRm << 1 | dir; 79210037SARM gem5 Developers 79310037SARM gem5 Developers return new_iss; 79410037SARM gem5 Developers} 79510037SARM gem5 Developers 7967197Sgblack@eecs.umich.eduvoid 79710417Sandreas.hansson@arm.comSupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7987197Sgblack@eecs.umich.edu{ 7998782Sgblack@eecs.umich.edu if (FullSystem) { 8008782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 8018806Sgblack@eecs.umich.edu return; 8028806Sgblack@eecs.umich.edu } 8037197Sgblack@eecs.umich.edu 8048806Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 8058806Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 8068806Sgblack@eecs.umich.edu uint32_t callNum; 80710037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 80810037SARM gem5 Developers OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 80910037SARM gem5 Developers if (opModeIs64(mode)) 81010037SARM gem5 Developers callNum = tc->readIntReg(INTREG_X8); 81110037SARM gem5 Developers else 81210037SARM gem5 Developers callNum = tc->readIntReg(INTREG_R7); 81311877Sbrandon.potter@amd.com Fault fault; 81411877Sbrandon.potter@amd.com tc->syscall(callNum, &fault); 8158806Sgblack@eecs.umich.edu 8168806Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 8178806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 8188806Sgblack@eecs.umich.edu assert(inst); 8198806Sgblack@eecs.umich.edu inst->advancePC(pc); 8208806Sgblack@eecs.umich.edu tc->pcState(pc); 8217197Sgblack@eecs.umich.edu} 8227197Sgblack@eecs.umich.edu 82310037SARM gem5 Developersbool 82410037SARM gem5 DevelopersSupervisorCall::routeToHyp(ThreadContext *tc) const 82510037SARM gem5 Developers{ 82610037SARM gem5 Developers bool toHyp; 82710037SARM gem5 Developers 82810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 82910037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 83010037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 83110037SARM gem5 Developers 83210037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 83310037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 83410037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 83510037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 83610037SARM gem5 Developers return toHyp; 83710037SARM gem5 Developers} 83810037SARM gem5 Developers 83910037SARM gem5 DevelopersExceptionClass 84010037SARM gem5 DevelopersSupervisorCall::ec(ThreadContext *tc) const 84110037SARM gem5 Developers{ 84210037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 84310037SARM gem5 Developers (from64 ? EC_SVC_64 : vals.ec); 84410037SARM gem5 Developers} 84510037SARM gem5 Developers 84610037SARM gem5 Developersuint32_t 84710037SARM gem5 DevelopersSupervisorCall::iss() const 84810037SARM gem5 Developers{ 84910037SARM gem5 Developers // Even if we have a 24 bit imm from an arm32 instruction then we only use 85010037SARM gem5 Developers // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 85110037SARM gem5 Developers return issRaw & 0xFFFF; 85210037SARM gem5 Developers} 85310037SARM gem5 Developers 85410037SARM gem5 Developersuint32_t 85510037SARM gem5 DevelopersSecureMonitorCall::iss() const 85610037SARM gem5 Developers{ 85710037SARM gem5 Developers if (from64) 85810037SARM gem5 Developers return bits(machInst, 20, 5); 85910037SARM gem5 Developers return 0; 86010037SARM gem5 Developers} 86110037SARM gem5 Developers 86210037SARM gem5 DevelopersExceptionClass 86310037SARM gem5 DevelopersUndefinedInstruction::ec(ThreadContext *tc) const 86410037SARM gem5 Developers{ 86512402Sgiacomo.travaglini@arm.com // If UndefinedInstruction is routed to hypervisor, 86612402Sgiacomo.travaglini@arm.com // HSR.EC field is 0. 86712402Sgiacomo.travaglini@arm.com if (hypRouted) 86812402Sgiacomo.travaglini@arm.com return EC_UNKNOWN; 86912402Sgiacomo.travaglini@arm.com else 87012402Sgiacomo.travaglini@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 87110037SARM gem5 Developers} 87210037SARM gem5 Developers 87310037SARM gem5 Developers 87410037SARM gem5 DevelopersHypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 87510037SARM gem5 Developers ArmFaultVals<HypervisorCall>(_machInst, _imm) 87610037SARM gem5 Developers{} 87710037SARM gem5 Developers 87810037SARM gem5 DevelopersExceptionClass 87911576SDylan.Johnson@ARM.comHypervisorCall::ec(ThreadContext *tc) const 88011576SDylan.Johnson@ARM.com{ 88111576SDylan.Johnson@ARM.com return from64 ? EC_HVC_64 : vals.ec; 88211576SDylan.Johnson@ARM.com} 88311576SDylan.Johnson@ARM.com 88411576SDylan.Johnson@ARM.comExceptionClass 88510037SARM gem5 DevelopersHypervisorTrap::ec(ThreadContext *tc) const 88610037SARM gem5 Developers{ 88710037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 88810037SARM gem5 Developers} 88910037SARM gem5 Developers 89010037SARM gem5 Developerstemplate<class T> 89110037SARM gem5 DevelopersFaultOffset 89210037SARM gem5 DevelopersArmFaultVals<T>::offset(ThreadContext *tc) 89310037SARM gem5 Developers{ 89410037SARM gem5 Developers bool isHypTrap = false; 89510037SARM gem5 Developers 89610037SARM gem5 Developers // Normally we just use the exception vector from the table at the top if 89710037SARM gem5 Developers // this file, however if this exception has caused a transition to hype 89810037SARM gem5 Developers // mode, and its an exception type that would only do this if it has been 89910037SARM gem5 Developers // trapped then we use the hyp trap vector instead of the normal vector 90010037SARM gem5 Developers if (vals.hypTrappable) { 90110037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 90210037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 90310037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 90410037SARM gem5 Developers isHypTrap = spsr.mode != MODE_HYP; 90510037SARM gem5 Developers } 90610037SARM gem5 Developers } 90710037SARM gem5 Developers return isHypTrap ? 0x14 : vals.offset; 90810037SARM gem5 Developers} 90910037SARM gem5 Developers 91012511Schuan.zhu@arm.comtemplate<class T> 91112511Schuan.zhu@arm.comFaultOffset 91212511Schuan.zhu@arm.comArmFaultVals<T>::offset64(ThreadContext *tc) 91312511Schuan.zhu@arm.com{ 91412511Schuan.zhu@arm.com if (toEL == fromEL) { 91512511Schuan.zhu@arm.com if (opModeIsT(fromMode)) 91612511Schuan.zhu@arm.com return vals.currELTOffset; 91712511Schuan.zhu@arm.com return vals.currELHOffset; 91812511Schuan.zhu@arm.com } else { 91912511Schuan.zhu@arm.com bool lower_32 = false; 92012511Schuan.zhu@arm.com if (toEL == EL3) { 92112511Schuan.zhu@arm.com if (!inSecureState(tc) && ArmSystem::haveEL(tc, EL2)) 92212511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL2); 92312511Schuan.zhu@arm.com else 92412511Schuan.zhu@arm.com lower_32 = ELIs32(tc, EL1); 92512511Schuan.zhu@arm.com } else { 92612511Schuan.zhu@arm.com lower_32 = ELIs32(tc, static_cast<ExceptionLevel>(toEL - 1)); 92712511Schuan.zhu@arm.com } 92812511Schuan.zhu@arm.com 92912511Schuan.zhu@arm.com if (lower_32) 93012511Schuan.zhu@arm.com return vals.lowerEL32Offset; 93112511Schuan.zhu@arm.com return vals.lowerEL64Offset; 93212511Schuan.zhu@arm.com } 93312511Schuan.zhu@arm.com} 93412511Schuan.zhu@arm.com 93510037SARM gem5 Developers// void 93610037SARM gem5 Developers// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 93710037SARM gem5 Developers// { 93810037SARM gem5 Developers// ESR esr = 0; 93910037SARM gem5 Developers// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 94010037SARM gem5 Developers// esr.il = !machInst.thumb; 94110037SARM gem5 Developers// if (machInst.aarch64) 94210037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 20, 5); 94310037SARM gem5 Developers// else if (machInst.thumb) 94410037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 7, 0); 94510037SARM gem5 Developers// else 94610037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 15, 0); 94710037SARM gem5 Developers// tc->setMiscReg(esr_idx, esr); 94810037SARM gem5 Developers// } 94910037SARM gem5 Developers 95010037SARM gem5 Developersvoid 95110417Sandreas.hansson@arm.comSecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 95210037SARM gem5 Developers{ 95310037SARM gem5 Developers if (FullSystem) { 95410037SARM gem5 Developers ArmFault::invoke(tc, inst); 95510037SARM gem5 Developers return; 95610037SARM gem5 Developers } 95710037SARM gem5 Developers} 95810037SARM gem5 Developers 95910037SARM gem5 DevelopersExceptionClass 96010037SARM gem5 DevelopersSecureMonitorCall::ec(ThreadContext *tc) const 96110037SARM gem5 Developers{ 96210037SARM gem5 Developers return (from64 ? EC_SMC_64 : vals.ec); 96310037SARM gem5 Developers} 96410037SARM gem5 Developers 96512509Schuan.zhu@arm.combool 96612509Schuan.zhu@arm.comSupervisorTrap::routeToHyp(ThreadContext *tc) const 96712509Schuan.zhu@arm.com{ 96812509Schuan.zhu@arm.com bool toHyp = false; 96912509Schuan.zhu@arm.com 97012509Schuan.zhu@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 97112509Schuan.zhu@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 97212509Schuan.zhu@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 97312509Schuan.zhu@arm.com 97412509Schuan.zhu@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 97512509Schuan.zhu@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 97612509Schuan.zhu@arm.com return toHyp; 97712509Schuan.zhu@arm.com} 97812509Schuan.zhu@arm.com 97912509Schuan.zhu@arm.comuint32_t 98012509Schuan.zhu@arm.comSupervisorTrap::iss() const 98112509Schuan.zhu@arm.com{ 98212509Schuan.zhu@arm.com // If SupervisorTrap is routed to hypervisor, iss field is 0. 98312509Schuan.zhu@arm.com if (hypRouted) { 98412509Schuan.zhu@arm.com return 0; 98512509Schuan.zhu@arm.com } 98612509Schuan.zhu@arm.com return issRaw; 98712509Schuan.zhu@arm.com} 98812509Schuan.zhu@arm.com 98910037SARM gem5 DevelopersExceptionClass 99010037SARM gem5 DevelopersSupervisorTrap::ec(ThreadContext *tc) const 99110037SARM gem5 Developers{ 99212509Schuan.zhu@arm.com if (hypRouted) 99312509Schuan.zhu@arm.com return EC_UNKNOWN; 99412509Schuan.zhu@arm.com else 99512509Schuan.zhu@arm.com return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 99610037SARM gem5 Developers} 99710037SARM gem5 Developers 99810037SARM gem5 DevelopersExceptionClass 99910037SARM gem5 DevelopersSecureMonitorTrap::ec(ThreadContext *tc) const 100010037SARM gem5 Developers{ 100110037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 100210037SARM gem5 Developers (from64 ? EC_SMC_64 : vals.ec); 100310037SARM gem5 Developers} 100410037SARM gem5 Developers 10057362Sgblack@eecs.umich.edutemplate<class T> 10067362Sgblack@eecs.umich.eduvoid 100710417Sandreas.hansson@arm.comAbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 10087362Sgblack@eecs.umich.edu{ 100910037SARM gem5 Developers if (tranMethod == ArmFault::UnknownTran) { 101010037SARM gem5 Developers tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 101110037SARM gem5 Developers : ArmFault::VmsaTran; 101210037SARM gem5 Developers 101310037SARM gem5 Developers if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 101410037SARM gem5 Developers // See ARM ARM B3-1416 101510037SARM gem5 Developers bool override_LPAE = false; 101610037SARM gem5 Developers TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 101710037SARM gem5 Developers TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 101810037SARM gem5 Developers if (ttbcr_s.eae) { 101910037SARM gem5 Developers override_LPAE = true; 102010037SARM gem5 Developers } else { 102110037SARM gem5 Developers // Unimplemented code option, not seen in testing. May need 102210037SARM gem5 Developers // extension according to the manual exceprt above. 102310037SARM gem5 Developers DPRINTF(Faults, "Warning: Incomplete translation method " 102410037SARM gem5 Developers "override detected.\n"); 102510037SARM gem5 Developers } 102610037SARM gem5 Developers if (override_LPAE) 102710037SARM gem5 Developers tranMethod = ArmFault::LpaeTran; 102810037SARM gem5 Developers } 102910037SARM gem5 Developers } 103010037SARM gem5 Developers 103110037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 103211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 103310037SARM gem5 Developers } 103410037SARM gem5 Developers // Get effective fault source encoding 103510037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 103610037SARM gem5 Developers 103710037SARM gem5 Developers // source must be determined BEFORE invoking generic routines which will 103810037SARM gem5 Developers // try to set hsr etc. and are based upon source! 10398205SAli.Saidi@ARM.com ArmFaultVals<T>::invoke(tc, inst); 104010037SARM gem5 Developers 104111496Sandreas.sandberg@arm.com if (!this->to64) { // AArch32 104212570Sgiacomo.travaglini@arm.com FSR fsr = getFsr(tc); 104310037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 104410037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, faultAddr); 104510037SARM gem5 Developers } else if (stage2) { 104610037SARM gem5 Developers tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 104710037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, OVAddr); 104810037SARM gem5 Developers } else { 104910037SARM gem5 Developers tc->setMiscReg(T::FsrIndex, fsr); 105010037SARM gem5 Developers tc->setMiscReg(T::FarIndex, faultAddr); 105110037SARM gem5 Developers } 105210037SARM gem5 Developers DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 105310037SARM gem5 Developers "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 105410037SARM gem5 Developers } else { // AArch64 105510037SARM gem5 Developers // Set the FAR register. Nothing else to do if we are in AArch64 state 105610037SARM gem5 Developers // because the syndrome register has already been set inside invoke64() 105711585SDylan.Johnson@ARM.com if (stage2) { 105811585SDylan.Johnson@ARM.com // stage 2 fault, set HPFAR_EL2 to the faulting IPA 105911585SDylan.Johnson@ARM.com // and FAR_EL2 to the Original VA 106011585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), OVAddr); 106111585SDylan.Johnson@ARM.com tc->setMiscReg(MISCREG_HPFAR_EL2, bits(faultAddr, 47, 12) << 4); 106211585SDylan.Johnson@ARM.com 106311585SDylan.Johnson@ARM.com DPRINTF(Faults, "Abort Fault (Stage 2) VA: 0x%x IPA: 0x%x\n", 106411585SDylan.Johnson@ARM.com OVAddr, faultAddr); 106511585SDylan.Johnson@ARM.com } else { 106611585SDylan.Johnson@ARM.com tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 106711585SDylan.Johnson@ARM.com } 106810037SARM gem5 Developers } 106910037SARM gem5 Developers} 107010037SARM gem5 Developers 107110037SARM gem5 Developerstemplate<class T> 107212570Sgiacomo.travaglini@arm.comvoid 107312570Sgiacomo.travaglini@arm.comAbortFault<T>::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 107412570Sgiacomo.travaglini@arm.com{ 107512570Sgiacomo.travaglini@arm.com srcEncoded = getFaultStatusCode(tc); 107612570Sgiacomo.travaglini@arm.com if (srcEncoded == ArmFault::FaultSourceInvalid) { 107712570Sgiacomo.travaglini@arm.com panic("Invalid fault source\n"); 107812570Sgiacomo.travaglini@arm.com } 107912570Sgiacomo.travaglini@arm.com ArmFault::setSyndrome(tc, syndrome_reg); 108012570Sgiacomo.travaglini@arm.com} 108112570Sgiacomo.travaglini@arm.com 108212570Sgiacomo.travaglini@arm.comtemplate<class T> 108312570Sgiacomo.travaglini@arm.comuint8_t 108412570Sgiacomo.travaglini@arm.comAbortFault<T>::getFaultStatusCode(ThreadContext *tc) const 108512570Sgiacomo.travaglini@arm.com{ 108612570Sgiacomo.travaglini@arm.com 108712570Sgiacomo.travaglini@arm.com panic_if(!this->faultUpdated, 108812570Sgiacomo.travaglini@arm.com "Trying to use un-updated ArmFault internal variables\n"); 108912570Sgiacomo.travaglini@arm.com 109012570Sgiacomo.travaglini@arm.com uint8_t fsc = 0; 109112570Sgiacomo.travaglini@arm.com 109212570Sgiacomo.travaglini@arm.com if (!this->to64) { 109312570Sgiacomo.travaglini@arm.com // AArch32 109412570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 109512570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 109612570Sgiacomo.travaglini@arm.com fsc = ArmFault::longDescFaultSources[source]; 109712570Sgiacomo.travaglini@arm.com } else { 109812570Sgiacomo.travaglini@arm.com fsc = ArmFault::shortDescFaultSources[source]; 109912570Sgiacomo.travaglini@arm.com } 110012570Sgiacomo.travaglini@arm.com } else { 110112570Sgiacomo.travaglini@arm.com // AArch64 110212570Sgiacomo.travaglini@arm.com fsc = ArmFault::aarch64FaultSources[source]; 110312570Sgiacomo.travaglini@arm.com } 110412570Sgiacomo.travaglini@arm.com 110512570Sgiacomo.travaglini@arm.com return fsc; 110612570Sgiacomo.travaglini@arm.com} 110712570Sgiacomo.travaglini@arm.com 110812570Sgiacomo.travaglini@arm.comtemplate<class T> 110910037SARM gem5 DevelopersFSR 111012570Sgiacomo.travaglini@arm.comAbortFault<T>::getFsr(ThreadContext *tc) const 111110037SARM gem5 Developers{ 11127362Sgblack@eecs.umich.edu FSR fsr = 0; 11138314Sgeoffrey.blake@arm.com 111412570Sgiacomo.travaglini@arm.com auto fsc = getFaultStatusCode(tc); 111512570Sgiacomo.travaglini@arm.com 111612570Sgiacomo.travaglini@arm.com // AArch32 111712570Sgiacomo.travaglini@arm.com assert(tranMethod != ArmFault::UnknownTran); 111812570Sgiacomo.travaglini@arm.com if (tranMethod == ArmFault::LpaeTran) { 111912570Sgiacomo.travaglini@arm.com fsr.status = fsc; 112012570Sgiacomo.travaglini@arm.com fsr.lpae = 1; 112110037SARM gem5 Developers } else { 112212570Sgiacomo.travaglini@arm.com fsr.fsLow = bits(fsc, 3, 0); 112312570Sgiacomo.travaglini@arm.com fsr.fsHigh = bits(fsc, 4); 112412570Sgiacomo.travaglini@arm.com fsr.domain = static_cast<uint8_t>(domain); 112510037SARM gem5 Developers } 112612570Sgiacomo.travaglini@arm.com 112712570Sgiacomo.travaglini@arm.com fsr.wnr = (write ? 1 : 0); 112812570Sgiacomo.travaglini@arm.com fsr.ext = 0; 112912570Sgiacomo.travaglini@arm.com 113010037SARM gem5 Developers return fsr; 113110037SARM gem5 Developers} 113210037SARM gem5 Developers 113310037SARM gem5 Developerstemplate<class T> 113410037SARM gem5 Developersbool 113510037SARM gem5 DevelopersAbortFault<T>::abortDisable(ThreadContext *tc) 113610037SARM gem5 Developers{ 113710037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 113810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 113910037SARM gem5 Developers return (!scr.ns || scr.aw); 114010037SARM gem5 Developers } 114110037SARM gem5 Developers return true; 114210037SARM gem5 Developers} 114310037SARM gem5 Developers 114410037SARM gem5 Developerstemplate<class T> 114510037SARM gem5 Developersvoid 114610037SARM gem5 DevelopersAbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 114710037SARM gem5 Developers{ 114810037SARM gem5 Developers switch (id) 114910037SARM gem5 Developers { 115010037SARM gem5 Developers case ArmFault::S1PTW: 115110037SARM gem5 Developers s1ptw = val; 115210037SARM gem5 Developers break; 115310037SARM gem5 Developers case ArmFault::OVA: 115410037SARM gem5 Developers OVAddr = val; 115510037SARM gem5 Developers break; 115610037SARM gem5 Developers 115710037SARM gem5 Developers // Just ignore unknown ID's 115810037SARM gem5 Developers default: 115910037SARM gem5 Developers break; 116010037SARM gem5 Developers } 116110037SARM gem5 Developers} 116210037SARM gem5 Developers 116310037SARM gem5 Developerstemplate<class T> 116410037SARM gem5 Developersuint32_t 116510037SARM gem5 DevelopersAbortFault<T>::iss() const 116610037SARM gem5 Developers{ 116710037SARM gem5 Developers uint32_t val; 116810037SARM gem5 Developers 116910037SARM gem5 Developers val = srcEncoded & 0x3F; 117010037SARM gem5 Developers val |= write << 6; 117110037SARM gem5 Developers val |= s1ptw << 7; 117210037SARM gem5 Developers return (val); 117310037SARM gem5 Developers} 117410037SARM gem5 Developers 117510037SARM gem5 Developerstemplate<class T> 117610037SARM gem5 Developersbool 117710037SARM gem5 DevelopersAbortFault<T>::isMMUFault() const 117810037SARM gem5 Developers{ 117910037SARM gem5 Developers // NOTE: Not relying on LL information being aligned to lowest bits here 118010037SARM gem5 Developers return 118110037SARM gem5 Developers (source == ArmFault::AlignmentFault) || 118210037SARM gem5 Developers ((source >= ArmFault::TranslationLL) && 118310037SARM gem5 Developers (source < ArmFault::TranslationLL + 4)) || 118410037SARM gem5 Developers ((source >= ArmFault::AccessFlagLL) && 118510037SARM gem5 Developers (source < ArmFault::AccessFlagLL + 4)) || 118610037SARM gem5 Developers ((source >= ArmFault::DomainLL) && 118710037SARM gem5 Developers (source < ArmFault::DomainLL + 4)) || 118810037SARM gem5 Developers ((source >= ArmFault::PermissionLL) && 118910037SARM gem5 Developers (source < ArmFault::PermissionLL + 4)); 119010037SARM gem5 Developers} 119110037SARM gem5 Developers 119210037SARM gem5 DevelopersExceptionClass 119310037SARM gem5 DevelopersPrefetchAbort::ec(ThreadContext *tc) const 119410037SARM gem5 Developers{ 119510037SARM gem5 Developers if (to64) { 119610037SARM gem5 Developers // AArch64 119710037SARM gem5 Developers if (toEL == fromEL) 119810037SARM gem5 Developers return EC_PREFETCH_ABORT_CURR_EL; 119910037SARM gem5 Developers else 120010037SARM gem5 Developers return EC_PREFETCH_ABORT_LOWER_EL; 120110037SARM gem5 Developers } else { 120210037SARM gem5 Developers // AArch32 120310037SARM gem5 Developers // Abort faults have different EC codes depending on whether 120410037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 120510037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 120610037SARM gem5 Developers 120710037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 120810037SARM gem5 Developers 120910037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 121010037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 121110037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 121210037SARM gem5 Developers } 121310037SARM gem5 Developers return ec; 121410037SARM gem5 Developers } 121510037SARM gem5 Developers} 121610037SARM gem5 Developers 121710037SARM gem5 Developersbool 121810037SARM gem5 DevelopersPrefetchAbort::routeToMonitor(ThreadContext *tc) const 121910037SARM gem5 Developers{ 122010037SARM gem5 Developers SCR scr = 0; 122110037SARM gem5 Developers if (from64) 122210037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 122310037SARM gem5 Developers else 122410037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 122510037SARM gem5 Developers 122610037SARM gem5 Developers return scr.ea && !isMMUFault(); 122710037SARM gem5 Developers} 122810037SARM gem5 Developers 122910037SARM gem5 Developersbool 123010037SARM gem5 DevelopersPrefetchAbort::routeToHyp(ThreadContext *tc) const 123110037SARM gem5 Developers{ 123210037SARM gem5 Developers bool toHyp; 123310037SARM gem5 Developers 123410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 123510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 123610037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 123710037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 123810037SARM gem5 Developers 123910037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 124010037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 124110037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 124210037SARM gem5 Developers toHyp |= (stage2 || 124310037SARM gem5 Developers ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 124410037SARM gem5 Developers ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 124511581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 124610037SARM gem5 Developers return toHyp; 124710037SARM gem5 Developers} 124810037SARM gem5 Developers 124910037SARM gem5 DevelopersExceptionClass 125010037SARM gem5 DevelopersDataAbort::ec(ThreadContext *tc) const 125110037SARM gem5 Developers{ 125210037SARM gem5 Developers if (to64) { 125310037SARM gem5 Developers // AArch64 125410037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 125510367SAndrew.Bardsley@arm.com panic("Asynchronous External Abort should be handled with " 125610367SAndrew.Bardsley@arm.com "SystemErrors (SErrors)!"); 125710037SARM gem5 Developers } 125810037SARM gem5 Developers if (toEL == fromEL) 125910037SARM gem5 Developers return EC_DATA_ABORT_CURR_EL; 126010037SARM gem5 Developers else 126110037SARM gem5 Developers return EC_DATA_ABORT_LOWER_EL; 126210037SARM gem5 Developers } else { 126310037SARM gem5 Developers // AArch32 126410037SARM gem5 Developers // Abort faults have different EC codes depending on whether 126510037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 126610037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 126710037SARM gem5 Developers 126810037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 126910037SARM gem5 Developers 127010037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 127110037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 127210037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 127310037SARM gem5 Developers } 127410037SARM gem5 Developers return ec; 127510037SARM gem5 Developers } 127610037SARM gem5 Developers} 127710037SARM gem5 Developers 127810037SARM gem5 Developersbool 127910037SARM gem5 DevelopersDataAbort::routeToMonitor(ThreadContext *tc) const 128010037SARM gem5 Developers{ 128110037SARM gem5 Developers SCR scr = 0; 128210037SARM gem5 Developers if (from64) 128310037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 128410037SARM gem5 Developers else 128510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 128610037SARM gem5 Developers 128710037SARM gem5 Developers return scr.ea && !isMMUFault(); 128810037SARM gem5 Developers} 128910037SARM gem5 Developers 129010037SARM gem5 Developersbool 129110037SARM gem5 DevelopersDataAbort::routeToHyp(ThreadContext *tc) const 129210037SARM gem5 Developers{ 129310037SARM gem5 Developers bool toHyp; 129410037SARM gem5 Developers 129510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 129610037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 129710037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 129810037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 129910037SARM gem5 Developers 130010037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 130110037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 130210037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 130310037SARM gem5 Developers toHyp |= (stage2 || 130410037SARM gem5 Developers ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 130510037SARM gem5 Developers ((source == DebugEvent) && hdcr.tde) ) 130610037SARM gem5 Developers ) || 130710037SARM gem5 Developers ( (cpsr.mode == MODE_USER) && hcr.tge && 130810037SARM gem5 Developers ((source == AlignmentFault) || 130910037SARM gem5 Developers (source == SynchronousExternalAbort)) 131010037SARM gem5 Developers ) 131111581SDylan.Johnson@ARM.com ) && !inSecureState(tc); 131210037SARM gem5 Developers return toHyp; 131310037SARM gem5 Developers} 131410037SARM gem5 Developers 131510037SARM gem5 Developersuint32_t 131610037SARM gem5 DevelopersDataAbort::iss() const 131710037SARM gem5 Developers{ 131810037SARM gem5 Developers uint32_t val; 131910037SARM gem5 Developers 132010037SARM gem5 Developers // Add on the data abort specific fields to the generic abort ISS value 132110037SARM gem5 Developers val = AbortFault<DataAbort>::iss(); 132210037SARM gem5 Developers // ISS is valid if not caused by a stage 1 page table walk, and when taken 132310037SARM gem5 Developers // to AArch64 only when directed to EL2 132410037SARM gem5 Developers if (!s1ptw && (!to64 || toEL == EL2)) { 132510037SARM gem5 Developers val |= isv << 24; 132610037SARM gem5 Developers if (isv) { 132710037SARM gem5 Developers val |= sas << 22; 132810037SARM gem5 Developers val |= sse << 21; 132910037SARM gem5 Developers val |= srt << 16; 133010037SARM gem5 Developers // AArch64 only. These assignments are safe on AArch32 as well 133110037SARM gem5 Developers // because these vars are initialized to false 133210037SARM gem5 Developers val |= sf << 15; 133310037SARM gem5 Developers val |= ar << 14; 133410037SARM gem5 Developers } 133510037SARM gem5 Developers } 133610037SARM gem5 Developers return (val); 133710037SARM gem5 Developers} 133810037SARM gem5 Developers 133910037SARM gem5 Developersvoid 134010037SARM gem5 DevelopersDataAbort::annotate(AnnotationIDs id, uint64_t val) 134110037SARM gem5 Developers{ 134210037SARM gem5 Developers AbortFault<DataAbort>::annotate(id, val); 134310037SARM gem5 Developers switch (id) 134410037SARM gem5 Developers { 134510037SARM gem5 Developers case SAS: 134610037SARM gem5 Developers isv = true; 134710037SARM gem5 Developers sas = val; 134810037SARM gem5 Developers break; 134910037SARM gem5 Developers case SSE: 135010037SARM gem5 Developers isv = true; 135110037SARM gem5 Developers sse = val; 135210037SARM gem5 Developers break; 135310037SARM gem5 Developers case SRT: 135410037SARM gem5 Developers isv = true; 135510037SARM gem5 Developers srt = val; 135610037SARM gem5 Developers break; 135710037SARM gem5 Developers case SF: 135810037SARM gem5 Developers isv = true; 135910037SARM gem5 Developers sf = val; 136010037SARM gem5 Developers break; 136110037SARM gem5 Developers case AR: 136210037SARM gem5 Developers isv = true; 136310037SARM gem5 Developers ar = val; 136410037SARM gem5 Developers break; 136510037SARM gem5 Developers // Just ignore unknown ID's 136610037SARM gem5 Developers default: 136710037SARM gem5 Developers break; 136810037SARM gem5 Developers } 136910037SARM gem5 Developers} 137010037SARM gem5 Developers 137110037SARM gem5 Developersvoid 137210417Sandreas.hansson@arm.comVirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 137310037SARM gem5 Developers{ 137410037SARM gem5 Developers AbortFault<VirtualDataAbort>::invoke(tc, inst); 137510037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 137610037SARM gem5 Developers hcr.va = 0; 137710037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 137810037SARM gem5 Developers} 137910037SARM gem5 Developers 138010037SARM gem5 Developersbool 138110037SARM gem5 DevelopersInterrupt::routeToMonitor(ThreadContext *tc) const 138210037SARM gem5 Developers{ 138310037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 138410037SARM gem5 Developers SCR scr = 0; 138510037SARM gem5 Developers if (from64) 138610037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 138710037SARM gem5 Developers else 138810037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 138910037SARM gem5 Developers return scr.irq; 139010037SARM gem5 Developers} 139110037SARM gem5 Developers 139210037SARM gem5 Developersbool 139310037SARM gem5 DevelopersInterrupt::routeToHyp(ThreadContext *tc) const 139410037SARM gem5 Developers{ 139510037SARM gem5 Developers bool toHyp; 139610037SARM gem5 Developers 139710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 139810037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 139910037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 140010037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 140111581SDylan.Johnson@ARM.com toHyp = (!scr.irq && hcr.imo && !inSecureState(tc)) || 140210037SARM gem5 Developers (cpsr.mode == MODE_HYP); 140310037SARM gem5 Developers return toHyp; 140410037SARM gem5 Developers} 140510037SARM gem5 Developers 140610037SARM gem5 Developersbool 140710037SARM gem5 DevelopersInterrupt::abortDisable(ThreadContext *tc) 140810037SARM gem5 Developers{ 140910037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 141010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 141110037SARM gem5 Developers return (!scr.ns || scr.aw); 141210037SARM gem5 Developers } 141310037SARM gem5 Developers return true; 141410037SARM gem5 Developers} 141510037SARM gem5 Developers 141610037SARM gem5 DevelopersVirtualInterrupt::VirtualInterrupt() 141710037SARM gem5 Developers{} 141810037SARM gem5 Developers 141910037SARM gem5 Developersbool 142010037SARM gem5 DevelopersFastInterrupt::routeToMonitor(ThreadContext *tc) const 142110037SARM gem5 Developers{ 142210037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 142310037SARM gem5 Developers SCR scr = 0; 142410037SARM gem5 Developers if (from64) 142510037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 142610037SARM gem5 Developers else 142710037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 142810037SARM gem5 Developers return scr.fiq; 142910037SARM gem5 Developers} 143010037SARM gem5 Developers 143110037SARM gem5 Developersbool 143210037SARM gem5 DevelopersFastInterrupt::routeToHyp(ThreadContext *tc) const 143310037SARM gem5 Developers{ 143410037SARM gem5 Developers bool toHyp; 143510037SARM gem5 Developers 143610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 143710037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 143810037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 143910037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 144011581SDylan.Johnson@ARM.com toHyp = (!scr.fiq && hcr.fmo && !inSecureState(tc)) || 144110037SARM gem5 Developers (cpsr.mode == MODE_HYP); 144210037SARM gem5 Developers return toHyp; 144310037SARM gem5 Developers} 144410037SARM gem5 Developers 144510037SARM gem5 Developersbool 144610037SARM gem5 DevelopersFastInterrupt::abortDisable(ThreadContext *tc) 144710037SARM gem5 Developers{ 144810037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 144910037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 145010037SARM gem5 Developers return (!scr.ns || scr.aw); 145110037SARM gem5 Developers } 145210037SARM gem5 Developers return true; 145310037SARM gem5 Developers} 145410037SARM gem5 Developers 145510037SARM gem5 Developersbool 145610037SARM gem5 DevelopersFastInterrupt::fiqDisable(ThreadContext *tc) 145710037SARM gem5 Developers{ 145810037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc)) { 145910037SARM gem5 Developers return true; 146010037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc)) { 146110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 146210037SARM gem5 Developers return (!scr.ns || scr.fw); 146310037SARM gem5 Developers } 146410037SARM gem5 Developers return true; 146510037SARM gem5 Developers} 146610037SARM gem5 Developers 146710037SARM gem5 DevelopersVirtualFastInterrupt::VirtualFastInterrupt() 146810037SARM gem5 Developers{} 146910037SARM gem5 Developers 147010037SARM gem5 Developersvoid 147110417Sandreas.hansson@arm.comPCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 147210037SARM gem5 Developers{ 147310037SARM gem5 Developers ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 147410037SARM gem5 Developers assert(from64); 147510037SARM gem5 Developers // Set the FAR 147610037SARM gem5 Developers tc->setMiscReg(getFaultAddrReg64(), faultPC); 147710037SARM gem5 Developers} 147810037SARM gem5 Developers 147912568Sgiacomo.travaglini@arm.combool 148012568Sgiacomo.travaglini@arm.comPCAlignmentFault::routeToHyp(ThreadContext *tc) const 148112568Sgiacomo.travaglini@arm.com{ 148212568Sgiacomo.travaglini@arm.com bool toHyp = false; 148312568Sgiacomo.travaglini@arm.com 148412568Sgiacomo.travaglini@arm.com SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 148512568Sgiacomo.travaglini@arm.com HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 148612568Sgiacomo.travaglini@arm.com CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 148712568Sgiacomo.travaglini@arm.com 148812568Sgiacomo.travaglini@arm.com // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 148912568Sgiacomo.travaglini@arm.com toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.el == EL0); 149012568Sgiacomo.travaglini@arm.com return toHyp; 149112568Sgiacomo.travaglini@arm.com} 149212568Sgiacomo.travaglini@arm.com 149310037SARM gem5 DevelopersSPAlignmentFault::SPAlignmentFault() 149410037SARM gem5 Developers{} 149510037SARM gem5 Developers 149610037SARM gem5 DevelopersSystemError::SystemError() 149710037SARM gem5 Developers{} 149810037SARM gem5 Developers 149910037SARM gem5 Developersvoid 150010417Sandreas.hansson@arm.comSystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 150110037SARM gem5 Developers{ 150211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 150310037SARM gem5 Developers ArmFault::invoke(tc, inst); 150410037SARM gem5 Developers} 150510037SARM gem5 Developers 150610037SARM gem5 Developersbool 150710037SARM gem5 DevelopersSystemError::routeToMonitor(ThreadContext *tc) const 150810037SARM gem5 Developers{ 150910037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 151010037SARM gem5 Developers assert(from64); 151110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 151210037SARM gem5 Developers return scr.ea; 151310037SARM gem5 Developers} 151410037SARM gem5 Developers 151510037SARM gem5 Developersbool 151610037SARM gem5 DevelopersSystemError::routeToHyp(ThreadContext *tc) const 151710037SARM gem5 Developers{ 151810037SARM gem5 Developers bool toHyp; 151910037SARM gem5 Developers assert(from64); 152010037SARM gem5 Developers 152110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 152210037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 152310037SARM gem5 Developers 152411581SDylan.Johnson@ARM.com toHyp = (!scr.ea && hcr.amo && !inSecureState(tc)) || 152511581SDylan.Johnson@ARM.com (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(tc)); 152610037SARM gem5 Developers return toHyp; 15277362Sgblack@eecs.umich.edu} 15287362Sgblack@eecs.umich.edu 152912299Sandreas.sandberg@arm.com 153012299Sandreas.sandberg@arm.comSoftwareBreakpoint::SoftwareBreakpoint(ExtMachInst _mach_inst, uint32_t _iss) 153112299Sandreas.sandberg@arm.com : ArmFaultVals<SoftwareBreakpoint>(_mach_inst, _iss) 153212299Sandreas.sandberg@arm.com{} 153312299Sandreas.sandberg@arm.com 153412299Sandreas.sandberg@arm.combool 153512299Sandreas.sandberg@arm.comSoftwareBreakpoint::routeToHyp(ThreadContext *tc) const 153612299Sandreas.sandberg@arm.com{ 153712299Sandreas.sandberg@arm.com assert(from64); 153812299Sandreas.sandberg@arm.com 153912299Sandreas.sandberg@arm.com const bool have_el2 = ArmSystem::haveVirtualization(tc); 154012299Sandreas.sandberg@arm.com 154112299Sandreas.sandberg@arm.com const HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR_EL2); 154212299Sandreas.sandberg@arm.com const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2); 154312299Sandreas.sandberg@arm.com 154412299Sandreas.sandberg@arm.com return have_el2 && !inSecureState(tc) && fromEL <= EL1 && 154512299Sandreas.sandberg@arm.com (hcr.tge || mdcr.tde); 154612299Sandreas.sandberg@arm.com} 154712299Sandreas.sandberg@arm.com 154812732Sandreas.sandberg@arm.comExceptionClass 154912732Sandreas.sandberg@arm.comSoftwareBreakpoint::ec(ThreadContext *tc) const 155012732Sandreas.sandberg@arm.com{ 155112732Sandreas.sandberg@arm.com return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec; 155212732Sandreas.sandberg@arm.com} 155312732Sandreas.sandberg@arm.com 15547652Sminkyu.jeong@arm.comvoid 155510417Sandreas.hansson@arm.comArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 15568518Sgeoffrey.blake@arm.com DPRINTF(Faults, "Invoking ArmSev Fault\n"); 15578806Sgblack@eecs.umich.edu if (!FullSystem) 15588806Sgblack@eecs.umich.edu return; 15598806Sgblack@eecs.umich.edu 15608806Sgblack@eecs.umich.edu // Set sev_mailbox to 1, clear the pending interrupt from remote 15618806Sgblack@eecs.umich.edu // SEV execution and let pipeline continue as pcState is still 15628806Sgblack@eecs.umich.edu // valid. 15638806Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 156411150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 15658518Sgeoffrey.blake@arm.com} 15668518Sgeoffrey.blake@arm.com 156710037SARM gem5 Developers// Instantiate all the templates to make the linker happy 156810037SARM gem5 Developerstemplate class ArmFaultVals<Reset>; 156910037SARM gem5 Developerstemplate class ArmFaultVals<UndefinedInstruction>; 157010037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorCall>; 157110037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorCall>; 157210037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorCall>; 157310037SARM gem5 Developerstemplate class ArmFaultVals<PrefetchAbort>; 157410037SARM gem5 Developerstemplate class ArmFaultVals<DataAbort>; 157510037SARM gem5 Developerstemplate class ArmFaultVals<VirtualDataAbort>; 157610037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorTrap>; 157710037SARM gem5 Developerstemplate class ArmFaultVals<Interrupt>; 157810037SARM gem5 Developerstemplate class ArmFaultVals<VirtualInterrupt>; 157910037SARM gem5 Developerstemplate class ArmFaultVals<FastInterrupt>; 158010037SARM gem5 Developerstemplate class ArmFaultVals<VirtualFastInterrupt>; 158110037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorTrap>; 158210037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorTrap>; 158310037SARM gem5 Developerstemplate class ArmFaultVals<PCAlignmentFault>; 158410037SARM gem5 Developerstemplate class ArmFaultVals<SPAlignmentFault>; 158510037SARM gem5 Developerstemplate class ArmFaultVals<SystemError>; 158612299Sandreas.sandberg@arm.comtemplate class ArmFaultVals<SoftwareBreakpoint>; 158710037SARM gem5 Developerstemplate class ArmFaultVals<ArmSev>; 158810037SARM gem5 Developerstemplate class AbortFault<PrefetchAbort>; 158910037SARM gem5 Developerstemplate class AbortFault<DataAbort>; 159010037SARM gem5 Developerstemplate class AbortFault<VirtualDataAbort>; 159110037SARM gem5 Developers 159210037SARM gem5 Developers 159310037SARM gem5 DevelopersIllegalInstSetStateFault::IllegalInstSetStateFault() 159410037SARM gem5 Developers{} 159510037SARM gem5 Developers 15966019Shines@cs.fsu.edu 15976019Shines@cs.fsu.edu} // namespace ArmISA 1598