faults.cc revision 11576
1/* 2 * Copyright (c) 2010, 2012-2014, 2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2003-2005 The Regents of The University of Michigan 15 * Copyright (c) 2007-2008 The Florida State University 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 * 41 * Authors: Ali Saidi 42 * Gabe Black 43 * Giacomo Gabrielli 44 * Thomas Grocutt 45 */ 46 47#include "arch/arm/faults.hh" 48#include "arch/arm/system.hh" 49#include "arch/arm/utility.hh" 50#include "arch/arm/insts/static_inst.hh" 51#include "base/compiler.hh" 52#include "base/trace.hh" 53#include "cpu/base.hh" 54#include "cpu/thread_context.hh" 55#include "debug/Faults.hh" 56#include "sim/full_system.hh" 57 58namespace ArmISA 59{ 60 61uint8_t ArmFault::shortDescFaultSources[] = { 62 0x01, // AlignmentFault 63 0x04, // InstructionCacheMaintenance 64 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 65 0x0c, // SynchExtAbtOnTranslTableWalkL1 66 0x0e, // SynchExtAbtOnTranslTableWalkL2 67 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 68 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 69 0x1c, // SynchPtyErrOnTranslTableWalkL1 70 0x1e, // SynchPtyErrOnTranslTableWalkL2 71 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 72 0xff, // TranslationL0 (INVALID) 73 0x05, // TranslationL1 74 0x07, // TranslationL2 75 0xff, // TranslationL3 (INVALID) 76 0xff, // AccessFlagL0 (INVALID) 77 0x03, // AccessFlagL1 78 0x06, // AccessFlagL2 79 0xff, // AccessFlagL3 (INVALID) 80 0xff, // DomainL0 (INVALID) 81 0x09, // DomainL1 82 0x0b, // DomainL2 83 0xff, // DomainL3 (INVALID) 84 0xff, // PermissionL0 (INVALID) 85 0x0d, // PermissionL1 86 0x0f, // PermissionL2 87 0xff, // PermissionL3 (INVALID) 88 0x02, // DebugEvent 89 0x08, // SynchronousExternalAbort 90 0x10, // TLBConflictAbort 91 0x19, // SynchPtyErrOnMemoryAccess 92 0x16, // AsynchronousExternalAbort 93 0x18, // AsynchPtyErrOnMemoryAccess 94 0xff, // AddressSizeL0 (INVALID) 95 0xff, // AddressSizeL1 (INVALID) 96 0xff, // AddressSizeL2 (INVALID) 97 0xff, // AddressSizeL3 (INVALID) 98 0x40, // PrefetchTLBMiss 99 0x80 // PrefetchUncacheable 100}; 101 102static_assert(sizeof(ArmFault::shortDescFaultSources) == 103 ArmFault::NumFaultSources, 104 "Invalid size of ArmFault::shortDescFaultSources[]"); 105 106uint8_t ArmFault::longDescFaultSources[] = { 107 0x21, // AlignmentFault 108 0xff, // InstructionCacheMaintenance (INVALID) 109 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 110 0x15, // SynchExtAbtOnTranslTableWalkL1 111 0x16, // SynchExtAbtOnTranslTableWalkL2 112 0x17, // SynchExtAbtOnTranslTableWalkL3 113 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 114 0x1d, // SynchPtyErrOnTranslTableWalkL1 115 0x1e, // SynchPtyErrOnTranslTableWalkL2 116 0x1f, // SynchPtyErrOnTranslTableWalkL3 117 0xff, // TranslationL0 (INVALID) 118 0x05, // TranslationL1 119 0x06, // TranslationL2 120 0x07, // TranslationL3 121 0xff, // AccessFlagL0 (INVALID) 122 0x09, // AccessFlagL1 123 0x0a, // AccessFlagL2 124 0x0b, // AccessFlagL3 125 0xff, // DomainL0 (INVALID) 126 0x3d, // DomainL1 127 0x3e, // DomainL2 128 0xff, // DomainL3 (RESERVED) 129 0xff, // PermissionL0 (INVALID) 130 0x0d, // PermissionL1 131 0x0e, // PermissionL2 132 0x0f, // PermissionL3 133 0x22, // DebugEvent 134 0x10, // SynchronousExternalAbort 135 0x30, // TLBConflictAbort 136 0x18, // SynchPtyErrOnMemoryAccess 137 0x11, // AsynchronousExternalAbort 138 0x19, // AsynchPtyErrOnMemoryAccess 139 0xff, // AddressSizeL0 (INVALID) 140 0xff, // AddressSizeL1 (INVALID) 141 0xff, // AddressSizeL2 (INVALID) 142 0xff, // AddressSizeL3 (INVALID) 143 0x40, // PrefetchTLBMiss 144 0x80 // PrefetchUncacheable 145}; 146 147static_assert(sizeof(ArmFault::longDescFaultSources) == 148 ArmFault::NumFaultSources, 149 "Invalid size of ArmFault::longDescFaultSources[]"); 150 151uint8_t ArmFault::aarch64FaultSources[] = { 152 0x21, // AlignmentFault 153 0xff, // InstructionCacheMaintenance (INVALID) 154 0x14, // SynchExtAbtOnTranslTableWalkL0 155 0x15, // SynchExtAbtOnTranslTableWalkL1 156 0x16, // SynchExtAbtOnTranslTableWalkL2 157 0x17, // SynchExtAbtOnTranslTableWalkL3 158 0x1c, // SynchPtyErrOnTranslTableWalkL0 159 0x1d, // SynchPtyErrOnTranslTableWalkL1 160 0x1e, // SynchPtyErrOnTranslTableWalkL2 161 0x1f, // SynchPtyErrOnTranslTableWalkL3 162 0x04, // TranslationL0 163 0x05, // TranslationL1 164 0x06, // TranslationL2 165 0x07, // TranslationL3 166 0x08, // AccessFlagL0 167 0x09, // AccessFlagL1 168 0x0a, // AccessFlagL2 169 0x0b, // AccessFlagL3 170 // @todo: Section & Page Domain Fault in AArch64? 171 0xff, // DomainL0 (INVALID) 172 0xff, // DomainL1 (INVALID) 173 0xff, // DomainL2 (INVALID) 174 0xff, // DomainL3 (INVALID) 175 0x0c, // PermissionL0 176 0x0d, // PermissionL1 177 0x0e, // PermissionL2 178 0x0f, // PermissionL3 179 0xff, // DebugEvent (INVALID) 180 0x10, // SynchronousExternalAbort 181 0x30, // TLBConflictAbort 182 0x18, // SynchPtyErrOnMemoryAccess 183 0xff, // AsynchronousExternalAbort (INVALID) 184 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 185 0x00, // AddressSizeL0 186 0x01, // AddressSizeL1 187 0x02, // AddressSizeL2 188 0x03, // AddressSizeL3 189 0x40, // PrefetchTLBMiss 190 0x80 // PrefetchUncacheable 191}; 192 193static_assert(sizeof(ArmFault::aarch64FaultSources) == 194 ArmFault::NumFaultSources, 195 "Invalid size of ArmFault::aarch64FaultSources[]"); 196 197// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 198// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 199// {A, F} disable, class, stat 200template<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = { 201 // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 202 // location in AArch64) 203 "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 204 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 205}; 206template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = { 207 "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 208 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat() 209}; 210template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = { 211 "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 212 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat() 213}; 214template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = { 215 "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 216 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat() 217}; 218template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = { 219 "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 220 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat() 221}; 222template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = { 223 "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 224 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat() 225}; 226template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = { 227 "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 228 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat() 229}; 230template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = { 231 "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 232 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat() 233}; 234template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = { 235 // @todo: double check these values 236 "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 237 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 238}; 239template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = { 240 "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 241 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat() 242}; 243template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = { 244 "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 245 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat() 246}; 247template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = { 248 "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 249 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 250}; 251template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = { 252 "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 253 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat() 254}; 255template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = { 256 // Some dummy values (SupervisorTrap is AArch64-only) 257 "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 258 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 259}; 260template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = { 261 // Some dummy values (SecureMonitorTrap is AArch64-only) 262 "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON, 263 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 264}; 265template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = { 266 // Some dummy values (PCAlignmentFault is AArch64-only) 267 "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 268 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat() 269}; 270template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = { 271 // Some dummy values (SPAlignmentFault is AArch64-only) 272 "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 273 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 274}; 275template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 276 // Some dummy values (SError is AArch64-only) 277 "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 278 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 279}; 280template<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = { 281 // Some dummy values 282 "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 283 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 284}; 285template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 286 // Some dummy values 287 "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 288 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 289}; 290template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 291 // Some dummy values (SPAlignmentFault is AArch64-only) 292 "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 293 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat() 294}; 295 296Addr 297ArmFault::getVector(ThreadContext *tc) 298{ 299 Addr base; 300 301 // ARM ARM issue C B1.8.1 302 bool haveSecurity = ArmSystem::haveSecurity(tc); 303 304 // panic if SCTLR.VE because I have no idea what to do with vectored 305 // interrupts 306 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 307 assert(!sctlr.ve); 308 // Check for invalid modes 309 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 310 assert(haveSecurity || cpsr.mode != MODE_MON); 311 assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 312 313 switch (cpsr.mode) 314 { 315 case MODE_MON: 316 base = tc->readMiscReg(MISCREG_MVBAR); 317 break; 318 case MODE_HYP: 319 base = tc->readMiscReg(MISCREG_HVBAR); 320 break; 321 default: 322 if (sctlr.v) { 323 base = HighVecs; 324 } else { 325 base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 326 } 327 break; 328 } 329 return base + offset(tc); 330} 331 332Addr 333ArmFault::getVector64(ThreadContext *tc) 334{ 335 Addr vbar; 336 switch (toEL) { 337 case EL3: 338 assert(ArmSystem::haveSecurity(tc)); 339 vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 340 break; 341 case EL2: 342 assert(ArmSystem::haveVirtualization(tc)); 343 vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 344 break; 345 case EL1: 346 vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 347 break; 348 default: 349 panic("Invalid target exception level"); 350 break; 351 } 352 return vbar + offset64(); 353} 354 355MiscRegIndex 356ArmFault::getSyndromeReg64() const 357{ 358 switch (toEL) { 359 case EL1: 360 return MISCREG_ESR_EL1; 361 case EL2: 362 return MISCREG_ESR_EL2; 363 case EL3: 364 return MISCREG_ESR_EL3; 365 default: 366 panic("Invalid exception level"); 367 break; 368 } 369} 370 371MiscRegIndex 372ArmFault::getFaultAddrReg64() const 373{ 374 switch (toEL) { 375 case EL1: 376 return MISCREG_FAR_EL1; 377 case EL2: 378 return MISCREG_FAR_EL2; 379 case EL3: 380 return MISCREG_FAR_EL3; 381 default: 382 panic("Invalid exception level"); 383 break; 384 } 385} 386 387void 388ArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 389{ 390 uint32_t value; 391 uint32_t exc_class = (uint32_t) ec(tc); 392 uint32_t issVal = iss(); 393 assert(!from64 || ArmSystem::highestELIs64(tc)); 394 395 value = exc_class << 26; 396 397 // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 398 // 0x25) for which the ISS information is not valid (ARMv7). 399 // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 400 // valid it is treated as RES1. 401 if (to64) { 402 value |= 1 << 25; 403 } else if ((bits(exc_class, 5, 3) != 4) || 404 (bits(exc_class, 2) && bits(issVal, 24))) { 405 if (!machInst.thumb || machInst.bigThumb) 406 value |= 1 << 25; 407 } 408 // Condition code valid for EC[5:4] nonzero 409 if (!from64 && ((bits(exc_class, 5, 4) == 0) && 410 (bits(exc_class, 3, 0) != 0))) { 411 if (!machInst.thumb) { 412 uint32_t cond; 413 ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 414 // If its on unconditional instruction report with a cond code of 415 // 0xE, ie the unconditional code 416 cond = (condCode == COND_UC) ? COND_AL : condCode; 417 value |= cond << 20; 418 value |= 1 << 24; 419 } 420 value |= bits(issVal, 19, 0); 421 } else { 422 value |= issVal; 423 } 424 tc->setMiscReg(syndrome_reg, value); 425} 426 427void 428ArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 429{ 430 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 431 432 if (ArmSystem::highestELIs64(tc)) { // ARMv8 433 // Determine source exception level and mode 434 fromMode = (OperatingMode) (uint8_t) cpsr.mode; 435 fromEL = opModeToEL(fromMode); 436 if (opModeIs64(fromMode)) 437 from64 = true; 438 439 // Determine target exception level 440 if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) 441 toEL = EL3; 442 else 443 toEL = opModeToEL(nextMode()); 444 if (fromEL > toEL) 445 toEL = fromEL; 446 447 if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) { 448 // Invoke exception handler in AArch64 state 449 to64 = true; 450 invoke64(tc, inst); 451 return; 452 } 453 } 454 455 // ARMv7 (ARM ARM issue C B1.9) 456 457 bool have_security = ArmSystem::haveSecurity(tc); 458 bool have_virtualization = ArmSystem::haveVirtualization(tc); 459 460 FaultBase::invoke(tc); 461 if (!FullSystem) 462 return; 463 countStat()++; 464 465 SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 466 SCR scr = tc->readMiscReg(MISCREG_SCR); 467 CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 468 saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 469 saved_cpsr.c = tc->readCCReg(CCREG_C); 470 saved_cpsr.v = tc->readCCReg(CCREG_V); 471 saved_cpsr.ge = tc->readCCReg(CCREG_GE); 472 473 Addr curPc M5_VAR_USED = tc->pcState().pc(); 474 ITSTATE it = tc->pcState().itstate(); 475 saved_cpsr.it2 = it.top6; 476 saved_cpsr.it1 = it.bottom2; 477 478 // if we have a valid instruction then use it to annotate this fault with 479 // extra information. This is used to generate the correct fault syndrome 480 // information 481 if (inst) { 482 ArmStaticInst *armInst = reinterpret_cast<ArmStaticInst *>(inst.get()); 483 armInst->annotateFault(this); 484 } 485 486 if (have_security && routeToMonitor(tc)) 487 cpsr.mode = MODE_MON; 488 else if (have_virtualization && routeToHyp(tc)) 489 cpsr.mode = MODE_HYP; 490 else 491 cpsr.mode = nextMode(); 492 493 // Ensure Secure state if initially in Monitor mode 494 if (have_security && saved_cpsr.mode == MODE_MON) { 495 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 496 if (scr.ns) { 497 scr.ns = 0; 498 tc->setMiscRegNoEffect(MISCREG_SCR, scr); 499 } 500 } 501 502 // some bits are set differently if we have been routed to hyp mode 503 if (cpsr.mode == MODE_HYP) { 504 SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 505 cpsr.t = hsctlr.te; 506 cpsr.e = hsctlr.ee; 507 if (!scr.ea) {cpsr.a = 1;} 508 if (!scr.fiq) {cpsr.f = 1;} 509 if (!scr.irq) {cpsr.i = 1;} 510 } else if (cpsr.mode == MODE_MON) { 511 // Special case handling when entering monitor mode 512 cpsr.t = sctlr.te; 513 cpsr.e = sctlr.ee; 514 cpsr.a = 1; 515 cpsr.f = 1; 516 cpsr.i = 1; 517 } else { 518 cpsr.t = sctlr.te; 519 cpsr.e = sctlr.ee; 520 521 // The *Disable functions are virtual and different per fault 522 cpsr.a = cpsr.a | abortDisable(tc); 523 cpsr.f = cpsr.f | fiqDisable(tc); 524 cpsr.i = 1; 525 } 526 cpsr.it1 = cpsr.it2 = 0; 527 cpsr.j = 0; 528 tc->setMiscReg(MISCREG_CPSR, cpsr); 529 530 // Make sure mailbox sets to one always 531 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 532 533 // Clear the exclusive monitor 534 tc->setMiscReg(MISCREG_LOCKFLAG, 0); 535 536 if (cpsr.mode == MODE_HYP) { 537 tc->setMiscReg(MISCREG_ELR_HYP, curPc + 538 (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 539 } else { 540 tc->setIntReg(INTREG_LR, curPc + 541 (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 542 } 543 544 switch (cpsr.mode) { 545 case MODE_FIQ: 546 tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 547 break; 548 case MODE_IRQ: 549 tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 550 break; 551 case MODE_SVC: 552 tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 553 break; 554 case MODE_MON: 555 assert(have_security); 556 tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 557 break; 558 case MODE_ABORT: 559 tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 560 break; 561 case MODE_UNDEFINED: 562 tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 563 if (ec(tc) != EC_UNKNOWN) 564 setSyndrome(tc, MISCREG_HSR); 565 break; 566 case MODE_HYP: 567 assert(have_virtualization); 568 tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 569 setSyndrome(tc, MISCREG_HSR); 570 break; 571 default: 572 panic("unknown Mode\n"); 573 } 574 575 Addr newPc = getVector(tc); 576 DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 577 name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 578 PCState pc(newPc); 579 pc.thumb(cpsr.t); 580 pc.nextThumb(pc.thumb()); 581 pc.jazelle(cpsr.j); 582 pc.nextJazelle(pc.jazelle()); 583 pc.aarch64(!cpsr.width); 584 pc.nextAArch64(!cpsr.width); 585 tc->pcState(pc); 586} 587 588void 589ArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 590{ 591 // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 592 MiscRegIndex elr_idx, spsr_idx; 593 switch (toEL) { 594 case EL1: 595 elr_idx = MISCREG_ELR_EL1; 596 spsr_idx = MISCREG_SPSR_EL1; 597 break; 598 case EL2: 599 assert(ArmSystem::haveVirtualization(tc)); 600 elr_idx = MISCREG_ELR_EL2; 601 spsr_idx = MISCREG_SPSR_EL2; 602 break; 603 case EL3: 604 assert(ArmSystem::haveSecurity(tc)); 605 elr_idx = MISCREG_ELR_EL3; 606 spsr_idx = MISCREG_SPSR_EL3; 607 break; 608 default: 609 panic("Invalid target exception level"); 610 break; 611 } 612 613 // Save process state into SPSR_ELx 614 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 615 CPSR spsr = cpsr; 616 spsr.nz = tc->readCCReg(CCREG_NZ); 617 spsr.c = tc->readCCReg(CCREG_C); 618 spsr.v = tc->readCCReg(CCREG_V); 619 if (from64) { 620 // Force some bitfields to 0 621 spsr.q = 0; 622 spsr.it1 = 0; 623 spsr.j = 0; 624 spsr.res0_23_22 = 0; 625 spsr.ge = 0; 626 spsr.it2 = 0; 627 spsr.t = 0; 628 } else { 629 spsr.ge = tc->readCCReg(CCREG_GE); 630 ITSTATE it = tc->pcState().itstate(); 631 spsr.it2 = it.top6; 632 spsr.it1 = it.bottom2; 633 // Force some bitfields to 0 634 spsr.res0_23_22 = 0; 635 spsr.ss = 0; 636 } 637 tc->setMiscReg(spsr_idx, spsr); 638 639 // Save preferred return address into ELR_ELx 640 Addr curr_pc = tc->pcState().pc(); 641 Addr ret_addr = curr_pc; 642 if (from64) 643 ret_addr += armPcElrOffset(); 644 else 645 ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 646 tc->setMiscReg(elr_idx, ret_addr); 647 648 // Update process state 649 OperatingMode64 mode = 0; 650 mode.spX = 1; 651 mode.el = toEL; 652 mode.width = 0; 653 cpsr.mode = mode; 654 cpsr.daif = 0xf; 655 cpsr.il = 0; 656 cpsr.ss = 0; 657 tc->setMiscReg(MISCREG_CPSR, cpsr); 658 659 // Set PC to start of exception handler 660 Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL); 661 DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 662 "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 663 PCState pc(new_pc); 664 pc.aarch64(!cpsr.width); 665 pc.nextAArch64(!cpsr.width); 666 tc->pcState(pc); 667 668 // If we have a valid instruction then use it to annotate this fault with 669 // extra information. This is used to generate the correct fault syndrome 670 // information 671 if (inst) 672 reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 673 // Save exception syndrome 674 if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 675 setSyndrome(tc, getSyndromeReg64()); 676} 677 678void 679Reset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 680{ 681 if (FullSystem) { 682 tc->getCpuPtr()->clearInterrupts(tc->threadId()); 683 tc->clearArchRegs(); 684 } 685 if (!ArmSystem::highestELIs64(tc)) { 686 ArmFault::invoke(tc, inst); 687 tc->setMiscReg(MISCREG_VMPIDR, 688 getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 689 690 // Unless we have SMC code to get us there, boot in HYP! 691 if (ArmSystem::haveVirtualization(tc) && 692 !ArmSystem::haveSecurity(tc)) { 693 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 694 cpsr.mode = MODE_HYP; 695 tc->setMiscReg(MISCREG_CPSR, cpsr); 696 } 697 } else { 698 // Advance the PC to the IMPLEMENTATION DEFINED reset value 699 PCState pc = ArmSystem::resetAddr64(tc); 700 pc.aarch64(true); 701 pc.nextAArch64(true); 702 tc->pcState(pc); 703 } 704} 705 706void 707UndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 708{ 709 if (FullSystem) { 710 ArmFault::invoke(tc, inst); 711 return; 712 } 713 714 // If the mnemonic isn't defined this has to be an unknown instruction. 715 assert(unknown || mnemonic != NULL); 716 if (disabled) { 717 panic("Attempted to execute disabled instruction " 718 "'%s' (inst 0x%08x)", mnemonic, machInst); 719 } else if (unknown) { 720 panic("Attempted to execute unknown instruction (inst 0x%08x)", 721 machInst); 722 } else { 723 panic("Attempted to execute unimplemented instruction " 724 "'%s' (inst 0x%08x)", mnemonic, machInst); 725 } 726} 727 728bool 729UndefinedInstruction::routeToHyp(ThreadContext *tc) const 730{ 731 bool toHyp; 732 733 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 734 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 735 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 736 737 // if in Hyp mode then stay in Hyp mode 738 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 739 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 740 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 741 return toHyp; 742} 743 744uint32_t 745UndefinedInstruction::iss() const 746{ 747 if (overrideEc == EC_INVALID) 748 return issRaw; 749 750 uint32_t new_iss = 0; 751 uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 752 753 dir = bits(machInst, 21, 21); 754 op0 = bits(machInst, 20, 19); 755 op1 = bits(machInst, 18, 16); 756 CRn = bits(machInst, 15, 12); 757 CRm = bits(machInst, 11, 8); 758 op2 = bits(machInst, 7, 5); 759 Rt = bits(machInst, 4, 0); 760 761 new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 762 Rt << 5 | CRm << 1 | dir; 763 764 return new_iss; 765} 766 767void 768SupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 769{ 770 if (FullSystem) { 771 ArmFault::invoke(tc, inst); 772 return; 773 } 774 775 // As of now, there isn't a 32 bit thumb version of this instruction. 776 assert(!machInst.bigThumb); 777 uint32_t callNum; 778 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 779 OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 780 if (opModeIs64(mode)) 781 callNum = tc->readIntReg(INTREG_X8); 782 else 783 callNum = tc->readIntReg(INTREG_R7); 784 tc->syscall(callNum); 785 786 // Advance the PC since that won't happen automatically. 787 PCState pc = tc->pcState(); 788 assert(inst); 789 inst->advancePC(pc); 790 tc->pcState(pc); 791} 792 793bool 794SupervisorCall::routeToHyp(ThreadContext *tc) const 795{ 796 bool toHyp; 797 798 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 799 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 800 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 801 802 // if in Hyp mode then stay in Hyp mode 803 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 804 // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 805 toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 806 return toHyp; 807} 808 809ExceptionClass 810SupervisorCall::ec(ThreadContext *tc) const 811{ 812 return (overrideEc != EC_INVALID) ? overrideEc : 813 (from64 ? EC_SVC_64 : vals.ec); 814} 815 816uint32_t 817SupervisorCall::iss() const 818{ 819 // Even if we have a 24 bit imm from an arm32 instruction then we only use 820 // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 821 return issRaw & 0xFFFF; 822} 823 824uint32_t 825SecureMonitorCall::iss() const 826{ 827 if (from64) 828 return bits(machInst, 20, 5); 829 return 0; 830} 831 832ExceptionClass 833UndefinedInstruction::ec(ThreadContext *tc) const 834{ 835 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 836} 837 838 839HypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 840 ArmFaultVals<HypervisorCall>(_machInst, _imm) 841{} 842 843ExceptionClass 844HypervisorCall::ec(ThreadContext *tc) const 845{ 846 return from64 ? EC_HVC_64 : vals.ec; 847} 848 849ExceptionClass 850HypervisorTrap::ec(ThreadContext *tc) const 851{ 852 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 853} 854 855template<class T> 856FaultOffset 857ArmFaultVals<T>::offset(ThreadContext *tc) 858{ 859 bool isHypTrap = false; 860 861 // Normally we just use the exception vector from the table at the top if 862 // this file, however if this exception has caused a transition to hype 863 // mode, and its an exception type that would only do this if it has been 864 // trapped then we use the hyp trap vector instead of the normal vector 865 if (vals.hypTrappable) { 866 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 867 if (cpsr.mode == MODE_HYP) { 868 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 869 isHypTrap = spsr.mode != MODE_HYP; 870 } 871 } 872 return isHypTrap ? 0x14 : vals.offset; 873} 874 875// void 876// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 877// { 878// ESR esr = 0; 879// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 880// esr.il = !machInst.thumb; 881// if (machInst.aarch64) 882// esr.imm16 = bits(machInst.instBits, 20, 5); 883// else if (machInst.thumb) 884// esr.imm16 = bits(machInst.instBits, 7, 0); 885// else 886// esr.imm16 = bits(machInst.instBits, 15, 0); 887// tc->setMiscReg(esr_idx, esr); 888// } 889 890void 891SecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 892{ 893 if (FullSystem) { 894 ArmFault::invoke(tc, inst); 895 return; 896 } 897} 898 899ExceptionClass 900SecureMonitorCall::ec(ThreadContext *tc) const 901{ 902 return (from64 ? EC_SMC_64 : vals.ec); 903} 904 905ExceptionClass 906SupervisorTrap::ec(ThreadContext *tc) const 907{ 908 return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 909} 910 911ExceptionClass 912SecureMonitorTrap::ec(ThreadContext *tc) const 913{ 914 return (overrideEc != EC_INVALID) ? overrideEc : 915 (from64 ? EC_SMC_64 : vals.ec); 916} 917 918template<class T> 919void 920AbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 921{ 922 if (tranMethod == ArmFault::UnknownTran) { 923 tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 924 : ArmFault::VmsaTran; 925 926 if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 927 // See ARM ARM B3-1416 928 bool override_LPAE = false; 929 TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 930 TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 931 if (ttbcr_s.eae) { 932 override_LPAE = true; 933 } else { 934 // Unimplemented code option, not seen in testing. May need 935 // extension according to the manual exceprt above. 936 DPRINTF(Faults, "Warning: Incomplete translation method " 937 "override detected.\n"); 938 } 939 if (override_LPAE) 940 tranMethod = ArmFault::LpaeTran; 941 } 942 } 943 944 if (source == ArmFault::AsynchronousExternalAbort) { 945 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 946 } 947 // Get effective fault source encoding 948 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 949 FSR fsr = getFsr(tc); 950 951 // source must be determined BEFORE invoking generic routines which will 952 // try to set hsr etc. and are based upon source! 953 ArmFaultVals<T>::invoke(tc, inst); 954 955 if (!this->to64) { // AArch32 956 if (cpsr.mode == MODE_HYP) { 957 tc->setMiscReg(T::HFarIndex, faultAddr); 958 } else if (stage2) { 959 tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 960 tc->setMiscReg(T::HFarIndex, OVAddr); 961 } else { 962 tc->setMiscReg(T::FsrIndex, fsr); 963 tc->setMiscReg(T::FarIndex, faultAddr); 964 } 965 DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 966 "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 967 } else { // AArch64 968 // Set the FAR register. Nothing else to do if we are in AArch64 state 969 // because the syndrome register has already been set inside invoke64() 970 tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 971 } 972} 973 974template<class T> 975FSR 976AbortFault<T>::getFsr(ThreadContext *tc) 977{ 978 FSR fsr = 0; 979 980 if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) { 981 // AArch32 982 assert(tranMethod != ArmFault::UnknownTran); 983 if (tranMethod == ArmFault::LpaeTran) { 984 srcEncoded = ArmFault::longDescFaultSources[source]; 985 fsr.status = srcEncoded; 986 fsr.lpae = 1; 987 } else { 988 srcEncoded = ArmFault::shortDescFaultSources[source]; 989 fsr.fsLow = bits(srcEncoded, 3, 0); 990 fsr.fsHigh = bits(srcEncoded, 4); 991 fsr.domain = static_cast<uint8_t>(domain); 992 } 993 fsr.wnr = (write ? 1 : 0); 994 fsr.ext = 0; 995 } else { 996 // AArch64 997 srcEncoded = ArmFault::aarch64FaultSources[source]; 998 } 999 if (srcEncoded == ArmFault::FaultSourceInvalid) { 1000 panic("Invalid fault source\n"); 1001 } 1002 return fsr; 1003} 1004 1005template<class T> 1006bool 1007AbortFault<T>::abortDisable(ThreadContext *tc) 1008{ 1009 if (ArmSystem::haveSecurity(tc)) { 1010 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1011 return (!scr.ns || scr.aw); 1012 } 1013 return true; 1014} 1015 1016template<class T> 1017void 1018AbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 1019{ 1020 switch (id) 1021 { 1022 case ArmFault::S1PTW: 1023 s1ptw = val; 1024 break; 1025 case ArmFault::OVA: 1026 OVAddr = val; 1027 break; 1028 1029 // Just ignore unknown ID's 1030 default: 1031 break; 1032 } 1033} 1034 1035template<class T> 1036uint32_t 1037AbortFault<T>::iss() const 1038{ 1039 uint32_t val; 1040 1041 val = srcEncoded & 0x3F; 1042 val |= write << 6; 1043 val |= s1ptw << 7; 1044 return (val); 1045} 1046 1047template<class T> 1048bool 1049AbortFault<T>::isMMUFault() const 1050{ 1051 // NOTE: Not relying on LL information being aligned to lowest bits here 1052 return 1053 (source == ArmFault::AlignmentFault) || 1054 ((source >= ArmFault::TranslationLL) && 1055 (source < ArmFault::TranslationLL + 4)) || 1056 ((source >= ArmFault::AccessFlagLL) && 1057 (source < ArmFault::AccessFlagLL + 4)) || 1058 ((source >= ArmFault::DomainLL) && 1059 (source < ArmFault::DomainLL + 4)) || 1060 ((source >= ArmFault::PermissionLL) && 1061 (source < ArmFault::PermissionLL + 4)); 1062} 1063 1064ExceptionClass 1065PrefetchAbort::ec(ThreadContext *tc) const 1066{ 1067 if (to64) { 1068 // AArch64 1069 if (toEL == fromEL) 1070 return EC_PREFETCH_ABORT_CURR_EL; 1071 else 1072 return EC_PREFETCH_ABORT_LOWER_EL; 1073 } else { 1074 // AArch32 1075 // Abort faults have different EC codes depending on whether 1076 // the fault originated within HYP mode, or not. So override 1077 // the method and add the extra adjustment of the EC value. 1078 1079 ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 1080 1081 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1082 if (spsr.mode == MODE_HYP) { 1083 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1084 } 1085 return ec; 1086 } 1087} 1088 1089bool 1090PrefetchAbort::routeToMonitor(ThreadContext *tc) const 1091{ 1092 SCR scr = 0; 1093 if (from64) 1094 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1095 else 1096 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1097 1098 return scr.ea && !isMMUFault(); 1099} 1100 1101bool 1102PrefetchAbort::routeToHyp(ThreadContext *tc) const 1103{ 1104 bool toHyp; 1105 1106 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1107 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1108 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1109 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1110 1111 // if in Hyp mode then stay in Hyp mode 1112 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1113 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1114 toHyp |= (stage2 || 1115 ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 1116 ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 1117 ) && !inSecureState(scr, cpsr); 1118 return toHyp; 1119} 1120 1121ExceptionClass 1122DataAbort::ec(ThreadContext *tc) const 1123{ 1124 if (to64) { 1125 // AArch64 1126 if (source == ArmFault::AsynchronousExternalAbort) { 1127 panic("Asynchronous External Abort should be handled with " 1128 "SystemErrors (SErrors)!"); 1129 } 1130 if (toEL == fromEL) 1131 return EC_DATA_ABORT_CURR_EL; 1132 else 1133 return EC_DATA_ABORT_LOWER_EL; 1134 } else { 1135 // AArch32 1136 // Abort faults have different EC codes depending on whether 1137 // the fault originated within HYP mode, or not. So override 1138 // the method and add the extra adjustment of the EC value. 1139 1140 ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 1141 1142 CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 1143 if (spsr.mode == MODE_HYP) { 1144 ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 1145 } 1146 return ec; 1147 } 1148} 1149 1150bool 1151DataAbort::routeToMonitor(ThreadContext *tc) const 1152{ 1153 SCR scr = 0; 1154 if (from64) 1155 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1156 else 1157 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1158 1159 return scr.ea && !isMMUFault(); 1160} 1161 1162bool 1163DataAbort::routeToHyp(ThreadContext *tc) const 1164{ 1165 bool toHyp; 1166 1167 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1168 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1169 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1170 HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 1171 1172 // if in Hyp mode then stay in Hyp mode 1173 toHyp = scr.ns && (cpsr.mode == MODE_HYP); 1174 // otherwise, check whether to take to Hyp mode through Hyp Trap vector 1175 toHyp |= (stage2 || 1176 ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 1177 ((source == DebugEvent) && hdcr.tde) ) 1178 ) || 1179 ( (cpsr.mode == MODE_USER) && hcr.tge && 1180 ((source == AlignmentFault) || 1181 (source == SynchronousExternalAbort)) 1182 ) 1183 ) && !inSecureState(scr, cpsr); 1184 return toHyp; 1185} 1186 1187uint32_t 1188DataAbort::iss() const 1189{ 1190 uint32_t val; 1191 1192 // Add on the data abort specific fields to the generic abort ISS value 1193 val = AbortFault<DataAbort>::iss(); 1194 // ISS is valid if not caused by a stage 1 page table walk, and when taken 1195 // to AArch64 only when directed to EL2 1196 if (!s1ptw && (!to64 || toEL == EL2)) { 1197 val |= isv << 24; 1198 if (isv) { 1199 val |= sas << 22; 1200 val |= sse << 21; 1201 val |= srt << 16; 1202 // AArch64 only. These assignments are safe on AArch32 as well 1203 // because these vars are initialized to false 1204 val |= sf << 15; 1205 val |= ar << 14; 1206 } 1207 } 1208 return (val); 1209} 1210 1211void 1212DataAbort::annotate(AnnotationIDs id, uint64_t val) 1213{ 1214 AbortFault<DataAbort>::annotate(id, val); 1215 switch (id) 1216 { 1217 case SAS: 1218 isv = true; 1219 sas = val; 1220 break; 1221 case SSE: 1222 isv = true; 1223 sse = val; 1224 break; 1225 case SRT: 1226 isv = true; 1227 srt = val; 1228 break; 1229 case SF: 1230 isv = true; 1231 sf = val; 1232 break; 1233 case AR: 1234 isv = true; 1235 ar = val; 1236 break; 1237 // Just ignore unknown ID's 1238 default: 1239 break; 1240 } 1241} 1242 1243void 1244VirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1245{ 1246 AbortFault<VirtualDataAbort>::invoke(tc, inst); 1247 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1248 hcr.va = 0; 1249 tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 1250} 1251 1252bool 1253Interrupt::routeToMonitor(ThreadContext *tc) const 1254{ 1255 assert(ArmSystem::haveSecurity(tc)); 1256 SCR scr = 0; 1257 if (from64) 1258 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1259 else 1260 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1261 return scr.irq; 1262} 1263 1264bool 1265Interrupt::routeToHyp(ThreadContext *tc) const 1266{ 1267 bool toHyp; 1268 1269 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1270 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1271 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1272 // Determine whether IRQs are routed to Hyp mode. 1273 toHyp = (!scr.irq && hcr.imo && !inSecureState(scr, cpsr)) || 1274 (cpsr.mode == MODE_HYP); 1275 return toHyp; 1276} 1277 1278bool 1279Interrupt::abortDisable(ThreadContext *tc) 1280{ 1281 if (ArmSystem::haveSecurity(tc)) { 1282 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1283 return (!scr.ns || scr.aw); 1284 } 1285 return true; 1286} 1287 1288VirtualInterrupt::VirtualInterrupt() 1289{} 1290 1291bool 1292FastInterrupt::routeToMonitor(ThreadContext *tc) const 1293{ 1294 assert(ArmSystem::haveSecurity(tc)); 1295 SCR scr = 0; 1296 if (from64) 1297 scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1298 else 1299 scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1300 return scr.fiq; 1301} 1302 1303bool 1304FastInterrupt::routeToHyp(ThreadContext *tc) const 1305{ 1306 bool toHyp; 1307 1308 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1309 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1310 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1311 // Determine whether IRQs are routed to Hyp mode. 1312 toHyp = (!scr.fiq && hcr.fmo && !inSecureState(scr, cpsr)) || 1313 (cpsr.mode == MODE_HYP); 1314 return toHyp; 1315} 1316 1317bool 1318FastInterrupt::abortDisable(ThreadContext *tc) 1319{ 1320 if (ArmSystem::haveSecurity(tc)) { 1321 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1322 return (!scr.ns || scr.aw); 1323 } 1324 return true; 1325} 1326 1327bool 1328FastInterrupt::fiqDisable(ThreadContext *tc) 1329{ 1330 if (ArmSystem::haveVirtualization(tc)) { 1331 return true; 1332 } else if (ArmSystem::haveSecurity(tc)) { 1333 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 1334 return (!scr.ns || scr.fw); 1335 } 1336 return true; 1337} 1338 1339VirtualFastInterrupt::VirtualFastInterrupt() 1340{} 1341 1342void 1343PCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1344{ 1345 ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 1346 assert(from64); 1347 // Set the FAR 1348 tc->setMiscReg(getFaultAddrReg64(), faultPC); 1349} 1350 1351SPAlignmentFault::SPAlignmentFault() 1352{} 1353 1354SystemError::SystemError() 1355{} 1356 1357void 1358SystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 1359{ 1360 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 1361 ArmFault::invoke(tc, inst); 1362} 1363 1364bool 1365SystemError::routeToMonitor(ThreadContext *tc) const 1366{ 1367 assert(ArmSystem::haveSecurity(tc)); 1368 assert(from64); 1369 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1370 return scr.ea; 1371} 1372 1373bool 1374SystemError::routeToHyp(ThreadContext *tc) const 1375{ 1376 bool toHyp; 1377 assert(from64); 1378 1379 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 1380 HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 1381 CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 1382 1383 toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) || 1384 (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr)); 1385 return toHyp; 1386} 1387 1388void 1389FlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1390 DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 1391 1392 // Set the PC to the next instruction of the faulting instruction. 1393 // Net effect is simply squashing all instructions behind and 1394 // start refetching from the next instruction. 1395 PCState pc = tc->pcState(); 1396 assert(inst); 1397 inst->advancePC(pc); 1398 tc->pcState(pc); 1399} 1400 1401void 1402ArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 1403 DPRINTF(Faults, "Invoking ArmSev Fault\n"); 1404 if (!FullSystem) 1405 return; 1406 1407 // Set sev_mailbox to 1, clear the pending interrupt from remote 1408 // SEV execution and let pipeline continue as pcState is still 1409 // valid. 1410 tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 1411 tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 1412} 1413 1414// Instantiate all the templates to make the linker happy 1415template class ArmFaultVals<Reset>; 1416template class ArmFaultVals<UndefinedInstruction>; 1417template class ArmFaultVals<SupervisorCall>; 1418template class ArmFaultVals<SecureMonitorCall>; 1419template class ArmFaultVals<HypervisorCall>; 1420template class ArmFaultVals<PrefetchAbort>; 1421template class ArmFaultVals<DataAbort>; 1422template class ArmFaultVals<VirtualDataAbort>; 1423template class ArmFaultVals<HypervisorTrap>; 1424template class ArmFaultVals<Interrupt>; 1425template class ArmFaultVals<VirtualInterrupt>; 1426template class ArmFaultVals<FastInterrupt>; 1427template class ArmFaultVals<VirtualFastInterrupt>; 1428template class ArmFaultVals<SupervisorTrap>; 1429template class ArmFaultVals<SecureMonitorTrap>; 1430template class ArmFaultVals<PCAlignmentFault>; 1431template class ArmFaultVals<SPAlignmentFault>; 1432template class ArmFaultVals<SystemError>; 1433template class ArmFaultVals<FlushPipe>; 1434template class ArmFaultVals<ArmSev>; 1435template class AbortFault<PrefetchAbort>; 1436template class AbortFault<DataAbort>; 1437template class AbortFault<VirtualDataAbort>; 1438 1439 1440IllegalInstSetStateFault::IllegalInstSetStateFault() 1441{} 1442 1443 1444} // namespace ArmISA 1445