faults.cc revision 11574
16019Shines@cs.fsu.edu/* 211496Sandreas.sandberg@arm.com * Copyright (c) 2010, 2012-2014, 2016 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146019Shines@cs.fsu.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 156019Shines@cs.fsu.edu * Copyright (c) 2007-2008 The Florida State University 166019Shines@cs.fsu.edu * All rights reserved. 176019Shines@cs.fsu.edu * 186019Shines@cs.fsu.edu * Redistribution and use in source and binary forms, with or without 196019Shines@cs.fsu.edu * modification, are permitted provided that the following conditions are 206019Shines@cs.fsu.edu * met: redistributions of source code must retain the above copyright 216019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer; 226019Shines@cs.fsu.edu * redistributions in binary form must reproduce the above copyright 236019Shines@cs.fsu.edu * notice, this list of conditions and the following disclaimer in the 246019Shines@cs.fsu.edu * documentation and/or other materials provided with the distribution; 256019Shines@cs.fsu.edu * neither the name of the copyright holders nor the names of its 266019Shines@cs.fsu.edu * contributors may be used to endorse or promote products derived from 276019Shines@cs.fsu.edu * this software without specific prior written permission. 286019Shines@cs.fsu.edu * 296019Shines@cs.fsu.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306019Shines@cs.fsu.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316019Shines@cs.fsu.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326019Shines@cs.fsu.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336019Shines@cs.fsu.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346019Shines@cs.fsu.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356019Shines@cs.fsu.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366019Shines@cs.fsu.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376019Shines@cs.fsu.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386019Shines@cs.fsu.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396019Shines@cs.fsu.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406019Shines@cs.fsu.edu * 416735Sgblack@eecs.umich.edu * Authors: Ali Saidi 426735Sgblack@eecs.umich.edu * Gabe Black 4310037SARM gem5 Developers * Giacomo Gabrielli 4410037SARM gem5 Developers * Thomas Grocutt 456019Shines@cs.fsu.edu */ 466019Shines@cs.fsu.edu 476019Shines@cs.fsu.edu#include "arch/arm/faults.hh" 4810037SARM gem5 Developers#include "arch/arm/system.hh" 4910037SARM gem5 Developers#include "arch/arm/utility.hh" 5010037SARM gem5 Developers#include "arch/arm/insts/static_inst.hh" 5110037SARM gem5 Developers#include "base/compiler.hh" 528229Snate@binkert.org#include "base/trace.hh" 538229Snate@binkert.org#include "cpu/base.hh" 546019Shines@cs.fsu.edu#include "cpu/thread_context.hh" 558232Snate@binkert.org#include "debug/Faults.hh" 568782Sgblack@eecs.umich.edu#include "sim/full_system.hh" 576019Shines@cs.fsu.edu 586019Shines@cs.fsu.edunamespace ArmISA 596019Shines@cs.fsu.edu{ 606019Shines@cs.fsu.edu 6110037SARM gem5 Developersuint8_t ArmFault::shortDescFaultSources[] = { 6210037SARM gem5 Developers 0x01, // AlignmentFault 6310037SARM gem5 Developers 0x04, // InstructionCacheMaintenance 6410037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 6510037SARM gem5 Developers 0x0c, // SynchExtAbtOnTranslTableWalkL1 6610037SARM gem5 Developers 0x0e, // SynchExtAbtOnTranslTableWalkL2 6710037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL3 (INVALID) 6810037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 6910037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL1 7010037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 7110037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL3 (INVALID) 7210037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 7310037SARM gem5 Developers 0x05, // TranslationL1 7410037SARM gem5 Developers 0x07, // TranslationL2 7510037SARM gem5 Developers 0xff, // TranslationL3 (INVALID) 7610037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 7710037SARM gem5 Developers 0x03, // AccessFlagL1 7810037SARM gem5 Developers 0x06, // AccessFlagL2 7910037SARM gem5 Developers 0xff, // AccessFlagL3 (INVALID) 8010037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 8110037SARM gem5 Developers 0x09, // DomainL1 8210037SARM gem5 Developers 0x0b, // DomainL2 8310037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 8410037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 8510037SARM gem5 Developers 0x0d, // PermissionL1 8610037SARM gem5 Developers 0x0f, // PermissionL2 8710037SARM gem5 Developers 0xff, // PermissionL3 (INVALID) 8810037SARM gem5 Developers 0x02, // DebugEvent 8910037SARM gem5 Developers 0x08, // SynchronousExternalAbort 9010037SARM gem5 Developers 0x10, // TLBConflictAbort 9110037SARM gem5 Developers 0x19, // SynchPtyErrOnMemoryAccess 9210037SARM gem5 Developers 0x16, // AsynchronousExternalAbort 9310037SARM gem5 Developers 0x18, // AsynchPtyErrOnMemoryAccess 9410037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 9510037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 9610037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 9710037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 9810037SARM gem5 Developers 0x40, // PrefetchTLBMiss 9910037SARM gem5 Developers 0x80 // PrefetchUncacheable 10010037SARM gem5 Developers}; 1016019Shines@cs.fsu.edu 10210037SARM gem5 Developersstatic_assert(sizeof(ArmFault::shortDescFaultSources) == 10310037SARM gem5 Developers ArmFault::NumFaultSources, 10410037SARM gem5 Developers "Invalid size of ArmFault::shortDescFaultSources[]"); 1056019Shines@cs.fsu.edu 10610037SARM gem5 Developersuint8_t ArmFault::longDescFaultSources[] = { 10710037SARM gem5 Developers 0x21, // AlignmentFault 10810037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 10910037SARM gem5 Developers 0xff, // SynchExtAbtOnTranslTableWalkL0 (INVALID) 11010037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 11110037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 11210037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 11310037SARM gem5 Developers 0xff, // SynchPtyErrOnTranslTableWalkL0 (INVALID) 11410037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 11510037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 11610037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 11710037SARM gem5 Developers 0xff, // TranslationL0 (INVALID) 11810037SARM gem5 Developers 0x05, // TranslationL1 11910037SARM gem5 Developers 0x06, // TranslationL2 12010037SARM gem5 Developers 0x07, // TranslationL3 12110037SARM gem5 Developers 0xff, // AccessFlagL0 (INVALID) 12210037SARM gem5 Developers 0x09, // AccessFlagL1 12310037SARM gem5 Developers 0x0a, // AccessFlagL2 12410037SARM gem5 Developers 0x0b, // AccessFlagL3 12510037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 12610037SARM gem5 Developers 0x3d, // DomainL1 12710037SARM gem5 Developers 0x3e, // DomainL2 12810037SARM gem5 Developers 0xff, // DomainL3 (RESERVED) 12910037SARM gem5 Developers 0xff, // PermissionL0 (INVALID) 13010037SARM gem5 Developers 0x0d, // PermissionL1 13110037SARM gem5 Developers 0x0e, // PermissionL2 13210037SARM gem5 Developers 0x0f, // PermissionL3 13310037SARM gem5 Developers 0x22, // DebugEvent 13410037SARM gem5 Developers 0x10, // SynchronousExternalAbort 13510037SARM gem5 Developers 0x30, // TLBConflictAbort 13610037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 13710037SARM gem5 Developers 0x11, // AsynchronousExternalAbort 13810037SARM gem5 Developers 0x19, // AsynchPtyErrOnMemoryAccess 13910037SARM gem5 Developers 0xff, // AddressSizeL0 (INVALID) 14010037SARM gem5 Developers 0xff, // AddressSizeL1 (INVALID) 14110037SARM gem5 Developers 0xff, // AddressSizeL2 (INVALID) 14210037SARM gem5 Developers 0xff, // AddressSizeL3 (INVALID) 14310037SARM gem5 Developers 0x40, // PrefetchTLBMiss 14410037SARM gem5 Developers 0x80 // PrefetchUncacheable 14510037SARM gem5 Developers}; 1466019Shines@cs.fsu.edu 14710037SARM gem5 Developersstatic_assert(sizeof(ArmFault::longDescFaultSources) == 14810037SARM gem5 Developers ArmFault::NumFaultSources, 14910037SARM gem5 Developers "Invalid size of ArmFault::longDescFaultSources[]"); 1506019Shines@cs.fsu.edu 15110037SARM gem5 Developersuint8_t ArmFault::aarch64FaultSources[] = { 15210037SARM gem5 Developers 0x21, // AlignmentFault 15310037SARM gem5 Developers 0xff, // InstructionCacheMaintenance (INVALID) 15410037SARM gem5 Developers 0x14, // SynchExtAbtOnTranslTableWalkL0 15510037SARM gem5 Developers 0x15, // SynchExtAbtOnTranslTableWalkL1 15610037SARM gem5 Developers 0x16, // SynchExtAbtOnTranslTableWalkL2 15710037SARM gem5 Developers 0x17, // SynchExtAbtOnTranslTableWalkL3 15810037SARM gem5 Developers 0x1c, // SynchPtyErrOnTranslTableWalkL0 15910037SARM gem5 Developers 0x1d, // SynchPtyErrOnTranslTableWalkL1 16010037SARM gem5 Developers 0x1e, // SynchPtyErrOnTranslTableWalkL2 16110037SARM gem5 Developers 0x1f, // SynchPtyErrOnTranslTableWalkL3 16210037SARM gem5 Developers 0x04, // TranslationL0 16310037SARM gem5 Developers 0x05, // TranslationL1 16410037SARM gem5 Developers 0x06, // TranslationL2 16510037SARM gem5 Developers 0x07, // TranslationL3 16610037SARM gem5 Developers 0x08, // AccessFlagL0 16710037SARM gem5 Developers 0x09, // AccessFlagL1 16810037SARM gem5 Developers 0x0a, // AccessFlagL2 16910037SARM gem5 Developers 0x0b, // AccessFlagL3 17010037SARM gem5 Developers // @todo: Section & Page Domain Fault in AArch64? 17110037SARM gem5 Developers 0xff, // DomainL0 (INVALID) 17210037SARM gem5 Developers 0xff, // DomainL1 (INVALID) 17310037SARM gem5 Developers 0xff, // DomainL2 (INVALID) 17410037SARM gem5 Developers 0xff, // DomainL3 (INVALID) 17510037SARM gem5 Developers 0x0c, // PermissionL0 17610037SARM gem5 Developers 0x0d, // PermissionL1 17710037SARM gem5 Developers 0x0e, // PermissionL2 17810037SARM gem5 Developers 0x0f, // PermissionL3 17910037SARM gem5 Developers 0xff, // DebugEvent (INVALID) 18010037SARM gem5 Developers 0x10, // SynchronousExternalAbort 18110037SARM gem5 Developers 0x30, // TLBConflictAbort 18210037SARM gem5 Developers 0x18, // SynchPtyErrOnMemoryAccess 18310037SARM gem5 Developers 0xff, // AsynchronousExternalAbort (INVALID) 18410037SARM gem5 Developers 0xff, // AsynchPtyErrOnMemoryAccess (INVALID) 18510037SARM gem5 Developers 0x00, // AddressSizeL0 18610037SARM gem5 Developers 0x01, // AddressSizeL1 18710037SARM gem5 Developers 0x02, // AddressSizeL2 18810037SARM gem5 Developers 0x03, // AddressSizeL3 18910037SARM gem5 Developers 0x40, // PrefetchTLBMiss 19010037SARM gem5 Developers 0x80 // PrefetchUncacheable 19110037SARM gem5 Developers}; 1926019Shines@cs.fsu.edu 19310037SARM gem5 Developersstatic_assert(sizeof(ArmFault::aarch64FaultSources) == 19410037SARM gem5 Developers ArmFault::NumFaultSources, 19510037SARM gem5 Developers "Invalid size of ArmFault::aarch64FaultSources[]"); 1966019Shines@cs.fsu.edu 19710037SARM gem5 Developers// Fields: name, offset, cur{ELT,ELH}Offset, lowerEL{64,32}Offset, next mode, 19810037SARM gem5 Developers// {ARM, Thumb, ARM_ELR, Thumb_ELR} PC offset, hyp trap, 19910037SARM gem5 Developers// {A, F} disable, class, stat 20010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<Reset>::vals = { 20110037SARM gem5 Developers // Some dummy values (the reset vector has an IMPLEMENTATION DEFINED 20210037SARM gem5 Developers // location in AArch64) 20310037SARM gem5 Developers "Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 20410037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 20510037SARM gem5 Developers}; 20610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals = { 20710037SARM gem5 Developers "Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED, 20810037SARM gem5 Developers 4, 2, 0, 0, true, false, false, EC_UNKNOWN, FaultStat() 20910037SARM gem5 Developers}; 21010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals = { 21110037SARM gem5 Developers "Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 21210037SARM gem5 Developers 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP, FaultStat() 21310037SARM gem5 Developers}; 21410037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals = { 21510037SARM gem5 Developers "Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON, 21610037SARM gem5 Developers 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP, FaultStat() 21710037SARM gem5 Developers}; 21810037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals = { 21910037SARM gem5 Developers "Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 22010037SARM gem5 Developers 4, 4, 4, 4, true, false, false, EC_HVC, FaultStat() 22110037SARM gem5 Developers}; 22210037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals = { 22310037SARM gem5 Developers "Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22410037SARM gem5 Developers 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP, FaultStat() 22510037SARM gem5 Developers}; 22610037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals = { 22710037SARM gem5 Developers "Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 22810037SARM gem5 Developers 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP, FaultStat() 22910037SARM gem5 Developers}; 23010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals = { 23110037SARM gem5 Developers "Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT, 23210037SARM gem5 Developers 8, 8, 0, 0, true, true, false, EC_INVALID, FaultStat() 23310037SARM gem5 Developers}; 23410037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals = { 23510037SARM gem5 Developers // @todo: double check these values 23610037SARM gem5 Developers "Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP, 23710037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 23810037SARM gem5 Developers}; 23910037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals = { 24010037SARM gem5 Developers "IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24110037SARM gem5 Developers 4, 4, 0, 0, false, true, false, EC_UNKNOWN, FaultStat() 24210037SARM gem5 Developers}; 24310037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals = { 24410037SARM gem5 Developers "Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ, 24510037SARM gem5 Developers 4, 4, 0, 0, false, true, false, EC_INVALID, FaultStat() 24610037SARM gem5 Developers}; 24710037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals = { 24810037SARM gem5 Developers "FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 24910037SARM gem5 Developers 4, 4, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 25010037SARM gem5 Developers}; 25110037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals = { 25210037SARM gem5 Developers "Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ, 25310037SARM gem5 Developers 4, 4, 0, 0, false, true, true, EC_INVALID, FaultStat() 25410037SARM gem5 Developers}; 25510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals = { 25610037SARM gem5 Developers // Some dummy values (SupervisorTrap is AArch64-only) 25710037SARM gem5 Developers "Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 25810037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 25910037SARM gem5 Developers}; 26010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals = { 26110037SARM gem5 Developers // Some dummy values (SecureMonitorTrap is AArch64-only) 26210037SARM gem5 Developers "Secure Monitor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_MON, 26310037SARM gem5 Developers 0, 0, 0, 0, false, false, false, EC_UNKNOWN, FaultStat() 26410037SARM gem5 Developers}; 26510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals = { 26610037SARM gem5 Developers // Some dummy values (PCAlignmentFault is AArch64-only) 26710037SARM gem5 Developers "PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 26810037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT, FaultStat() 26910037SARM gem5 Developers}; 27010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals = { 27110037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 27210037SARM gem5 Developers "SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 27310037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT, FaultStat() 27410037SARM gem5 Developers}; 27510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals = { 27610037SARM gem5 Developers // Some dummy values (SError is AArch64-only) 27710037SARM gem5 Developers "SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC, 27810037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_SERROR, FaultStat() 27910037SARM gem5 Developers}; 28010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<FlushPipe>::vals = { 28110037SARM gem5 Developers // Some dummy values 28210037SARM gem5 Developers "Pipe Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 28310037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 28410037SARM gem5 Developers}; 28510037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals = { 28610037SARM gem5 Developers // Some dummy values 28710037SARM gem5 Developers "ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC, 28810037SARM gem5 Developers 0, 0, 0, 0, false, true, true, EC_UNKNOWN, FaultStat() 28910037SARM gem5 Developers}; 29010037SARM gem5 Developerstemplate<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals = { 29110037SARM gem5 Developers // Some dummy values (SPAlignmentFault is AArch64-only) 29210037SARM gem5 Developers "Illegal Inst Set State Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC, 29310037SARM gem5 Developers 0, 0, 0, 0, true, false, false, EC_ILLEGAL_INST, FaultStat() 29410037SARM gem5 Developers}; 2956019Shines@cs.fsu.edu 29610037SARM gem5 DevelopersAddr 2977362Sgblack@eecs.umich.eduArmFault::getVector(ThreadContext *tc) 2986735Sgblack@eecs.umich.edu{ 29910037SARM gem5 Developers Addr base; 3006019Shines@cs.fsu.edu 30110037SARM gem5 Developers // ARM ARM issue C B1.8.1 30210037SARM gem5 Developers bool haveSecurity = ArmSystem::haveSecurity(tc); 3037400SAli.Saidi@ARM.com 3046735Sgblack@eecs.umich.edu // panic if SCTLR.VE because I have no idea what to do with vectored 3056735Sgblack@eecs.umich.edu // interrupts 30610037SARM gem5 Developers SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 3076735Sgblack@eecs.umich.edu assert(!sctlr.ve); 30810037SARM gem5 Developers // Check for invalid modes 30910037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 31010037SARM gem5 Developers assert(haveSecurity || cpsr.mode != MODE_MON); 31110037SARM gem5 Developers assert(ArmSystem::haveVirtualization(tc) || cpsr.mode != MODE_HYP); 3127400SAli.Saidi@ARM.com 31310037SARM gem5 Developers switch (cpsr.mode) 31410037SARM gem5 Developers { 31510037SARM gem5 Developers case MODE_MON: 31610037SARM gem5 Developers base = tc->readMiscReg(MISCREG_MVBAR); 31710037SARM gem5 Developers break; 31810037SARM gem5 Developers case MODE_HYP: 31910037SARM gem5 Developers base = tc->readMiscReg(MISCREG_HVBAR); 32010037SARM gem5 Developers break; 32110037SARM gem5 Developers default: 32210037SARM gem5 Developers if (sctlr.v) { 32310037SARM gem5 Developers base = HighVecs; 32410037SARM gem5 Developers } else { 32510037SARM gem5 Developers base = haveSecurity ? tc->readMiscReg(MISCREG_VBAR) : 0; 32610037SARM gem5 Developers } 32710037SARM gem5 Developers break; 32810037SARM gem5 Developers } 32910037SARM gem5 Developers return base + offset(tc); 3306019Shines@cs.fsu.edu} 3316019Shines@cs.fsu.edu 33210037SARM gem5 DevelopersAddr 33310037SARM gem5 DevelopersArmFault::getVector64(ThreadContext *tc) 33410037SARM gem5 Developers{ 33510037SARM gem5 Developers Addr vbar; 33610037SARM gem5 Developers switch (toEL) { 33710037SARM gem5 Developers case EL3: 33810037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 33910037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL3); 34010037SARM gem5 Developers break; 34111574SCurtis.Dunham@arm.com case EL2: 34211574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 34311574SCurtis.Dunham@arm.com vbar = tc->readMiscReg(MISCREG_VBAR_EL2); 34411574SCurtis.Dunham@arm.com break; 34510037SARM gem5 Developers case EL1: 34610037SARM gem5 Developers vbar = tc->readMiscReg(MISCREG_VBAR_EL1); 34710037SARM gem5 Developers break; 34810037SARM gem5 Developers default: 34910037SARM gem5 Developers panic("Invalid target exception level"); 35010037SARM gem5 Developers break; 35110037SARM gem5 Developers } 35210037SARM gem5 Developers return vbar + offset64(); 35310037SARM gem5 Developers} 35410037SARM gem5 Developers 35510037SARM gem5 DevelopersMiscRegIndex 35610037SARM gem5 DevelopersArmFault::getSyndromeReg64() const 35710037SARM gem5 Developers{ 35810037SARM gem5 Developers switch (toEL) { 35910037SARM gem5 Developers case EL1: 36010037SARM gem5 Developers return MISCREG_ESR_EL1; 36110037SARM gem5 Developers case EL2: 36210037SARM gem5 Developers return MISCREG_ESR_EL2; 36310037SARM gem5 Developers case EL3: 36410037SARM gem5 Developers return MISCREG_ESR_EL3; 36510037SARM gem5 Developers default: 36610037SARM gem5 Developers panic("Invalid exception level"); 36710037SARM gem5 Developers break; 36810037SARM gem5 Developers } 36910037SARM gem5 Developers} 37010037SARM gem5 Developers 37110037SARM gem5 DevelopersMiscRegIndex 37210037SARM gem5 DevelopersArmFault::getFaultAddrReg64() const 37310037SARM gem5 Developers{ 37410037SARM gem5 Developers switch (toEL) { 37510037SARM gem5 Developers case EL1: 37610037SARM gem5 Developers return MISCREG_FAR_EL1; 37710037SARM gem5 Developers case EL2: 37810037SARM gem5 Developers return MISCREG_FAR_EL2; 37910037SARM gem5 Developers case EL3: 38010037SARM gem5 Developers return MISCREG_FAR_EL3; 38110037SARM gem5 Developers default: 38210037SARM gem5 Developers panic("Invalid exception level"); 38310037SARM gem5 Developers break; 38410037SARM gem5 Developers } 38510037SARM gem5 Developers} 38610037SARM gem5 Developers 38710037SARM gem5 Developersvoid 38810037SARM gem5 DevelopersArmFault::setSyndrome(ThreadContext *tc, MiscRegIndex syndrome_reg) 38910037SARM gem5 Developers{ 39010037SARM gem5 Developers uint32_t value; 39110037SARM gem5 Developers uint32_t exc_class = (uint32_t) ec(tc); 39210037SARM gem5 Developers uint32_t issVal = iss(); 39310037SARM gem5 Developers assert(!from64 || ArmSystem::highestELIs64(tc)); 39410037SARM gem5 Developers 39510037SARM gem5 Developers value = exc_class << 26; 39610037SARM gem5 Developers 39710037SARM gem5 Developers // HSR.IL not valid for Prefetch Aborts (0x20, 0x21) and Data Aborts (0x24, 39810037SARM gem5 Developers // 0x25) for which the ISS information is not valid (ARMv7). 39910037SARM gem5 Developers // @todo: ARMv8 revises AArch32 functionality: when HSR.IL is not 40010037SARM gem5 Developers // valid it is treated as RES1. 40110037SARM gem5 Developers if (to64) { 40210037SARM gem5 Developers value |= 1 << 25; 40310037SARM gem5 Developers } else if ((bits(exc_class, 5, 3) != 4) || 40410037SARM gem5 Developers (bits(exc_class, 2) && bits(issVal, 24))) { 40510037SARM gem5 Developers if (!machInst.thumb || machInst.bigThumb) 40610037SARM gem5 Developers value |= 1 << 25; 40710037SARM gem5 Developers } 40810037SARM gem5 Developers // Condition code valid for EC[5:4] nonzero 40910037SARM gem5 Developers if (!from64 && ((bits(exc_class, 5, 4) == 0) && 41010037SARM gem5 Developers (bits(exc_class, 3, 0) != 0))) { 41110037SARM gem5 Developers if (!machInst.thumb) { 41210037SARM gem5 Developers uint32_t cond; 41310037SARM gem5 Developers ConditionCode condCode = (ConditionCode) (uint32_t) machInst.condCode; 41410037SARM gem5 Developers // If its on unconditional instruction report with a cond code of 41510037SARM gem5 Developers // 0xE, ie the unconditional code 41610037SARM gem5 Developers cond = (condCode == COND_UC) ? COND_AL : condCode; 41710037SARM gem5 Developers value |= cond << 20; 41810037SARM gem5 Developers value |= 1 << 24; 41910037SARM gem5 Developers } 42010037SARM gem5 Developers value |= bits(issVal, 19, 0); 42110037SARM gem5 Developers } else { 42210037SARM gem5 Developers value |= issVal; 42310037SARM gem5 Developers } 42410037SARM gem5 Developers tc->setMiscReg(syndrome_reg, value); 42510037SARM gem5 Developers} 42610037SARM gem5 Developers 42710037SARM gem5 Developersvoid 42810417Sandreas.hansson@arm.comArmFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 4296019Shines@cs.fsu.edu{ 43010037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 43110037SARM gem5 Developers 43210037SARM gem5 Developers if (ArmSystem::highestELIs64(tc)) { // ARMv8 43310037SARM gem5 Developers // Determine source exception level and mode 43410037SARM gem5 Developers fromMode = (OperatingMode) (uint8_t) cpsr.mode; 43510037SARM gem5 Developers fromEL = opModeToEL(fromMode); 43610037SARM gem5 Developers if (opModeIs64(fromMode)) 43710037SARM gem5 Developers from64 = true; 43810037SARM gem5 Developers 43910037SARM gem5 Developers // Determine target exception level 44010037SARM gem5 Developers if (ArmSystem::haveSecurity(tc) && routeToMonitor(tc)) 44110037SARM gem5 Developers toEL = EL3; 44210037SARM gem5 Developers else 44310037SARM gem5 Developers toEL = opModeToEL(nextMode()); 44410037SARM gem5 Developers if (fromEL > toEL) 44510037SARM gem5 Developers toEL = fromEL; 44610037SARM gem5 Developers 44710037SARM gem5 Developers if (toEL == ArmSystem::highestEL(tc) || ELIs64(tc, toEL)) { 44810037SARM gem5 Developers // Invoke exception handler in AArch64 state 44910037SARM gem5 Developers to64 = true; 45010037SARM gem5 Developers invoke64(tc, inst); 45110037SARM gem5 Developers return; 45210037SARM gem5 Developers } 45310037SARM gem5 Developers } 45410037SARM gem5 Developers 45510037SARM gem5 Developers // ARMv7 (ARM ARM issue C B1.9) 45610037SARM gem5 Developers 45710037SARM gem5 Developers bool have_security = ArmSystem::haveSecurity(tc); 45810037SARM gem5 Developers bool have_virtualization = ArmSystem::haveVirtualization(tc); 45910037SARM gem5 Developers 4606735Sgblack@eecs.umich.edu FaultBase::invoke(tc); 4618782Sgblack@eecs.umich.edu if (!FullSystem) 4628782Sgblack@eecs.umich.edu return; 4636735Sgblack@eecs.umich.edu countStat()++; 4646019Shines@cs.fsu.edu 4656735Sgblack@eecs.umich.edu SCTLR sctlr = tc->readMiscReg(MISCREG_SCTLR); 46610037SARM gem5 Developers SCR scr = tc->readMiscReg(MISCREG_SCR); 4678303SAli.Saidi@ARM.com CPSR saved_cpsr = tc->readMiscReg(MISCREG_CPSR); 46810338SCurtis.Dunham@arm.com saved_cpsr.nz = tc->readCCReg(CCREG_NZ); 46910338SCurtis.Dunham@arm.com saved_cpsr.c = tc->readCCReg(CCREG_C); 47010338SCurtis.Dunham@arm.com saved_cpsr.v = tc->readCCReg(CCREG_V); 47110338SCurtis.Dunham@arm.com saved_cpsr.ge = tc->readCCReg(CCREG_GE); 4728303SAli.Saidi@ARM.com 4737720Sgblack@eecs.umich.edu Addr curPc M5_VAR_USED = tc->pcState().pc(); 4748205SAli.Saidi@ARM.com ITSTATE it = tc->pcState().itstate(); 4758205SAli.Saidi@ARM.com saved_cpsr.it2 = it.top6; 4768205SAli.Saidi@ARM.com saved_cpsr.it1 = it.bottom2; 4776735Sgblack@eecs.umich.edu 47810037SARM gem5 Developers // if we have a valid instruction then use it to annotate this fault with 47910037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 48010037SARM gem5 Developers // information 48110037SARM gem5 Developers if (inst) { 48210037SARM gem5 Developers ArmStaticInst *armInst = reinterpret_cast<ArmStaticInst *>(inst.get()); 48310037SARM gem5 Developers armInst->annotateFault(this); 48410037SARM gem5 Developers } 48510037SARM gem5 Developers 48610037SARM gem5 Developers if (have_security && routeToMonitor(tc)) 48710037SARM gem5 Developers cpsr.mode = MODE_MON; 48810037SARM gem5 Developers else if (have_virtualization && routeToHyp(tc)) 48910037SARM gem5 Developers cpsr.mode = MODE_HYP; 49010037SARM gem5 Developers else 49110037SARM gem5 Developers cpsr.mode = nextMode(); 49210037SARM gem5 Developers 49310037SARM gem5 Developers // Ensure Secure state if initially in Monitor mode 49410037SARM gem5 Developers if (have_security && saved_cpsr.mode == MODE_MON) { 49510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 49610037SARM gem5 Developers if (scr.ns) { 49710037SARM gem5 Developers scr.ns = 0; 49810037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_SCR, scr); 49910037SARM gem5 Developers } 50010037SARM gem5 Developers } 50110037SARM gem5 Developers 50210037SARM gem5 Developers // some bits are set differently if we have been routed to hyp mode 50310037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 50410037SARM gem5 Developers SCTLR hsctlr = tc->readMiscReg(MISCREG_HSCTLR); 50510037SARM gem5 Developers cpsr.t = hsctlr.te; 50610037SARM gem5 Developers cpsr.e = hsctlr.ee; 50710037SARM gem5 Developers if (!scr.ea) {cpsr.a = 1;} 50810037SARM gem5 Developers if (!scr.fiq) {cpsr.f = 1;} 50910037SARM gem5 Developers if (!scr.irq) {cpsr.i = 1;} 51010037SARM gem5 Developers } else if (cpsr.mode == MODE_MON) { 51110037SARM gem5 Developers // Special case handling when entering monitor mode 51210037SARM gem5 Developers cpsr.t = sctlr.te; 51310037SARM gem5 Developers cpsr.e = sctlr.ee; 51410037SARM gem5 Developers cpsr.a = 1; 51510037SARM gem5 Developers cpsr.f = 1; 51610037SARM gem5 Developers cpsr.i = 1; 51710037SARM gem5 Developers } else { 51810037SARM gem5 Developers cpsr.t = sctlr.te; 51910037SARM gem5 Developers cpsr.e = sctlr.ee; 52010037SARM gem5 Developers 52110037SARM gem5 Developers // The *Disable functions are virtual and different per fault 52210037SARM gem5 Developers cpsr.a = cpsr.a | abortDisable(tc); 52310037SARM gem5 Developers cpsr.f = cpsr.f | fiqDisable(tc); 52410037SARM gem5 Developers cpsr.i = 1; 52510037SARM gem5 Developers } 5266735Sgblack@eecs.umich.edu cpsr.it1 = cpsr.it2 = 0; 5276735Sgblack@eecs.umich.edu cpsr.j = 0; 5286735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_CPSR, cpsr); 52910037SARM gem5 Developers 5308518Sgeoffrey.blake@arm.com // Make sure mailbox sets to one always 5318518Sgeoffrey.blake@arm.com tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 5326735Sgblack@eecs.umich.edu 53310037SARM gem5 Developers // Clear the exclusive monitor 53410037SARM gem5 Developers tc->setMiscReg(MISCREG_LOCKFLAG, 0); 53510037SARM gem5 Developers 53610037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 53710037SARM gem5 Developers tc->setMiscReg(MISCREG_ELR_HYP, curPc + 53810037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true))); 53910037SARM gem5 Developers } else { 54010037SARM gem5 Developers tc->setIntReg(INTREG_LR, curPc + 54110037SARM gem5 Developers (saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false))); 54210037SARM gem5 Developers } 54310037SARM gem5 Developers 54410037SARM gem5 Developers switch (cpsr.mode) { 5456735Sgblack@eecs.umich.edu case MODE_FIQ: 5466735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_FIQ, saved_cpsr); 5476735Sgblack@eecs.umich.edu break; 5486735Sgblack@eecs.umich.edu case MODE_IRQ: 5496735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_IRQ, saved_cpsr); 5506735Sgblack@eecs.umich.edu break; 5516735Sgblack@eecs.umich.edu case MODE_SVC: 5526735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_SVC, saved_cpsr); 5536735Sgblack@eecs.umich.edu break; 55410037SARM gem5 Developers case MODE_MON: 55510037SARM gem5 Developers assert(have_security); 55610037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_MON, saved_cpsr); 5576735Sgblack@eecs.umich.edu break; 5586735Sgblack@eecs.umich.edu case MODE_ABORT: 5596735Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SPSR_ABT, saved_cpsr); 5606735Sgblack@eecs.umich.edu break; 56110037SARM gem5 Developers case MODE_UNDEFINED: 56210037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr); 56310037SARM gem5 Developers if (ec(tc) != EC_UNKNOWN) 56410037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 56510037SARM gem5 Developers break; 56610037SARM gem5 Developers case MODE_HYP: 56710037SARM gem5 Developers assert(have_virtualization); 56810037SARM gem5 Developers tc->setMiscReg(MISCREG_SPSR_HYP, saved_cpsr); 56910037SARM gem5 Developers setSyndrome(tc, MISCREG_HSR); 57010037SARM gem5 Developers break; 5716735Sgblack@eecs.umich.edu default: 5726735Sgblack@eecs.umich.edu panic("unknown Mode\n"); 5737093Sgblack@eecs.umich.edu } 5747093Sgblack@eecs.umich.edu 5757720Sgblack@eecs.umich.edu Addr newPc = getVector(tc); 5767585SAli.Saidi@arm.com DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x\n", 5777720Sgblack@eecs.umich.edu name(), cpsr, curPc, tc->readIntReg(INTREG_LR), newPc); 5787720Sgblack@eecs.umich.edu PCState pc(newPc); 5797720Sgblack@eecs.umich.edu pc.thumb(cpsr.t); 5807720Sgblack@eecs.umich.edu pc.nextThumb(pc.thumb()); 5817720Sgblack@eecs.umich.edu pc.jazelle(cpsr.j); 5827720Sgblack@eecs.umich.edu pc.nextJazelle(pc.jazelle()); 58310037SARM gem5 Developers pc.aarch64(!cpsr.width); 58410037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 5857720Sgblack@eecs.umich.edu tc->pcState(pc); 5866019Shines@cs.fsu.edu} 5877189Sgblack@eecs.umich.edu 5887400SAli.Saidi@ARM.comvoid 58910417Sandreas.hansson@arm.comArmFault::invoke64(ThreadContext *tc, const StaticInstPtr &inst) 59010037SARM gem5 Developers{ 59110037SARM gem5 Developers // Determine actual misc. register indices for ELR_ELx and SPSR_ELx 59210037SARM gem5 Developers MiscRegIndex elr_idx, spsr_idx; 59310037SARM gem5 Developers switch (toEL) { 59410037SARM gem5 Developers case EL1: 59510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL1; 59610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL1; 59710037SARM gem5 Developers break; 59811574SCurtis.Dunham@arm.com case EL2: 59911574SCurtis.Dunham@arm.com assert(ArmSystem::haveVirtualization(tc)); 60011574SCurtis.Dunham@arm.com elr_idx = MISCREG_ELR_EL2; 60111574SCurtis.Dunham@arm.com spsr_idx = MISCREG_SPSR_EL2; 60211574SCurtis.Dunham@arm.com break; 60310037SARM gem5 Developers case EL3: 60410037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 60510037SARM gem5 Developers elr_idx = MISCREG_ELR_EL3; 60610037SARM gem5 Developers spsr_idx = MISCREG_SPSR_EL3; 60710037SARM gem5 Developers break; 60810037SARM gem5 Developers default: 60910037SARM gem5 Developers panic("Invalid target exception level"); 61010037SARM gem5 Developers break; 61110037SARM gem5 Developers } 61210037SARM gem5 Developers 61310037SARM gem5 Developers // Save process state into SPSR_ELx 61410037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 61510037SARM gem5 Developers CPSR spsr = cpsr; 61610338SCurtis.Dunham@arm.com spsr.nz = tc->readCCReg(CCREG_NZ); 61710338SCurtis.Dunham@arm.com spsr.c = tc->readCCReg(CCREG_C); 61810338SCurtis.Dunham@arm.com spsr.v = tc->readCCReg(CCREG_V); 61910037SARM gem5 Developers if (from64) { 62010037SARM gem5 Developers // Force some bitfields to 0 62110037SARM gem5 Developers spsr.q = 0; 62210037SARM gem5 Developers spsr.it1 = 0; 62310037SARM gem5 Developers spsr.j = 0; 62410037SARM gem5 Developers spsr.res0_23_22 = 0; 62510037SARM gem5 Developers spsr.ge = 0; 62610037SARM gem5 Developers spsr.it2 = 0; 62710037SARM gem5 Developers spsr.t = 0; 62810037SARM gem5 Developers } else { 62910338SCurtis.Dunham@arm.com spsr.ge = tc->readCCReg(CCREG_GE); 63010037SARM gem5 Developers ITSTATE it = tc->pcState().itstate(); 63110037SARM gem5 Developers spsr.it2 = it.top6; 63210037SARM gem5 Developers spsr.it1 = it.bottom2; 63310037SARM gem5 Developers // Force some bitfields to 0 63410037SARM gem5 Developers spsr.res0_23_22 = 0; 63510037SARM gem5 Developers spsr.ss = 0; 63610037SARM gem5 Developers } 63710037SARM gem5 Developers tc->setMiscReg(spsr_idx, spsr); 63810037SARM gem5 Developers 63910037SARM gem5 Developers // Save preferred return address into ELR_ELx 64010037SARM gem5 Developers Addr curr_pc = tc->pcState().pc(); 64110037SARM gem5 Developers Addr ret_addr = curr_pc; 64210037SARM gem5 Developers if (from64) 64310037SARM gem5 Developers ret_addr += armPcElrOffset(); 64410037SARM gem5 Developers else 64510037SARM gem5 Developers ret_addr += spsr.t ? thumbPcElrOffset() : armPcElrOffset(); 64610037SARM gem5 Developers tc->setMiscReg(elr_idx, ret_addr); 64710037SARM gem5 Developers 64810037SARM gem5 Developers // Update process state 64910037SARM gem5 Developers OperatingMode64 mode = 0; 65010037SARM gem5 Developers mode.spX = 1; 65110037SARM gem5 Developers mode.el = toEL; 65210037SARM gem5 Developers mode.width = 0; 65310037SARM gem5 Developers cpsr.mode = mode; 65410037SARM gem5 Developers cpsr.daif = 0xf; 65510037SARM gem5 Developers cpsr.il = 0; 65610037SARM gem5 Developers cpsr.ss = 0; 65710037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 65810037SARM gem5 Developers 65910037SARM gem5 Developers // Set PC to start of exception handler 66010037SARM gem5 Developers Addr new_pc = purifyTaggedAddr(getVector64(tc), tc, toEL); 66110037SARM gem5 Developers DPRINTF(Faults, "Invoking Fault (AArch64 target EL):%s cpsr:%#x PC:%#x " 66210037SARM gem5 Developers "elr:%#x newVec: %#x\n", name(), cpsr, curr_pc, ret_addr, new_pc); 66310037SARM gem5 Developers PCState pc(new_pc); 66410037SARM gem5 Developers pc.aarch64(!cpsr.width); 66510037SARM gem5 Developers pc.nextAArch64(!cpsr.width); 66610037SARM gem5 Developers tc->pcState(pc); 66710037SARM gem5 Developers 66810037SARM gem5 Developers // If we have a valid instruction then use it to annotate this fault with 66910037SARM gem5 Developers // extra information. This is used to generate the correct fault syndrome 67010037SARM gem5 Developers // information 67110037SARM gem5 Developers if (inst) 67210037SARM gem5 Developers reinterpret_cast<ArmStaticInst *>(inst.get())->annotateFault(this); 67310037SARM gem5 Developers // Save exception syndrome 67410037SARM gem5 Developers if ((nextMode() != MODE_IRQ) && (nextMode() != MODE_FIQ)) 67510037SARM gem5 Developers setSyndrome(tc, getSyndromeReg64()); 67610037SARM gem5 Developers} 67710037SARM gem5 Developers 67810037SARM gem5 Developersvoid 67910417Sandreas.hansson@arm.comReset::invoke(ThreadContext *tc, const StaticInstPtr &inst) 6807400SAli.Saidi@ARM.com{ 6818782Sgblack@eecs.umich.edu if (FullSystem) { 68211150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupts(tc->threadId()); 6838782Sgblack@eecs.umich.edu tc->clearArchRegs(); 6848782Sgblack@eecs.umich.edu } 68510037SARM gem5 Developers if (!ArmSystem::highestELIs64(tc)) { 68610037SARM gem5 Developers ArmFault::invoke(tc, inst); 68710037SARM gem5 Developers tc->setMiscReg(MISCREG_VMPIDR, 68810037SARM gem5 Developers getMPIDR(dynamic_cast<ArmSystem*>(tc->getSystemPtr()), tc)); 68910037SARM gem5 Developers 69010037SARM gem5 Developers // Unless we have SMC code to get us there, boot in HYP! 69110037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc) && 69210037SARM gem5 Developers !ArmSystem::haveSecurity(tc)) { 69310037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 69410037SARM gem5 Developers cpsr.mode = MODE_HYP; 69510037SARM gem5 Developers tc->setMiscReg(MISCREG_CPSR, cpsr); 69610037SARM gem5 Developers } 69710037SARM gem5 Developers } else { 69810037SARM gem5 Developers // Advance the PC to the IMPLEMENTATION DEFINED reset value 69910037SARM gem5 Developers PCState pc = ArmSystem::resetAddr64(tc); 70010037SARM gem5 Developers pc.aarch64(true); 70110037SARM gem5 Developers pc.nextAArch64(true); 70210037SARM gem5 Developers tc->pcState(pc); 70310037SARM gem5 Developers } 7047400SAli.Saidi@ARM.com} 7057400SAli.Saidi@ARM.com 7067189Sgblack@eecs.umich.eduvoid 70710417Sandreas.hansson@arm.comUndefinedInstruction::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7087189Sgblack@eecs.umich.edu{ 7098782Sgblack@eecs.umich.edu if (FullSystem) { 7108782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7118806Sgblack@eecs.umich.edu return; 7128806Sgblack@eecs.umich.edu } 7138806Sgblack@eecs.umich.edu 7148806Sgblack@eecs.umich.edu // If the mnemonic isn't defined this has to be an unknown instruction. 7158806Sgblack@eecs.umich.edu assert(unknown || mnemonic != NULL); 7168806Sgblack@eecs.umich.edu if (disabled) { 7178806Sgblack@eecs.umich.edu panic("Attempted to execute disabled instruction " 7188806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7198806Sgblack@eecs.umich.edu } else if (unknown) { 7208806Sgblack@eecs.umich.edu panic("Attempted to execute unknown instruction (inst 0x%08x)", 7218806Sgblack@eecs.umich.edu machInst); 7227189Sgblack@eecs.umich.edu } else { 7238806Sgblack@eecs.umich.edu panic("Attempted to execute unimplemented instruction " 7248806Sgblack@eecs.umich.edu "'%s' (inst 0x%08x)", mnemonic, machInst); 7257189Sgblack@eecs.umich.edu } 7267189Sgblack@eecs.umich.edu} 7277189Sgblack@eecs.umich.edu 72810037SARM gem5 Developersbool 72910037SARM gem5 DevelopersUndefinedInstruction::routeToHyp(ThreadContext *tc) const 73010037SARM gem5 Developers{ 73110037SARM gem5 Developers bool toHyp; 73210037SARM gem5 Developers 73310037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 73410037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 73510037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 73610037SARM gem5 Developers 73710037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 73810037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 73910037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 74010037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 74110037SARM gem5 Developers return toHyp; 74210037SARM gem5 Developers} 74310037SARM gem5 Developers 74410037SARM gem5 Developersuint32_t 74510037SARM gem5 DevelopersUndefinedInstruction::iss() const 74610037SARM gem5 Developers{ 74710037SARM gem5 Developers if (overrideEc == EC_INVALID) 74810037SARM gem5 Developers return issRaw; 74910037SARM gem5 Developers 75010037SARM gem5 Developers uint32_t new_iss = 0; 75110037SARM gem5 Developers uint32_t op0, op1, op2, CRn, CRm, Rt, dir; 75210037SARM gem5 Developers 75310037SARM gem5 Developers dir = bits(machInst, 21, 21); 75410037SARM gem5 Developers op0 = bits(machInst, 20, 19); 75510037SARM gem5 Developers op1 = bits(machInst, 18, 16); 75610037SARM gem5 Developers CRn = bits(machInst, 15, 12); 75710037SARM gem5 Developers CRm = bits(machInst, 11, 8); 75810037SARM gem5 Developers op2 = bits(machInst, 7, 5); 75910037SARM gem5 Developers Rt = bits(machInst, 4, 0); 76010037SARM gem5 Developers 76110037SARM gem5 Developers new_iss = op0 << 20 | op2 << 17 | op1 << 14 | CRn << 10 | 76210037SARM gem5 Developers Rt << 5 | CRm << 1 | dir; 76310037SARM gem5 Developers 76410037SARM gem5 Developers return new_iss; 76510037SARM gem5 Developers} 76610037SARM gem5 Developers 7677197Sgblack@eecs.umich.eduvoid 76810417Sandreas.hansson@arm.comSupervisorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 7697197Sgblack@eecs.umich.edu{ 7708782Sgblack@eecs.umich.edu if (FullSystem) { 7718782Sgblack@eecs.umich.edu ArmFault::invoke(tc, inst); 7728806Sgblack@eecs.umich.edu return; 7738806Sgblack@eecs.umich.edu } 7747197Sgblack@eecs.umich.edu 7758806Sgblack@eecs.umich.edu // As of now, there isn't a 32 bit thumb version of this instruction. 7768806Sgblack@eecs.umich.edu assert(!machInst.bigThumb); 7778806Sgblack@eecs.umich.edu uint32_t callNum; 77810037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 77910037SARM gem5 Developers OperatingMode mode = (OperatingMode)(uint8_t)cpsr.mode; 78010037SARM gem5 Developers if (opModeIs64(mode)) 78110037SARM gem5 Developers callNum = tc->readIntReg(INTREG_X8); 78210037SARM gem5 Developers else 78310037SARM gem5 Developers callNum = tc->readIntReg(INTREG_R7); 7848806Sgblack@eecs.umich.edu tc->syscall(callNum); 7858806Sgblack@eecs.umich.edu 7868806Sgblack@eecs.umich.edu // Advance the PC since that won't happen automatically. 7878806Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7888806Sgblack@eecs.umich.edu assert(inst); 7898806Sgblack@eecs.umich.edu inst->advancePC(pc); 7908806Sgblack@eecs.umich.edu tc->pcState(pc); 7917197Sgblack@eecs.umich.edu} 7927197Sgblack@eecs.umich.edu 79310037SARM gem5 Developersbool 79410037SARM gem5 DevelopersSupervisorCall::routeToHyp(ThreadContext *tc) const 79510037SARM gem5 Developers{ 79610037SARM gem5 Developers bool toHyp; 79710037SARM gem5 Developers 79810037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 79910037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 80010037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 80110037SARM gem5 Developers 80210037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 80310037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 80410037SARM gem5 Developers // if HCR.TGE is set to 1, take to Hyp mode through Hyp Trap vector 80510037SARM gem5 Developers toHyp |= !inSecureState(scr, cpsr) && hcr.tge && (cpsr.mode == MODE_USER); 80610037SARM gem5 Developers return toHyp; 80710037SARM gem5 Developers} 80810037SARM gem5 Developers 80910037SARM gem5 DevelopersExceptionClass 81010037SARM gem5 DevelopersSupervisorCall::ec(ThreadContext *tc) const 81110037SARM gem5 Developers{ 81210037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 81310037SARM gem5 Developers (from64 ? EC_SVC_64 : vals.ec); 81410037SARM gem5 Developers} 81510037SARM gem5 Developers 81610037SARM gem5 Developersuint32_t 81710037SARM gem5 DevelopersSupervisorCall::iss() const 81810037SARM gem5 Developers{ 81910037SARM gem5 Developers // Even if we have a 24 bit imm from an arm32 instruction then we only use 82010037SARM gem5 Developers // the bottom 16 bits for the ISS value (it doesn't hurt for AArch64 SVC). 82110037SARM gem5 Developers return issRaw & 0xFFFF; 82210037SARM gem5 Developers} 82310037SARM gem5 Developers 82410037SARM gem5 Developersuint32_t 82510037SARM gem5 DevelopersSecureMonitorCall::iss() const 82610037SARM gem5 Developers{ 82710037SARM gem5 Developers if (from64) 82810037SARM gem5 Developers return bits(machInst, 20, 5); 82910037SARM gem5 Developers return 0; 83010037SARM gem5 Developers} 83110037SARM gem5 Developers 83210037SARM gem5 DevelopersExceptionClass 83310037SARM gem5 DevelopersUndefinedInstruction::ec(ThreadContext *tc) const 83410037SARM gem5 Developers{ 83510037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 83610037SARM gem5 Developers} 83710037SARM gem5 Developers 83810037SARM gem5 Developers 83910037SARM gem5 DevelopersHypervisorCall::HypervisorCall(ExtMachInst _machInst, uint32_t _imm) : 84010037SARM gem5 Developers ArmFaultVals<HypervisorCall>(_machInst, _imm) 84110037SARM gem5 Developers{} 84210037SARM gem5 Developers 84310037SARM gem5 DevelopersExceptionClass 84410037SARM gem5 DevelopersHypervisorTrap::ec(ThreadContext *tc) const 84510037SARM gem5 Developers{ 84610037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 84710037SARM gem5 Developers} 84810037SARM gem5 Developers 84910037SARM gem5 Developerstemplate<class T> 85010037SARM gem5 DevelopersFaultOffset 85110037SARM gem5 DevelopersArmFaultVals<T>::offset(ThreadContext *tc) 85210037SARM gem5 Developers{ 85310037SARM gem5 Developers bool isHypTrap = false; 85410037SARM gem5 Developers 85510037SARM gem5 Developers // Normally we just use the exception vector from the table at the top if 85610037SARM gem5 Developers // this file, however if this exception has caused a transition to hype 85710037SARM gem5 Developers // mode, and its an exception type that would only do this if it has been 85810037SARM gem5 Developers // trapped then we use the hyp trap vector instead of the normal vector 85910037SARM gem5 Developers if (vals.hypTrappable) { 86010037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 86110037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 86210037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 86310037SARM gem5 Developers isHypTrap = spsr.mode != MODE_HYP; 86410037SARM gem5 Developers } 86510037SARM gem5 Developers } 86610037SARM gem5 Developers return isHypTrap ? 0x14 : vals.offset; 86710037SARM gem5 Developers} 86810037SARM gem5 Developers 86910037SARM gem5 Developers// void 87010037SARM gem5 Developers// SupervisorCall::setSyndrome64(ThreadContext *tc, MiscRegIndex esr_idx) 87110037SARM gem5 Developers// { 87210037SARM gem5 Developers// ESR esr = 0; 87310037SARM gem5 Developers// esr.ec = machInst.aarch64 ? SvcAArch64 : SvcAArch32; 87410037SARM gem5 Developers// esr.il = !machInst.thumb; 87510037SARM gem5 Developers// if (machInst.aarch64) 87610037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 20, 5); 87710037SARM gem5 Developers// else if (machInst.thumb) 87810037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 7, 0); 87910037SARM gem5 Developers// else 88010037SARM gem5 Developers// esr.imm16 = bits(machInst.instBits, 15, 0); 88110037SARM gem5 Developers// tc->setMiscReg(esr_idx, esr); 88210037SARM gem5 Developers// } 88310037SARM gem5 Developers 88410037SARM gem5 Developersvoid 88510417Sandreas.hansson@arm.comSecureMonitorCall::invoke(ThreadContext *tc, const StaticInstPtr &inst) 88610037SARM gem5 Developers{ 88710037SARM gem5 Developers if (FullSystem) { 88810037SARM gem5 Developers ArmFault::invoke(tc, inst); 88910037SARM gem5 Developers return; 89010037SARM gem5 Developers } 89110037SARM gem5 Developers} 89210037SARM gem5 Developers 89310037SARM gem5 DevelopersExceptionClass 89410037SARM gem5 DevelopersSecureMonitorCall::ec(ThreadContext *tc) const 89510037SARM gem5 Developers{ 89610037SARM gem5 Developers return (from64 ? EC_SMC_64 : vals.ec); 89710037SARM gem5 Developers} 89810037SARM gem5 Developers 89910037SARM gem5 DevelopersExceptionClass 90010037SARM gem5 DevelopersSupervisorTrap::ec(ThreadContext *tc) const 90110037SARM gem5 Developers{ 90210037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : vals.ec; 90310037SARM gem5 Developers} 90410037SARM gem5 Developers 90510037SARM gem5 DevelopersExceptionClass 90610037SARM gem5 DevelopersSecureMonitorTrap::ec(ThreadContext *tc) const 90710037SARM gem5 Developers{ 90810037SARM gem5 Developers return (overrideEc != EC_INVALID) ? overrideEc : 90910037SARM gem5 Developers (from64 ? EC_SMC_64 : vals.ec); 91010037SARM gem5 Developers} 91110037SARM gem5 Developers 9127362Sgblack@eecs.umich.edutemplate<class T> 9137362Sgblack@eecs.umich.eduvoid 91410417Sandreas.hansson@arm.comAbortFault<T>::invoke(ThreadContext *tc, const StaticInstPtr &inst) 9157362Sgblack@eecs.umich.edu{ 91610037SARM gem5 Developers if (tranMethod == ArmFault::UnknownTran) { 91710037SARM gem5 Developers tranMethod = longDescFormatInUse(tc) ? ArmFault::LpaeTran 91810037SARM gem5 Developers : ArmFault::VmsaTran; 91910037SARM gem5 Developers 92010037SARM gem5 Developers if ((tranMethod == ArmFault::VmsaTran) && this->routeToMonitor(tc)) { 92110037SARM gem5 Developers // See ARM ARM B3-1416 92210037SARM gem5 Developers bool override_LPAE = false; 92310037SARM gem5 Developers TTBCR ttbcr_s = tc->readMiscReg(MISCREG_TTBCR_S); 92410037SARM gem5 Developers TTBCR M5_VAR_USED ttbcr_ns = tc->readMiscReg(MISCREG_TTBCR_NS); 92510037SARM gem5 Developers if (ttbcr_s.eae) { 92610037SARM gem5 Developers override_LPAE = true; 92710037SARM gem5 Developers } else { 92810037SARM gem5 Developers // Unimplemented code option, not seen in testing. May need 92910037SARM gem5 Developers // extension according to the manual exceprt above. 93010037SARM gem5 Developers DPRINTF(Faults, "Warning: Incomplete translation method " 93110037SARM gem5 Developers "override detected.\n"); 93210037SARM gem5 Developers } 93310037SARM gem5 Developers if (override_LPAE) 93410037SARM gem5 Developers tranMethod = ArmFault::LpaeTran; 93510037SARM gem5 Developers } 93610037SARM gem5 Developers } 93710037SARM gem5 Developers 93810037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 93911150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 94010037SARM gem5 Developers } 94110037SARM gem5 Developers // Get effective fault source encoding 94210037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 94310037SARM gem5 Developers FSR fsr = getFsr(tc); 94410037SARM gem5 Developers 94510037SARM gem5 Developers // source must be determined BEFORE invoking generic routines which will 94610037SARM gem5 Developers // try to set hsr etc. and are based upon source! 9478205SAli.Saidi@ARM.com ArmFaultVals<T>::invoke(tc, inst); 94810037SARM gem5 Developers 94911496Sandreas.sandberg@arm.com if (!this->to64) { // AArch32 95010037SARM gem5 Developers if (cpsr.mode == MODE_HYP) { 95110037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, faultAddr); 95210037SARM gem5 Developers } else if (stage2) { 95310037SARM gem5 Developers tc->setMiscReg(MISCREG_HPFAR, (faultAddr >> 8) & ~0xf); 95410037SARM gem5 Developers tc->setMiscReg(T::HFarIndex, OVAddr); 95510037SARM gem5 Developers } else { 95610037SARM gem5 Developers tc->setMiscReg(T::FsrIndex, fsr); 95710037SARM gem5 Developers tc->setMiscReg(T::FarIndex, faultAddr); 95810037SARM gem5 Developers } 95910037SARM gem5 Developers DPRINTF(Faults, "Abort Fault source=%#x fsr=%#x faultAddr=%#x "\ 96010037SARM gem5 Developers "tranMethod=%#x\n", source, fsr, faultAddr, tranMethod); 96110037SARM gem5 Developers } else { // AArch64 96210037SARM gem5 Developers // Set the FAR register. Nothing else to do if we are in AArch64 state 96310037SARM gem5 Developers // because the syndrome register has already been set inside invoke64() 96410037SARM gem5 Developers tc->setMiscReg(AbortFault<T>::getFaultAddrReg64(), faultAddr); 96510037SARM gem5 Developers } 96610037SARM gem5 Developers} 96710037SARM gem5 Developers 96810037SARM gem5 Developerstemplate<class T> 96910037SARM gem5 DevelopersFSR 97010037SARM gem5 DevelopersAbortFault<T>::getFsr(ThreadContext *tc) 97110037SARM gem5 Developers{ 9727362Sgblack@eecs.umich.edu FSR fsr = 0; 9738314Sgeoffrey.blake@arm.com 97410037SARM gem5 Developers if (((CPSR) tc->readMiscRegNoEffect(MISCREG_CPSR)).width) { 97510037SARM gem5 Developers // AArch32 97610037SARM gem5 Developers assert(tranMethod != ArmFault::UnknownTran); 97710037SARM gem5 Developers if (tranMethod == ArmFault::LpaeTran) { 97810037SARM gem5 Developers srcEncoded = ArmFault::longDescFaultSources[source]; 97910037SARM gem5 Developers fsr.status = srcEncoded; 98010037SARM gem5 Developers fsr.lpae = 1; 98110037SARM gem5 Developers } else { 98210037SARM gem5 Developers srcEncoded = ArmFault::shortDescFaultSources[source]; 98310037SARM gem5 Developers fsr.fsLow = bits(srcEncoded, 3, 0); 98410037SARM gem5 Developers fsr.fsHigh = bits(srcEncoded, 4); 98510037SARM gem5 Developers fsr.domain = static_cast<uint8_t>(domain); 98610037SARM gem5 Developers } 98710037SARM gem5 Developers fsr.wnr = (write ? 1 : 0); 98810037SARM gem5 Developers fsr.ext = 0; 98910037SARM gem5 Developers } else { 99010037SARM gem5 Developers // AArch64 99110037SARM gem5 Developers srcEncoded = ArmFault::aarch64FaultSources[source]; 99210037SARM gem5 Developers } 99310037SARM gem5 Developers if (srcEncoded == ArmFault::FaultSourceInvalid) { 99410037SARM gem5 Developers panic("Invalid fault source\n"); 99510037SARM gem5 Developers } 99610037SARM gem5 Developers return fsr; 99710037SARM gem5 Developers} 99810037SARM gem5 Developers 99910037SARM gem5 Developerstemplate<class T> 100010037SARM gem5 Developersbool 100110037SARM gem5 DevelopersAbortFault<T>::abortDisable(ThreadContext *tc) 100210037SARM gem5 Developers{ 100310037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 100410037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 100510037SARM gem5 Developers return (!scr.ns || scr.aw); 100610037SARM gem5 Developers } 100710037SARM gem5 Developers return true; 100810037SARM gem5 Developers} 100910037SARM gem5 Developers 101010037SARM gem5 Developerstemplate<class T> 101110037SARM gem5 Developersvoid 101210037SARM gem5 DevelopersAbortFault<T>::annotate(ArmFault::AnnotationIDs id, uint64_t val) 101310037SARM gem5 Developers{ 101410037SARM gem5 Developers switch (id) 101510037SARM gem5 Developers { 101610037SARM gem5 Developers case ArmFault::S1PTW: 101710037SARM gem5 Developers s1ptw = val; 101810037SARM gem5 Developers break; 101910037SARM gem5 Developers case ArmFault::OVA: 102010037SARM gem5 Developers OVAddr = val; 102110037SARM gem5 Developers break; 102210037SARM gem5 Developers 102310037SARM gem5 Developers // Just ignore unknown ID's 102410037SARM gem5 Developers default: 102510037SARM gem5 Developers break; 102610037SARM gem5 Developers } 102710037SARM gem5 Developers} 102810037SARM gem5 Developers 102910037SARM gem5 Developerstemplate<class T> 103010037SARM gem5 Developersuint32_t 103110037SARM gem5 DevelopersAbortFault<T>::iss() const 103210037SARM gem5 Developers{ 103310037SARM gem5 Developers uint32_t val; 103410037SARM gem5 Developers 103510037SARM gem5 Developers val = srcEncoded & 0x3F; 103610037SARM gem5 Developers val |= write << 6; 103710037SARM gem5 Developers val |= s1ptw << 7; 103810037SARM gem5 Developers return (val); 103910037SARM gem5 Developers} 104010037SARM gem5 Developers 104110037SARM gem5 Developerstemplate<class T> 104210037SARM gem5 Developersbool 104310037SARM gem5 DevelopersAbortFault<T>::isMMUFault() const 104410037SARM gem5 Developers{ 104510037SARM gem5 Developers // NOTE: Not relying on LL information being aligned to lowest bits here 104610037SARM gem5 Developers return 104710037SARM gem5 Developers (source == ArmFault::AlignmentFault) || 104810037SARM gem5 Developers ((source >= ArmFault::TranslationLL) && 104910037SARM gem5 Developers (source < ArmFault::TranslationLL + 4)) || 105010037SARM gem5 Developers ((source >= ArmFault::AccessFlagLL) && 105110037SARM gem5 Developers (source < ArmFault::AccessFlagLL + 4)) || 105210037SARM gem5 Developers ((source >= ArmFault::DomainLL) && 105310037SARM gem5 Developers (source < ArmFault::DomainLL + 4)) || 105410037SARM gem5 Developers ((source >= ArmFault::PermissionLL) && 105510037SARM gem5 Developers (source < ArmFault::PermissionLL + 4)); 105610037SARM gem5 Developers} 105710037SARM gem5 Developers 105810037SARM gem5 DevelopersExceptionClass 105910037SARM gem5 DevelopersPrefetchAbort::ec(ThreadContext *tc) const 106010037SARM gem5 Developers{ 106110037SARM gem5 Developers if (to64) { 106210037SARM gem5 Developers // AArch64 106310037SARM gem5 Developers if (toEL == fromEL) 106410037SARM gem5 Developers return EC_PREFETCH_ABORT_CURR_EL; 106510037SARM gem5 Developers else 106610037SARM gem5 Developers return EC_PREFETCH_ABORT_LOWER_EL; 106710037SARM gem5 Developers } else { 106810037SARM gem5 Developers // AArch32 106910037SARM gem5 Developers // Abort faults have different EC codes depending on whether 107010037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 107110037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 107210037SARM gem5 Developers 107310037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<PrefetchAbort>::vals.ec; 107410037SARM gem5 Developers 107510037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 107610037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 107710037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 107810037SARM gem5 Developers } 107910037SARM gem5 Developers return ec; 108010037SARM gem5 Developers } 108110037SARM gem5 Developers} 108210037SARM gem5 Developers 108310037SARM gem5 Developersbool 108410037SARM gem5 DevelopersPrefetchAbort::routeToMonitor(ThreadContext *tc) const 108510037SARM gem5 Developers{ 108610037SARM gem5 Developers SCR scr = 0; 108710037SARM gem5 Developers if (from64) 108810037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 108910037SARM gem5 Developers else 109010037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 109110037SARM gem5 Developers 109210037SARM gem5 Developers return scr.ea && !isMMUFault(); 109310037SARM gem5 Developers} 109410037SARM gem5 Developers 109510037SARM gem5 Developersbool 109610037SARM gem5 DevelopersPrefetchAbort::routeToHyp(ThreadContext *tc) const 109710037SARM gem5 Developers{ 109810037SARM gem5 Developers bool toHyp; 109910037SARM gem5 Developers 110010037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 110110037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 110210037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 110310037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 110410037SARM gem5 Developers 110510037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 110610037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 110710037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 110810037SARM gem5 Developers toHyp |= (stage2 || 110910037SARM gem5 Developers ( (source == DebugEvent) && hdcr.tde && (cpsr.mode != MODE_HYP)) || 111010037SARM gem5 Developers ( (source == SynchronousExternalAbort) && hcr.tge && (cpsr.mode == MODE_USER)) 111110037SARM gem5 Developers ) && !inSecureState(scr, cpsr); 111210037SARM gem5 Developers return toHyp; 111310037SARM gem5 Developers} 111410037SARM gem5 Developers 111510037SARM gem5 DevelopersExceptionClass 111610037SARM gem5 DevelopersDataAbort::ec(ThreadContext *tc) const 111710037SARM gem5 Developers{ 111810037SARM gem5 Developers if (to64) { 111910037SARM gem5 Developers // AArch64 112010037SARM gem5 Developers if (source == ArmFault::AsynchronousExternalAbort) { 112110367SAndrew.Bardsley@arm.com panic("Asynchronous External Abort should be handled with " 112210367SAndrew.Bardsley@arm.com "SystemErrors (SErrors)!"); 112310037SARM gem5 Developers } 112410037SARM gem5 Developers if (toEL == fromEL) 112510037SARM gem5 Developers return EC_DATA_ABORT_CURR_EL; 112610037SARM gem5 Developers else 112710037SARM gem5 Developers return EC_DATA_ABORT_LOWER_EL; 112810037SARM gem5 Developers } else { 112910037SARM gem5 Developers // AArch32 113010037SARM gem5 Developers // Abort faults have different EC codes depending on whether 113110037SARM gem5 Developers // the fault originated within HYP mode, or not. So override 113210037SARM gem5 Developers // the method and add the extra adjustment of the EC value. 113310037SARM gem5 Developers 113410037SARM gem5 Developers ExceptionClass ec = ArmFaultVals<DataAbort>::vals.ec; 113510037SARM gem5 Developers 113610037SARM gem5 Developers CPSR spsr = tc->readMiscReg(MISCREG_SPSR_HYP); 113710037SARM gem5 Developers if (spsr.mode == MODE_HYP) { 113810037SARM gem5 Developers ec = ((ExceptionClass) (((uint32_t) ec) + 1)); 113910037SARM gem5 Developers } 114010037SARM gem5 Developers return ec; 114110037SARM gem5 Developers } 114210037SARM gem5 Developers} 114310037SARM gem5 Developers 114410037SARM gem5 Developersbool 114510037SARM gem5 DevelopersDataAbort::routeToMonitor(ThreadContext *tc) const 114610037SARM gem5 Developers{ 114710037SARM gem5 Developers SCR scr = 0; 114810037SARM gem5 Developers if (from64) 114910037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 115010037SARM gem5 Developers else 115110037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 115210037SARM gem5 Developers 115310037SARM gem5 Developers return scr.ea && !isMMUFault(); 115410037SARM gem5 Developers} 115510037SARM gem5 Developers 115610037SARM gem5 Developersbool 115710037SARM gem5 DevelopersDataAbort::routeToHyp(ThreadContext *tc) const 115810037SARM gem5 Developers{ 115910037SARM gem5 Developers bool toHyp; 116010037SARM gem5 Developers 116110037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 116210037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 116310037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 116410037SARM gem5 Developers HDCR hdcr = tc->readMiscRegNoEffect(MISCREG_HDCR); 116510037SARM gem5 Developers 116610037SARM gem5 Developers // if in Hyp mode then stay in Hyp mode 116710037SARM gem5 Developers toHyp = scr.ns && (cpsr.mode == MODE_HYP); 116810037SARM gem5 Developers // otherwise, check whether to take to Hyp mode through Hyp Trap vector 116910037SARM gem5 Developers toHyp |= (stage2 || 117010037SARM gem5 Developers ( (cpsr.mode != MODE_HYP) && ( ((source == AsynchronousExternalAbort) && hcr.amo) || 117110037SARM gem5 Developers ((source == DebugEvent) && hdcr.tde) ) 117210037SARM gem5 Developers ) || 117310037SARM gem5 Developers ( (cpsr.mode == MODE_USER) && hcr.tge && 117410037SARM gem5 Developers ((source == AlignmentFault) || 117510037SARM gem5 Developers (source == SynchronousExternalAbort)) 117610037SARM gem5 Developers ) 117710037SARM gem5 Developers ) && !inSecureState(scr, cpsr); 117810037SARM gem5 Developers return toHyp; 117910037SARM gem5 Developers} 118010037SARM gem5 Developers 118110037SARM gem5 Developersuint32_t 118210037SARM gem5 DevelopersDataAbort::iss() const 118310037SARM gem5 Developers{ 118410037SARM gem5 Developers uint32_t val; 118510037SARM gem5 Developers 118610037SARM gem5 Developers // Add on the data abort specific fields to the generic abort ISS value 118710037SARM gem5 Developers val = AbortFault<DataAbort>::iss(); 118810037SARM gem5 Developers // ISS is valid if not caused by a stage 1 page table walk, and when taken 118910037SARM gem5 Developers // to AArch64 only when directed to EL2 119010037SARM gem5 Developers if (!s1ptw && (!to64 || toEL == EL2)) { 119110037SARM gem5 Developers val |= isv << 24; 119210037SARM gem5 Developers if (isv) { 119310037SARM gem5 Developers val |= sas << 22; 119410037SARM gem5 Developers val |= sse << 21; 119510037SARM gem5 Developers val |= srt << 16; 119610037SARM gem5 Developers // AArch64 only. These assignments are safe on AArch32 as well 119710037SARM gem5 Developers // because these vars are initialized to false 119810037SARM gem5 Developers val |= sf << 15; 119910037SARM gem5 Developers val |= ar << 14; 120010037SARM gem5 Developers } 120110037SARM gem5 Developers } 120210037SARM gem5 Developers return (val); 120310037SARM gem5 Developers} 120410037SARM gem5 Developers 120510037SARM gem5 Developersvoid 120610037SARM gem5 DevelopersDataAbort::annotate(AnnotationIDs id, uint64_t val) 120710037SARM gem5 Developers{ 120810037SARM gem5 Developers AbortFault<DataAbort>::annotate(id, val); 120910037SARM gem5 Developers switch (id) 121010037SARM gem5 Developers { 121110037SARM gem5 Developers case SAS: 121210037SARM gem5 Developers isv = true; 121310037SARM gem5 Developers sas = val; 121410037SARM gem5 Developers break; 121510037SARM gem5 Developers case SSE: 121610037SARM gem5 Developers isv = true; 121710037SARM gem5 Developers sse = val; 121810037SARM gem5 Developers break; 121910037SARM gem5 Developers case SRT: 122010037SARM gem5 Developers isv = true; 122110037SARM gem5 Developers srt = val; 122210037SARM gem5 Developers break; 122310037SARM gem5 Developers case SF: 122410037SARM gem5 Developers isv = true; 122510037SARM gem5 Developers sf = val; 122610037SARM gem5 Developers break; 122710037SARM gem5 Developers case AR: 122810037SARM gem5 Developers isv = true; 122910037SARM gem5 Developers ar = val; 123010037SARM gem5 Developers break; 123110037SARM gem5 Developers // Just ignore unknown ID's 123210037SARM gem5 Developers default: 123310037SARM gem5 Developers break; 123410037SARM gem5 Developers } 123510037SARM gem5 Developers} 123610037SARM gem5 Developers 123710037SARM gem5 Developersvoid 123810417Sandreas.hansson@arm.comVirtualDataAbort::invoke(ThreadContext *tc, const StaticInstPtr &inst) 123910037SARM gem5 Developers{ 124010037SARM gem5 Developers AbortFault<VirtualDataAbort>::invoke(tc, inst); 124110037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 124210037SARM gem5 Developers hcr.va = 0; 124310037SARM gem5 Developers tc->setMiscRegNoEffect(MISCREG_HCR, hcr); 124410037SARM gem5 Developers} 124510037SARM gem5 Developers 124610037SARM gem5 Developersbool 124710037SARM gem5 DevelopersInterrupt::routeToMonitor(ThreadContext *tc) const 124810037SARM gem5 Developers{ 124910037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 125010037SARM gem5 Developers SCR scr = 0; 125110037SARM gem5 Developers if (from64) 125210037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 125310037SARM gem5 Developers else 125410037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 125510037SARM gem5 Developers return scr.irq; 125610037SARM gem5 Developers} 125710037SARM gem5 Developers 125810037SARM gem5 Developersbool 125910037SARM gem5 DevelopersInterrupt::routeToHyp(ThreadContext *tc) const 126010037SARM gem5 Developers{ 126110037SARM gem5 Developers bool toHyp; 126210037SARM gem5 Developers 126310037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 126410037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 126510037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 126610037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 126710037SARM gem5 Developers toHyp = (!scr.irq && hcr.imo && !inSecureState(scr, cpsr)) || 126810037SARM gem5 Developers (cpsr.mode == MODE_HYP); 126910037SARM gem5 Developers return toHyp; 127010037SARM gem5 Developers} 127110037SARM gem5 Developers 127210037SARM gem5 Developersbool 127310037SARM gem5 DevelopersInterrupt::abortDisable(ThreadContext *tc) 127410037SARM gem5 Developers{ 127510037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 127610037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 127710037SARM gem5 Developers return (!scr.ns || scr.aw); 127810037SARM gem5 Developers } 127910037SARM gem5 Developers return true; 128010037SARM gem5 Developers} 128110037SARM gem5 Developers 128210037SARM gem5 DevelopersVirtualInterrupt::VirtualInterrupt() 128310037SARM gem5 Developers{} 128410037SARM gem5 Developers 128510037SARM gem5 Developersbool 128610037SARM gem5 DevelopersFastInterrupt::routeToMonitor(ThreadContext *tc) const 128710037SARM gem5 Developers{ 128810037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 128910037SARM gem5 Developers SCR scr = 0; 129010037SARM gem5 Developers if (from64) 129110037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 129210037SARM gem5 Developers else 129310037SARM gem5 Developers scr = tc->readMiscRegNoEffect(MISCREG_SCR); 129410037SARM gem5 Developers return scr.fiq; 129510037SARM gem5 Developers} 129610037SARM gem5 Developers 129710037SARM gem5 Developersbool 129810037SARM gem5 DevelopersFastInterrupt::routeToHyp(ThreadContext *tc) const 129910037SARM gem5 Developers{ 130010037SARM gem5 Developers bool toHyp; 130110037SARM gem5 Developers 130210037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 130310037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 130410037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 130510037SARM gem5 Developers // Determine whether IRQs are routed to Hyp mode. 130610037SARM gem5 Developers toHyp = (!scr.fiq && hcr.fmo && !inSecureState(scr, cpsr)) || 130710037SARM gem5 Developers (cpsr.mode == MODE_HYP); 130810037SARM gem5 Developers return toHyp; 130910037SARM gem5 Developers} 131010037SARM gem5 Developers 131110037SARM gem5 Developersbool 131210037SARM gem5 DevelopersFastInterrupt::abortDisable(ThreadContext *tc) 131310037SARM gem5 Developers{ 131410037SARM gem5 Developers if (ArmSystem::haveSecurity(tc)) { 131510037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 131610037SARM gem5 Developers return (!scr.ns || scr.aw); 131710037SARM gem5 Developers } 131810037SARM gem5 Developers return true; 131910037SARM gem5 Developers} 132010037SARM gem5 Developers 132110037SARM gem5 Developersbool 132210037SARM gem5 DevelopersFastInterrupt::fiqDisable(ThreadContext *tc) 132310037SARM gem5 Developers{ 132410037SARM gem5 Developers if (ArmSystem::haveVirtualization(tc)) { 132510037SARM gem5 Developers return true; 132610037SARM gem5 Developers } else if (ArmSystem::haveSecurity(tc)) { 132710037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); 132810037SARM gem5 Developers return (!scr.ns || scr.fw); 132910037SARM gem5 Developers } 133010037SARM gem5 Developers return true; 133110037SARM gem5 Developers} 133210037SARM gem5 Developers 133310037SARM gem5 DevelopersVirtualFastInterrupt::VirtualFastInterrupt() 133410037SARM gem5 Developers{} 133510037SARM gem5 Developers 133610037SARM gem5 Developersvoid 133710417Sandreas.hansson@arm.comPCAlignmentFault::invoke(ThreadContext *tc, const StaticInstPtr &inst) 133810037SARM gem5 Developers{ 133910037SARM gem5 Developers ArmFaultVals<PCAlignmentFault>::invoke(tc, inst); 134010037SARM gem5 Developers assert(from64); 134110037SARM gem5 Developers // Set the FAR 134210037SARM gem5 Developers tc->setMiscReg(getFaultAddrReg64(), faultPC); 134310037SARM gem5 Developers} 134410037SARM gem5 Developers 134510037SARM gem5 DevelopersSPAlignmentFault::SPAlignmentFault() 134610037SARM gem5 Developers{} 134710037SARM gem5 Developers 134810037SARM gem5 DevelopersSystemError::SystemError() 134910037SARM gem5 Developers{} 135010037SARM gem5 Developers 135110037SARM gem5 Developersvoid 135210417Sandreas.hansson@arm.comSystemError::invoke(ThreadContext *tc, const StaticInstPtr &inst) 135310037SARM gem5 Developers{ 135411150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_ABT, 0); 135510037SARM gem5 Developers ArmFault::invoke(tc, inst); 135610037SARM gem5 Developers} 135710037SARM gem5 Developers 135810037SARM gem5 Developersbool 135910037SARM gem5 DevelopersSystemError::routeToMonitor(ThreadContext *tc) const 136010037SARM gem5 Developers{ 136110037SARM gem5 Developers assert(ArmSystem::haveSecurity(tc)); 136210037SARM gem5 Developers assert(from64); 136310037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 136410037SARM gem5 Developers return scr.ea; 136510037SARM gem5 Developers} 136610037SARM gem5 Developers 136710037SARM gem5 Developersbool 136810037SARM gem5 DevelopersSystemError::routeToHyp(ThreadContext *tc) const 136910037SARM gem5 Developers{ 137010037SARM gem5 Developers bool toHyp; 137110037SARM gem5 Developers assert(from64); 137210037SARM gem5 Developers 137310037SARM gem5 Developers SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); 137410037SARM gem5 Developers HCR hcr = tc->readMiscRegNoEffect(MISCREG_HCR); 137510037SARM gem5 Developers CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR); 137610037SARM gem5 Developers 137710037SARM gem5 Developers toHyp = (!scr.ea && hcr.amo && !inSecureState(scr, cpsr)) || 137810037SARM gem5 Developers (!scr.ea && !scr.rw && !hcr.amo && !inSecureState(scr,cpsr)); 137910037SARM gem5 Developers return toHyp; 13807362Sgblack@eecs.umich.edu} 13817362Sgblack@eecs.umich.edu 13827652Sminkyu.jeong@arm.comvoid 138310417Sandreas.hansson@arm.comFlushPipe::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 13847652Sminkyu.jeong@arm.com DPRINTF(Faults, "Invoking FlushPipe Fault\n"); 13857652Sminkyu.jeong@arm.com 13867652Sminkyu.jeong@arm.com // Set the PC to the next instruction of the faulting instruction. 13877652Sminkyu.jeong@arm.com // Net effect is simply squashing all instructions behind and 13887652Sminkyu.jeong@arm.com // start refetching from the next instruction. 13897720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 13907720Sgblack@eecs.umich.edu assert(inst); 13917720Sgblack@eecs.umich.edu inst->advancePC(pc); 13927720Sgblack@eecs.umich.edu tc->pcState(pc); 13937652Sminkyu.jeong@arm.com} 13947652Sminkyu.jeong@arm.com 13958518Sgeoffrey.blake@arm.comvoid 139610417Sandreas.hansson@arm.comArmSev::invoke(ThreadContext *tc, const StaticInstPtr &inst) { 13978518Sgeoffrey.blake@arm.com DPRINTF(Faults, "Invoking ArmSev Fault\n"); 13988806Sgblack@eecs.umich.edu if (!FullSystem) 13998806Sgblack@eecs.umich.edu return; 14008806Sgblack@eecs.umich.edu 14018806Sgblack@eecs.umich.edu // Set sev_mailbox to 1, clear the pending interrupt from remote 14028806Sgblack@eecs.umich.edu // SEV execution and let pipeline continue as pcState is still 14038806Sgblack@eecs.umich.edu // valid. 14048806Sgblack@eecs.umich.edu tc->setMiscReg(MISCREG_SEV_MAILBOX, 1); 140511150Smitch.hayenga@arm.com tc->getCpuPtr()->clearInterrupt(tc->threadId(), INT_SEV, 0); 14068518Sgeoffrey.blake@arm.com} 14078518Sgeoffrey.blake@arm.com 140810037SARM gem5 Developers// Instantiate all the templates to make the linker happy 140910037SARM gem5 Developerstemplate class ArmFaultVals<Reset>; 141010037SARM gem5 Developerstemplate class ArmFaultVals<UndefinedInstruction>; 141110037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorCall>; 141210037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorCall>; 141310037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorCall>; 141410037SARM gem5 Developerstemplate class ArmFaultVals<PrefetchAbort>; 141510037SARM gem5 Developerstemplate class ArmFaultVals<DataAbort>; 141610037SARM gem5 Developerstemplate class ArmFaultVals<VirtualDataAbort>; 141710037SARM gem5 Developerstemplate class ArmFaultVals<HypervisorTrap>; 141810037SARM gem5 Developerstemplate class ArmFaultVals<Interrupt>; 141910037SARM gem5 Developerstemplate class ArmFaultVals<VirtualInterrupt>; 142010037SARM gem5 Developerstemplate class ArmFaultVals<FastInterrupt>; 142110037SARM gem5 Developerstemplate class ArmFaultVals<VirtualFastInterrupt>; 142210037SARM gem5 Developerstemplate class ArmFaultVals<SupervisorTrap>; 142310037SARM gem5 Developerstemplate class ArmFaultVals<SecureMonitorTrap>; 142410037SARM gem5 Developerstemplate class ArmFaultVals<PCAlignmentFault>; 142510037SARM gem5 Developerstemplate class ArmFaultVals<SPAlignmentFault>; 142610037SARM gem5 Developerstemplate class ArmFaultVals<SystemError>; 142710037SARM gem5 Developerstemplate class ArmFaultVals<FlushPipe>; 142810037SARM gem5 Developerstemplate class ArmFaultVals<ArmSev>; 142910037SARM gem5 Developerstemplate class AbortFault<PrefetchAbort>; 143010037SARM gem5 Developerstemplate class AbortFault<DataAbort>; 143110037SARM gem5 Developerstemplate class AbortFault<VirtualDataAbort>; 143210037SARM gem5 Developers 143310037SARM gem5 Developers 143410037SARM gem5 DevelopersIllegalInstSetStateFault::IllegalInstSetStateFault() 143510037SARM gem5 Developers{} 143610037SARM gem5 Developers 14376019Shines@cs.fsu.edu 14386019Shines@cs.fsu.edu} // namespace ArmISA 1439