decoder.hh revision 9478:ba80f7d4f452
12SN/A/* 21762SN/A * Copyright (c) 2012 Google 32SN/A * All rights reserved. 42SN/A * 52SN/A * Redistribution and use in source and binary forms, with or without 62SN/A * modification, are permitted provided that the following conditions are 72SN/A * met: redistributions of source code must retain the above copyright 82SN/A * notice, this list of conditions and the following disclaimer; 92SN/A * redistributions in binary form must reproduce the above copyright 102SN/A * notice, this list of conditions and the following disclaimer in the 112SN/A * documentation and/or other materials provided with the distribution; 122SN/A * neither the name of the copyright holders nor the names of its 132SN/A * contributors may be used to endorse or promote products derived from 142SN/A * this software without specific prior written permission. 152SN/A * 162SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Gabe Black 292SN/A */ 302SN/A 312SN/A#ifndef __ARCH_ARM_DECODER_HH__ 322SN/A#define __ARCH_ARM_DECODER_HH__ 332SN/A 342147SN/A#include <cassert> 352147SN/A 362SN/A#include "arch/arm/miscregs.hh" 372SN/A#include "arch/arm/types.hh" 382SN/A#include "arch/generic/decode_cache.hh" 392SN/A#include "base/types.hh" 402SN/A#include "cpu/static_inst.hh" 412SN/A 422SN/Anamespace ArmISA 432SN/A{ 442SN/A 452SN/Aclass Decoder 462SN/A{ 472SN/A protected: 482SN/A //The extended machine instruction being generated 492SN/A ExtMachInst emi; 502SN/A MachInst data; 512SN/A bool bigThumb; 522SN/A bool instDone; 532SN/A bool outOfBytes; 542SN/A int offset; 551078SN/A bool foundIt; 562SN/A ITSTATE itBits; 572SN/A 581114SN/A int fpscrLen; 591114SN/A int fpscrStride; 602SN/A 612SN/A public: 622SN/A void reset() 632SN/A { 641114SN/A bigThumb = false; 651114SN/A offset = 0; 662SN/A emi = 0; 672SN/A instDone = false; 682SN/A outOfBytes = true; 691114SN/A foundIt = false; 701114SN/A } 711114SN/A 721114SN/A Decoder() : data(0), fpscrLen(0), fpscrStride(0) 731114SN/A { 741114SN/A reset(); 751114SN/A } 761114SN/A 771114SN/A void process(); 782SN/A 792SN/A //Use this to give data to the decoder. This should be used 802SN/A //when there is control flow. 812SN/A void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst); 82502SN/A 832SN/A //Use this to give data to the decoder. This should be used 842SN/A //when instructions are executed in order. 852SN/A void moreBytes(MachInst machInst) 862SN/A { 872SN/A moreBytes(0, 0, machInst); 882SN/A } 892SN/A 902SN/A inline void consumeBytes(int numBytes) 912SN/A { 922SN/A offset += numBytes; 931114SN/A assert(offset <= sizeof(MachInst)); 941114SN/A if (offset == sizeof(MachInst)) 951114SN/A outOfBytes = true; 962SN/A } 972SN/A 982SN/A bool needMoreBytes() const 992SN/A { 1002SN/A return outOfBytes; 1012SN/A } 1022SN/A 1032SN/A bool instReady() const 1042SN/A { 1052SN/A return instDone; 1062SN/A } 1072SN/A 1082SN/A int getInstSize() const 1092SN/A { 1102SN/A return (!emi.thumb || emi.bigThumb) ? 4 : 2; 1112SN/A } 1122SN/A 1132SN/A void setContext(FPSCR fpscr) 1142SN/A { 1152SN/A fpscrLen = fpscr.len; 1162SN/A fpscrStride = fpscr.stride; 1172SN/A } 1182SN/A 1192SN/A void takeOverFrom(Decoder *old) {} 1202SN/A 1212SN/A protected: 1222SN/A /// A cache of decoded instruction objects. 1232SN/A static GenericISA::BasicDecodeCache defaultCache; 1242SN/A 1252SN/A public: 126 StaticInstPtr decodeInst(ExtMachInst mach_inst); 127 128 /// Decode a machine instruction. 129 /// @param mach_inst The binary instruction to decode. 130 /// @retval A pointer to the corresponding StaticInst object. 131 StaticInstPtr 132 decode(ExtMachInst mach_inst, Addr addr) 133 { 134 return defaultCache.decode(this, mach_inst, addr); 135 } 136 137 StaticInstPtr 138 decode(ArmISA::PCState &nextPC) 139 { 140 if (!instDone) 141 return NULL; 142 143 assert(instDone); 144 ExtMachInst thisEmi = emi; 145 nextPC.npc(nextPC.pc() + getInstSize()); 146 if (foundIt) 147 nextPC.nextItstate(itBits); 148 thisEmi.itstate = nextPC.itstate(); 149 nextPC.size(getInstSize()); 150 emi = 0; 151 instDone = false; 152 foundIt = false; 153 return decode(thisEmi, nextPC.instAddr()); 154 } 155}; 156 157} // namespace ArmISA 158 159#endif // __ARCH_ARM_DECODER_HH__ 160