decoder.hh revision 9374:227a38f9d98c 
1/*
2 * Copyright (c) 2012 Google
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __ARCH_ARM_DECODER_HH__
32#define __ARCH_ARM_DECODER_HH__
33
34#include <cassert>
35
36#include "arch/arm/miscregs.hh"
37#include "arch/arm/types.hh"
38#include "arch/generic/decode_cache.hh"
39#include "base/types.hh"
40#include "cpu/static_inst.hh"
41
42class ThreadContext;
43
44namespace ArmISA
45{
46
47class Decoder
48{
49  protected:
50    ThreadContext * tc;
51    //The extended machine instruction being generated
52    ExtMachInst emi;
53    MachInst data;
54    bool bigThumb;
55    bool instDone;
56    bool outOfBytes;
57    int offset;
58    bool foundIt;
59    ITSTATE itBits;
60
61    int fpscrLen;
62    int fpscrStride;
63
64  public:
65    void reset()
66    {
67        bigThumb = false;
68        offset = 0;
69        emi = 0;
70        instDone = false;
71        outOfBytes = true;
72        foundIt = false;
73    }
74
75    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
76        fpscrLen(0), fpscrStride(0)
77    {
78        reset();
79    }
80
81    ThreadContext * getTC()
82    {
83        return tc;
84    }
85
86    void
87    setTC(ThreadContext * _tc)
88    {
89        tc = _tc;
90    }
91
92    void process();
93
94    //Use this to give data to the decoder. This should be used
95    //when there is control flow.
96    void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
97
98    //Use this to give data to the decoder. This should be used
99    //when instructions are executed in order.
100    void moreBytes(MachInst machInst)
101    {
102        moreBytes(0, 0, machInst);
103    }
104
105    inline void consumeBytes(int numBytes)
106    {
107        offset += numBytes;
108        assert(offset <= sizeof(MachInst));
109        if (offset == sizeof(MachInst))
110            outOfBytes = true;
111    }
112
113    bool needMoreBytes() const
114    {
115        return outOfBytes;
116    }
117
118    bool instReady() const
119    {
120        return instDone;
121    }
122
123    int getInstSize() const
124    {
125        return (!emi.thumb || emi.bigThumb) ? 4 : 2;
126    }
127
128    void setContext(FPSCR fpscr)
129    {
130        fpscrLen = fpscr.len;
131        fpscrStride = fpscr.stride;
132    }
133
134  protected:
135    /// A cache of decoded instruction objects.
136    static GenericISA::BasicDecodeCache defaultCache;
137
138  public:
139    StaticInstPtr decodeInst(ExtMachInst mach_inst);
140
141    /// Decode a machine instruction.
142    /// @param mach_inst The binary instruction to decode.
143    /// @retval A pointer to the corresponding StaticInst object.
144    StaticInstPtr
145    decode(ExtMachInst mach_inst, Addr addr)
146    {
147        return defaultCache.decode(this, mach_inst, addr);
148    }
149
150    StaticInstPtr
151    decode(ArmISA::PCState &nextPC)
152    {
153        if (!instDone)
154            return NULL;
155
156        assert(instDone);
157        ExtMachInst thisEmi = emi;
158        nextPC.npc(nextPC.pc() + getInstSize());
159        if (foundIt)
160            nextPC.nextItstate(itBits);
161        thisEmi.itstate = nextPC.itstate();
162        nextPC.size(getInstSize());
163        emi = 0;
164        instDone = false;
165        foundIt = false;
166        return decode(thisEmi, nextPC.instAddr());
167    }
168};
169
170} // namespace ArmISA
171
172#endif // __ARCH_ARM_DECODER_HH__
173