decoder.hh revision 10610:5fae03bd840a 
1/*
2 * Copyright (c) 2013-2014 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2012 Google
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __ARCH_ARM_DECODER_HH__
44#define __ARCH_ARM_DECODER_HH__
45
46#include <cassert>
47
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/types.hh"
50#include "arch/generic/decode_cache.hh"
51#include "base/types.hh"
52#include "cpu/static_inst.hh"
53
54namespace ArmISA
55{
56
57class Decoder
58{
59  protected:
60    //The extended machine instruction being generated
61    ExtMachInst emi;
62    MachInst data;
63    bool bigThumb;
64    bool instDone;
65    bool outOfBytes;
66    int offset;
67    bool foundIt;
68    ITSTATE itBits;
69
70    int fpscrLen;
71    int fpscrStride;
72
73    /// A cache of decoded instruction objects.
74    static GenericISA::BasicDecodeCache defaultCache;
75
76    /**
77     * Pre-decode an instruction from the current state of the
78     * decoder.
79     */
80    void process();
81
82    /**
83     * Consume bytes by moving the offset into the data word and
84     * sanity check the results.
85     */
86    void consumeBytes(int numBytes);
87
88  public: // Decoder API
89    Decoder();
90
91    /** Reset the decoders internal state. */
92    void reset();
93
94    /**
95     * Can the decoder accept more data?
96     *
97     * A CPU model uses this method to determine if the decoder can
98     * accept more data. Note that an instruction can be ready (see
99     * instReady() even if this method returns true.
100     */
101    bool needMoreBytes() const { return outOfBytes; }
102
103    /**
104     * Is an instruction ready to be decoded?
105     *
106     * CPU models call this method to determine if decode() will
107     * return a new instruction on the next call. It typically only
108     * returns false if the decoder hasn't received enough data to
109     * decode a full instruction.
110     */
111    bool instReady() const { return instDone; }
112
113    /**
114     * Feed data to the decoder.
115     *
116     * A CPU model uses this interface to load instruction data into
117     * the decoder. Once enough data has been loaded (check with
118     * instReady()), a decoded instruction can be retrieved using
119     * decode(ArmISA::PCState).
120     *
121     * This method is intended to support both fixed-length and
122     * variable-length instructions. Instruction data is fetch in
123     * MachInst blocks (which correspond to the size of a typical
124     * insturction). The method might need to be called multiple times
125     * if the instruction spans multiple blocks, in that case
126     * needMoreBytes() will return true and instReady() will return
127     * false.
128     *
129     * The fetchPC parameter is used to indicate where in memory the
130     * instruction was fetched from. This is should be the same
131     * address as the pc. If fetching multiple blocks, it indicates
132     * where subsequent blocks are fetched from (pc + n *
133     * sizeof(MachInst)).
134     *
135     * @param pc Instruction pointer that we are decoding.
136     * @param fetchPC The address this chunk was fetched from.
137     * @param inst Raw instruction data.
138     */
139    void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
140
141    /**
142     * Decode an instruction or fetch it from the code cache.
143     *
144     * This method decodes the currently pending pre-decoded
145     * instruction. Data must be fed to the decoder using moreBytes()
146     * until instReady() is true before calling this method.
147     *
148     * @param pc Instruction pointer that we are decoding.
149     * @return A pointer to a static instruction or NULL if the
150     * decoder isn't ready (see instReady()).
151     */
152    StaticInstPtr decode(ArmISA::PCState &pc);
153
154    /**
155     * Decode a pre-decoded machine instruction.
156     *
157     * @warn This method takes a pre-decoded instruction as its
158     * argument. It should typically not be called directly.
159     *
160     * @param mach_inst A pre-decoded instruction
161     * @retval A pointer to the corresponding StaticInst object.
162     */
163    StaticInstPtr decode(ExtMachInst mach_inst, Addr addr)
164    {
165        return defaultCache.decode(this, mach_inst, addr);
166    }
167
168    /**
169     * Decode a machine instruction without calling the cache.
170     *
171     * @note The implementation of this method is generated by the ISA
172     * parser script.
173     *
174     * @warn This method takes a pre-decoded instruction as its
175     * argument. It should typically not be called directly.
176     *
177     * @param mach_inst The binary instruction to decode.
178     * @retval A pointer to the corresponding StaticInst object.
179     */
180    StaticInstPtr decodeInst(ExtMachInst mach_inst);
181
182    /**
183     * Take over the state from an old decoder when switching CPUs.
184     *
185     * @param old Decoder used in old CPU
186     */
187    void takeOverFrom(Decoder *old) {}
188
189
190  public: // ARM-specific decoder state manipulation
191    void setContext(FPSCR fpscr)
192    {
193        fpscrLen = fpscr.len;
194        fpscrStride = fpscr.stride;
195    }
196};
197
198} // namespace ArmISA
199
200#endif // __ARCH_ARM_DECODER_HH__
201