xref: /gem5/src/arch/arm/SConscript

# -*- mode:python -*-

# Copyright (c) 2009 ARM Limited
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# Copyright (c) 2007-2008 The Florida State University
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# Authors: Stephen Hines
#          Ali Saidi

Import('*')

if env['TARGET_ISA'] == 'arm':
# Workaround for bug in SCons version > 0.97d20071212
# Scons bug id: 2006 M5 Bug id: 308 
    Dir('isa/formats')
    Source('faults.cc')
    Source('insts/branch.cc')
    Source('insts/macromem.cc')
    Source('insts/mem.cc')
    Source('insts/misc.cc')
    Source('insts/pred_inst.cc')
    Source('insts/static_inst.cc')
    Source('miscregs.cc')
    Source('nativetrace.cc')
    Source('pagetable.cc')
    Source('tlb.cc')
    Source('vtophys.cc')
    Source('utility.cc')

    SimObject('ArmNativeTrace.py')
    SimObject('ArmTLB.py')

    TraceFlag('Arm')
    TraceFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
    TraceFlag('Predecoder', "Instructions returned by the predecoder")
    if env['FULL_SYSTEM']:
        Source('interrupts.cc')
        Source('stacktrace.cc')
        Source('system.cc')
        
        SimObject('ArmInterrupts.py')
        SimObject('ArmSystem.py')
    else:
        Source('process.cc')
        Source('linux/linux.cc')
        Source('linux/process.cc')

    # Add in files generated by the ISA description.
    isa_desc_files = env.ISADesc('isa/main.isa')
    # Only non-header files need to be compiled.
    for f in isa_desc_files:
        if not f.path.endswith('.hh'):
            Source(f)