SConscript revision 13759 
1# -*- mode:python -*-
2
3# Copyright (c) 2009, 2012-2013, 2017-2018 ARM Limited
4# All rights reserved.
5#
6# The license below extends only to copyright in the software and shall
7# not be construed as granting a license to any other intellectual
8# property including but not limited to intellectual property relating
9# to a hardware implementation of the functionality of the software
10# licensed hereunder.  You may use the software subject to the license
11# terms below provided that you ensure that this notice is replicated
12# unmodified and in its entirety in all distributions of the software,
13# modified or unmodified, in source code or in binary form.
14#
15# Copyright (c) 2007-2008 The Florida State University
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Stephen Hines
42#          Ali Saidi
43
44Import('*')
45
46if env['TARGET_ISA'] == 'arm':
47# Workaround for bug in SCons version > 0.97d20071212
48# Scons bug id: 2006 M5 Bug id: 308
49    Dir('isa/formats')
50    Source('decoder.cc')
51    Source('faults.cc')
52    Source('insts/branch.cc')
53    Source('insts/branch64.cc')
54    Source('insts/data64.cc')
55    Source('insts/macromem.cc')
56    Source('insts/mem.cc')
57    Source('insts/mem64.cc')
58    Source('insts/misc.cc')
59    Source('insts/misc64.cc')
60    Source('insts/pred_inst.cc')
61    Source('insts/pseudo.cc')
62    Source('insts/static_inst.cc')
63    Source('insts/sve.cc')
64    Source('insts/vfp.cc')
65    Source('insts/fplib.cc')
66    Source('insts/crypto.cc')
67    Source('interrupts.cc')
68    Source('isa.cc')
69    Source('isa_device.cc')
70    Source('linux/linux.cc')
71    Source('linux/process.cc')
72    Source('linux/system.cc')
73    Source('freebsd/freebsd.cc')
74    Source('freebsd/process.cc')
75    Source('freebsd/system.cc')
76    Source('miscregs.cc')
77    Source('nativetrace.cc')
78    Source('pmu.cc')
79    Source('process.cc')
80    Source('remote_gdb.cc')
81    Source('semihosting.cc')
82    Source('stacktrace.cc')
83    Source('system.cc')
84    Source('table_walker.cc')
85    Source('stage2_mmu.cc')
86    Source('stage2_lookup.cc')
87    Source('tlb.cc')
88    Source('tlbi_op.cc')
89    Source('utility.cc')
90    Source('vtophys.cc')
91
92    SimObject('ArmInterrupts.py')
93    SimObject('ArmISA.py')
94    SimObject('ArmNativeTrace.py')
95    SimObject('ArmSemihosting.py')
96    SimObject('ArmSystem.py')
97    SimObject('ArmTLB.py')
98    SimObject('ArmPMU.py')
99
100    DebugFlag('Arm')
101    DebugFlag('Semihosting')
102    DebugFlag('Decoder', "Instructions returned by the predecoder")
103    DebugFlag('Faults', "Trace Exceptions, interrupts, svc/swi")
104    DebugFlag('PMUVerbose', "Performance Monitor")
105    DebugFlag('TLBVerbose')
106
107    # Add files generated by the ISA description.
108    ISADesc('isa/main.isa', decoder_splits=3, exec_splits=6)
109
110    GdbXml('arm/arm-with-neon.xml', 'gdb_xml_arm_target')
111    GdbXml('arm/arm-core.xml', 'gdb_xml_arm_core')
112    GdbXml('arm/arm-vfpv3.xml', 'gdb_xml_arm_vfpv3')
113    GdbXml('aarch64.xml', 'gdb_xml_aarch64_target')
114    GdbXml('aarch64-core.xml', 'gdb_xml_aarch64_core')
115    GdbXml('aarch64-fpu.xml', 'gdb_xml_aarch64_fpu')
116