ArmSystem.py revision 13173:210b6fc57533
12SN/A# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited 25522Snate@binkert.org# All rights reserved. 32SN/A# 42SN/A# The license below extends only to copyright in the software and shall 52SN/A# not be construed as granting a license to any other intellectual 62SN/A# property including but not limited to intellectual property relating 72SN/A# to a hardware implementation of the functionality of the software 82SN/A# licensed hereunder. You may use the software subject to the license 92SN/A# terms below provided that you ensure that this notice is replicated 102SN/A# unmodified and in its entirety in all distributions of the software, 112SN/A# modified or unmodified, in source code or in binary form. 122SN/A# 132SN/A# Redistribution and use in source and binary forms, with or without 142SN/A# modification, are permitted provided that the following conditions are 152SN/A# met: redistributions of source code must retain the above copyright 162SN/A# notice, this list of conditions and the following disclaimer; 172SN/A# redistributions in binary form must reproduce the above copyright 182SN/A# notice, this list of conditions and the following disclaimer in the 192SN/A# documentation and/or other materials provided with the distribution; 202SN/A# neither the name of the copyright holders nor the names of its 212SN/A# contributors may be used to endorse or promote products derived from 222SN/A# this software without specific prior written permission. 232SN/A# 242SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 252SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 262SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 272665Ssaidi@eecs.umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 284123Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 292SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 302SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 314123Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 322655Sstever@eecs.umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 335522Snate@binkert.org# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3410453SAndrew.Bardsley@arm.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 352SN/A# 365522Snate@binkert.org# Authors: Ali Saidi 375522Snate@binkert.org# Glenn Bergmans 385522Snate@binkert.org 395522Snate@binkert.orgfrom m5.params import * 404941Snate@binkert.orgfrom m5.SimObject import * 412SN/Afrom m5.util.fdthelper import * 422SN/A 435522Snate@binkert.orgfrom System import System 445522Snate@binkert.orgfrom ArmSemihosting import ArmSemihosting 455522Snate@binkert.org 465522Snate@binkert.orgclass ArmMachineType(Enum): 472SN/A map = { 482655Sstever@eecs.umich.edu 'RealViewPBX' : 1901, 492667Sstever@eecs.umich.edu 'VExpress_EMM' : 2272, 502667Sstever@eecs.umich.edu 'VExpress_EMM64' : 2272, 512655Sstever@eecs.umich.edu 'DTOnly' : -1, 521311SN/A } 535522Snate@binkert.org 545522Snate@binkert.orgclass ArmSystem(System): 551703SN/A type = 'ArmSystem' 565522Snate@binkert.org cxx_header = "arch/arm/system.hh" 575522Snate@binkert.org multi_proc = Param.Bool(True, "Multiprocessor system?") 585522Snate@binkert.org boot_loader = VectorParam.String([], 595522Snate@binkert.org "File that contains the boot loader code. Zero or more files may be " 602667Sstever@eecs.umich.edu "specified. The first boot loader that matches the kernel's " 612667Sstever@eecs.umich.edu "architecture will be used.") 622655Sstever@eecs.umich.edu gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface") 634941Snate@binkert.org flags_addr = Param.Addr(0, "Address of the flags register for MP booting") 644941Snate@binkert.org have_security = Param.Bool(False, 652667Sstever@eecs.umich.edu "True if Security Extensions are implemented") 66 have_virtualization = Param.Bool(False, 67 "True if Virtualization Extensions are implemented") 68 have_crypto = Param.Bool(False, 69 "True if Crypto Extensions is implemented") 70 have_lpae = Param.Bool(True, "True if LPAE is implemented") 71 highest_el_is_64 = Param.Bool(False, 72 "True if the register width of the highest implemented exception level " 73 "is 64 bits (ARMv8)") 74 reset_addr_64 = Param.Addr(0x0, 75 "Reset address if the highest implemented exception level is 64 bits " 76 "(ARMv8)") 77 auto_reset_addr_64 = Param.Bool(False, 78 "Determine reset address from kernel entry point if no boot loader") 79 phys_addr_range_64 = Param.UInt8(40, 80 "Supported physical address range in bits when using AArch64 (ARMv8)") 81 have_large_asid_64 = Param.Bool(False, 82 "True if ASID is 16 bits in AArch64 (ARMv8)") 83 84 semihosting = Param.ArmSemihosting(NULL, 85 "Enable support for the Arm semihosting by settings this parameter") 86 87 m5ops_base = Param.Addr(0, 88 "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " 89 "to disable.") 90 91 def generateDeviceTree(self, state): 92 # Generate a device tree root node for the system by creating the root 93 # node and adding the generated subnodes of all children. 94 # When a child needs to add multiple nodes, this is done by also 95 # creating a node called '/' which will then be merged with the 96 # root instead of appended. 97 98 def generateMemNode(mem_range): 99 node = FdtNode("memory@%x" % long(mem_range.start)) 100 node.append(FdtPropertyStrings("device_type", ["memory"])) 101 node.append(FdtPropertyWords("reg", 102 state.addrCells(mem_range.start) + 103 state.sizeCells(mem_range.size()) )) 104 return node 105 106 root = FdtNode('/') 107 root.append(state.addrCellsProperty()) 108 root.append(state.sizeCellsProperty()) 109 110 # Add memory nodes 111 for mem_range in self.mem_ranges: 112 root.append(generateMemNode(mem_range)) 113 114 for node in self.recurseDeviceTree(state): 115 # Merge root nodes instead of adding them (for children 116 # that need to add multiple root level nodes) 117 if node.get_name() == root.get_name(): 118 root.merge(node) 119 else: 120 root.append(node) 121 122 return root 123 124class GenericArmSystem(ArmSystem): 125 type = 'GenericArmSystem' 126 cxx_header = "arch/arm/system.hh" 127 machine_type = Param.ArmMachineType('DTOnly', 128 "Machine id from http://www.arm.linux.org.uk/developer/machines/") 129 atags_addr = Param.Addr("Address where default atags structure should " \ 130 "be written") 131 dtb_filename = Param.String("", 132 "File that contains the Device Tree Blob. Don't use DTB if empty.") 133 early_kernel_symbols = Param.Bool(False, 134 "enable early kernel symbol tables before MMU") 135 enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries") 136 137 panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \ 138 "guest kernel panics") 139 panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \ 140 "guest kernel oopses") 141 142class LinuxArmSystem(GenericArmSystem): 143 type = 'LinuxArmSystem' 144 cxx_header = "arch/arm/linux/system.hh" 145 146 @cxxMethod 147 def dumpDmesg(self): 148 """Dump dmesg from the simulated kernel to standard out""" 149 pass 150 151 # Have Linux systems for ARM auto-calc their load_addr_mask for proper 152 # kernel relocation. 153 load_addr_mask = 0x0 154 155class FreebsdArmSystem(GenericArmSystem): 156 type = 'FreebsdArmSystem' 157 cxx_header = "arch/arm/freebsd/system.hh" 158