ArmSystem.py revision 13167:258a04d4c20b
1# Copyright (c) 2009, 2012-2013, 2015-2018 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Redistribution and use in source and binary forms, with or without 14# modification, are permitted provided that the following conditions are 15# met: redistributions of source code must retain the above copyright 16# notice, this list of conditions and the following disclaimer; 17# redistributions in binary form must reproduce the above copyright 18# notice, this list of conditions and the following disclaimer in the 19# documentation and/or other materials provided with the distribution; 20# neither the name of the copyright holders nor the names of its 21# contributors may be used to endorse or promote products derived from 22# this software without specific prior written permission. 23# 24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35# 36# Authors: Ali Saidi 37# Glenn Bergmans 38 39from m5.params import * 40from m5.SimObject import * 41from m5.util.fdthelper import * 42 43from System import System 44from ArmSemihosting import ArmSemihosting 45 46class ArmMachineType(Enum): 47 map = { 48 'RealViewPBX' : 1901, 49 'VExpress_EMM' : 2272, 50 'VExpress_EMM64' : 2272, 51 'DTOnly' : -1, 52 } 53 54class ArmSystem(System): 55 type = 'ArmSystem' 56 cxx_header = "arch/arm/system.hh" 57 multi_proc = Param.Bool(True, "Multiprocessor system?") 58 boot_loader = VectorParam.String([], 59 "File that contains the boot loader code. Zero or more files may be " 60 "specified. The first boot loader that matches the kernel's " 61 "architecture will be used.") 62 gic_cpu_addr = Param.Addr(0, "Addres of the GIC CPU interface") 63 flags_addr = Param.Addr(0, "Address of the flags register for MP booting") 64 have_security = Param.Bool(False, 65 "True if Security Extensions are implemented") 66 have_virtualization = Param.Bool(False, 67 "True if Virtualization Extensions are implemented") 68 have_lpae = Param.Bool(True, "True if LPAE is implemented") 69 highest_el_is_64 = Param.Bool(False, 70 "True if the register width of the highest implemented exception level " 71 "is 64 bits (ARMv8)") 72 reset_addr_64 = Param.Addr(0x0, 73 "Reset address if the highest implemented exception level is 64 bits " 74 "(ARMv8)") 75 auto_reset_addr_64 = Param.Bool(False, 76 "Determine reset address from kernel entry point if no boot loader") 77 phys_addr_range_64 = Param.UInt8(40, 78 "Supported physical address range in bits when using AArch64 (ARMv8)") 79 have_large_asid_64 = Param.Bool(False, 80 "True if ASID is 16 bits in AArch64 (ARMv8)") 81 82 semihosting = Param.ArmSemihosting(NULL, 83 "Enable support for the Arm semihosting by settings this parameter") 84 85 m5ops_base = Param.Addr(0, 86 "Base of the 64KiB PA range used for memory-mapped m5ops. Set to 0 " 87 "to disable.") 88 89 def generateDeviceTree(self, state): 90 # Generate a device tree root node for the system by creating the root 91 # node and adding the generated subnodes of all children. 92 # When a child needs to add multiple nodes, this is done by also 93 # creating a node called '/' which will then be merged with the 94 # root instead of appended. 95 96 def generateMemNode(mem_range): 97 node = FdtNode("memory@%x" % long(mem_range.start)) 98 node.append(FdtPropertyStrings("device_type", ["memory"])) 99 node.append(FdtPropertyWords("reg", 100 state.addrCells(mem_range.start) + 101 state.sizeCells(mem_range.size()) )) 102 return node 103 104 root = FdtNode('/') 105 root.append(state.addrCellsProperty()) 106 root.append(state.sizeCellsProperty()) 107 108 # Add memory nodes 109 for mem_range in self.mem_ranges: 110 root.append(generateMemNode(mem_range)) 111 112 for node in self.recurseDeviceTree(state): 113 # Merge root nodes instead of adding them (for children 114 # that need to add multiple root level nodes) 115 if node.get_name() == root.get_name(): 116 root.merge(node) 117 else: 118 root.append(node) 119 120 return root 121 122class GenericArmSystem(ArmSystem): 123 type = 'GenericArmSystem' 124 cxx_header = "arch/arm/system.hh" 125 machine_type = Param.ArmMachineType('DTOnly', 126 "Machine id from http://www.arm.linux.org.uk/developer/machines/") 127 atags_addr = Param.Addr("Address where default atags structure should " \ 128 "be written") 129 dtb_filename = Param.String("", 130 "File that contains the Device Tree Blob. Don't use DTB if empty.") 131 early_kernel_symbols = Param.Bool(False, 132 "enable early kernel symbol tables before MMU") 133 enable_context_switch_stats_dump = Param.Bool(False, "enable stats/task info dumping at context switch boundaries") 134 135 panic_on_panic = Param.Bool(False, "Trigger a gem5 panic if the " \ 136 "guest kernel panics") 137 panic_on_oops = Param.Bool(False, "Trigger a gem5 panic if the " \ 138 "guest kernel oopses") 139 140class LinuxArmSystem(GenericArmSystem): 141 type = 'LinuxArmSystem' 142 cxx_header = "arch/arm/linux/system.hh" 143 144 @cxxMethod 145 def dumpDmesg(self): 146 """Dump dmesg from the simulated kernel to standard out""" 147 pass 148 149 # Have Linux systems for ARM auto-calc their load_addr_mask for proper 150 # kernel relocation. 151 load_addr_mask = 0x0 152 153class FreebsdArmSystem(GenericArmSystem): 154 type = 'FreebsdArmSystem' 155 cxx_header = "arch/arm/freebsd/system.hh" 156