ArmPMU.py revision 10465:a42b8d98fddc 
1# -*- mode:python -*-
2# Copyright (c) 2009-2014 ARM Limited
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37# Authors: Matt Horsnell
38#          Andreas Sandberg
39
40from m5.defines import buildEnv
41from m5.SimObject import SimObject
42from m5.params import *
43from m5.params import isNullPointer
44from m5.proxy import *
45
46class ArmPMU(SimObject):
47    type = 'ArmPMU'
48    cxx_class = 'ArmISA::PMU'
49    cxx_header = 'arch/arm/pmu.hh'
50
51    @classmethod
52    def export_methods(cls, code):
53        code('''
54      void addEventProbe(unsigned int id,
55                        SimObject *obj, const char *name);
56''')
57
58    # To prevent cycles in the configuration hierarchy, we don't keep
59    # a list of supported events as a configuration param. Instead, we
60    # keep them in a local list and register them using the
61    # addEventProbe interface when other SimObjects register their
62    # probe listeners.
63    _deferred_event_types = []
64    # Override the normal SimObject::regProbeListeners method and
65    # register deferred event handlers.
66    def regProbeListeners(self):
67        for event_id, obj, name in self._deferred_event_types:
68            self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name)
69
70        self.getCCObject().regProbeListeners()
71
72    def addEventProbe(self, event_id, obj, *args):
73        """Add a probe-based event to the PMU if obj is not None."""
74
75        if obj is None:
76            return
77
78        for name in args:
79            self._deferred_event_types.append((event_id, obj, name))
80
81    def addArchEvents(self,
82                      cpu=None,
83                      itb=None, dtb=None,
84                      icache=None, dcache=None,
85                      l2cache=None):
86        """Add architected events to the PMU.
87
88        This method can be called multiple times with only a subset of
89        the keyword arguments set. This enables event registration in
90        configuration scripts to happen closer to the instantiation of
91        the instrumented objects (e.g., the memory system) instead of
92        a central point.
93
94        CPU events should also be registered once per CPU that is
95        sharing the PMU (e.g., when switching between CPU models).
96        """
97
98        bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \
99            else None
100
101        # 0x01: L1I_CACHE_REFILL
102        self.addEventProbe(0x02, itb, "Refills")
103        # 0x03: L2D_CACHE_REFILL
104        # 0x04: L1D_CACHE
105        self.addEventProbe(0x05, dtb, "Refills")
106        self.addEventProbe(0x06, cpu, "RetiredLoads")
107        self.addEventProbe(0x07, cpu, "RetiredStores")
108        self.addEventProbe(0x08, cpu, "RetiredInsts")
109        # 0x09: EXC_TAKEN
110        # 0x0A: EXC_RETURN
111        # 0x0B: CID_WRITE_RETIRED
112        self.addEventProbe(0x0C, cpu, "RetiredBranches")
113        # 0x0D: BR_IMMED_RETIRED
114        # 0x0E: BR_RETURN_RETIRED
115        # 0x0F: UNALIGEND_LDST_RETIRED
116        self.addEventProbe(0x10, bpred, "Misses")
117        self.addEventProbe(0x11, cpu, "Cycles")
118        self.addEventProbe(0x12, bpred, "Branches")
119        self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores")
120        # 0x14: L1I_CACHE
121        # 0x15: L1D_CACHE_WB
122        # 0x16: L2D_CACHE
123        # 0x17: L2D_CACHE_REFILL
124        # 0x18: L2D_CACHE_WB
125        # 0x19: BUS_ACCESS
126        # 0x1A: MEMORY_ERROR
127        # 0x1B: INST_SPEC
128        # 0x1C: TTBR_WRITE_RETIRED
129        # 0x1D: BUS_CYCLES
130        # 0x1E: CHAIN
131        # 0x1F: L1D_CACHE_ALLOCATE
132        # 0x20: L2D_CACHE_ALLOCATE
133
134    platform = Param.Platform(Parent.any, "Platform this device is part of.")
135    eventCounters = Param.Int(31, "Number of supported PMU counters")
136    pmuInterrupt = Param.Int(68, "PMU GIC interrupt number")
137