ArmPMU.py revision 12117
110461SAndreas.Sandberg@ARM.com# -*- mode:python -*- 212117Sjose.marinho@arm.com# Copyright (c) 2009-2014, 2017 ARM Limited 310461SAndreas.Sandberg@ARM.com# All rights reserved. 410461SAndreas.Sandberg@ARM.com# 510461SAndreas.Sandberg@ARM.com# The license below extends only to copyright in the software and shall 610461SAndreas.Sandberg@ARM.com# not be construed as granting a license to any other intellectual 710461SAndreas.Sandberg@ARM.com# property including but not limited to intellectual property relating 810461SAndreas.Sandberg@ARM.com# to a hardware implementation of the functionality of the software 910461SAndreas.Sandberg@ARM.com# licensed hereunder. You may use the software subject to the license 1010461SAndreas.Sandberg@ARM.com# terms below provided that you ensure that this notice is replicated 1110461SAndreas.Sandberg@ARM.com# unmodified and in its entirety in all distributions of the software, 1210461SAndreas.Sandberg@ARM.com# modified or unmodified, in source code or in binary form. 1310461SAndreas.Sandberg@ARM.com# 1410461SAndreas.Sandberg@ARM.com# Redistribution and use in source and binary forms, with or without 1510461SAndreas.Sandberg@ARM.com# modification, are permitted provided that the following conditions are 1610461SAndreas.Sandberg@ARM.com# met: redistributions of source code must retain the above copyright 1710461SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer; 1810461SAndreas.Sandberg@ARM.com# redistributions in binary form must reproduce the above copyright 1910461SAndreas.Sandberg@ARM.com# notice, this list of conditions and the following disclaimer in the 2010461SAndreas.Sandberg@ARM.com# documentation and/or other materials provided with the distribution; 2110461SAndreas.Sandberg@ARM.com# neither the name of the copyright holders nor the names of its 2210461SAndreas.Sandberg@ARM.com# contributors may be used to endorse or promote products derived from 2310461SAndreas.Sandberg@ARM.com# this software without specific prior written permission. 2410461SAndreas.Sandberg@ARM.com# 2510461SAndreas.Sandberg@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610461SAndreas.Sandberg@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710461SAndreas.Sandberg@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810461SAndreas.Sandberg@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910461SAndreas.Sandberg@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010461SAndreas.Sandberg@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110461SAndreas.Sandberg@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210461SAndreas.Sandberg@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310461SAndreas.Sandberg@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410461SAndreas.Sandberg@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510461SAndreas.Sandberg@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610461SAndreas.Sandberg@ARM.com# 3710461SAndreas.Sandberg@ARM.com# Authors: Matt Horsnell 3810461SAndreas.Sandberg@ARM.com# Andreas Sandberg 3910461SAndreas.Sandberg@ARM.com 4010461SAndreas.Sandberg@ARM.comfrom m5.defines import buildEnv 4111988Sandreas.sandberg@arm.comfrom m5.SimObject import * 4210461SAndreas.Sandberg@ARM.comfrom m5.params import * 4310461SAndreas.Sandberg@ARM.comfrom m5.params import isNullPointer 4410461SAndreas.Sandberg@ARM.comfrom m5.proxy import * 4510461SAndreas.Sandberg@ARM.com 4610461SAndreas.Sandberg@ARM.comclass ArmPMU(SimObject): 4710461SAndreas.Sandberg@ARM.com type = 'ArmPMU' 4810461SAndreas.Sandberg@ARM.com cxx_class = 'ArmISA::PMU' 4910461SAndreas.Sandberg@ARM.com cxx_header = 'arch/arm/pmu.hh' 5010461SAndreas.Sandberg@ARM.com 5111988Sandreas.sandberg@arm.com cxx_exports = [ 5211988Sandreas.sandberg@arm.com PyBindMethod("addEventProbe"), 5311988Sandreas.sandberg@arm.com ] 5410461SAndreas.Sandberg@ARM.com 5510461SAndreas.Sandberg@ARM.com # To prevent cycles in the configuration hierarchy, we don't keep 5610461SAndreas.Sandberg@ARM.com # a list of supported events as a configuration param. Instead, we 5710461SAndreas.Sandberg@ARM.com # keep them in a local list and register them using the 5810461SAndreas.Sandberg@ARM.com # addEventProbe interface when other SimObjects register their 5910461SAndreas.Sandberg@ARM.com # probe listeners. 6010461SAndreas.Sandberg@ARM.com _deferred_event_types = [] 6110461SAndreas.Sandberg@ARM.com # Override the normal SimObject::regProbeListeners method and 6210461SAndreas.Sandberg@ARM.com # register deferred event handlers. 6310461SAndreas.Sandberg@ARM.com def regProbeListeners(self): 6410461SAndreas.Sandberg@ARM.com for event_id, obj, name in self._deferred_event_types: 6510461SAndreas.Sandberg@ARM.com self.getCCObject().addEventProbe(event_id, obj.getCCObject(), name) 6610461SAndreas.Sandberg@ARM.com 6710461SAndreas.Sandberg@ARM.com self.getCCObject().regProbeListeners() 6810461SAndreas.Sandberg@ARM.com 6910461SAndreas.Sandberg@ARM.com def addEventProbe(self, event_id, obj, *args): 7010461SAndreas.Sandberg@ARM.com """Add a probe-based event to the PMU if obj is not None.""" 7110461SAndreas.Sandberg@ARM.com 7210461SAndreas.Sandberg@ARM.com if obj is None: 7310461SAndreas.Sandberg@ARM.com return 7410461SAndreas.Sandberg@ARM.com 7510461SAndreas.Sandberg@ARM.com for name in args: 7610461SAndreas.Sandberg@ARM.com self._deferred_event_types.append((event_id, obj, name)) 7710461SAndreas.Sandberg@ARM.com 7810465SAndreas.Sandberg@ARM.com def addArchEvents(self, 7910465SAndreas.Sandberg@ARM.com cpu=None, 8010465SAndreas.Sandberg@ARM.com itb=None, dtb=None, 8110465SAndreas.Sandberg@ARM.com icache=None, dcache=None, 8210465SAndreas.Sandberg@ARM.com l2cache=None): 8310465SAndreas.Sandberg@ARM.com """Add architected events to the PMU. 8410465SAndreas.Sandberg@ARM.com 8510465SAndreas.Sandberg@ARM.com This method can be called multiple times with only a subset of 8610465SAndreas.Sandberg@ARM.com the keyword arguments set. This enables event registration in 8710465SAndreas.Sandberg@ARM.com configuration scripts to happen closer to the instantiation of 8810465SAndreas.Sandberg@ARM.com the instrumented objects (e.g., the memory system) instead of 8910465SAndreas.Sandberg@ARM.com a central point. 9010465SAndreas.Sandberg@ARM.com 9110465SAndreas.Sandberg@ARM.com CPU events should also be registered once per CPU that is 9210465SAndreas.Sandberg@ARM.com sharing the PMU (e.g., when switching between CPU models). 9310465SAndreas.Sandberg@ARM.com """ 9410465SAndreas.Sandberg@ARM.com 9510465SAndreas.Sandberg@ARM.com bpred = cpu.branchPred if cpu and not isNullPointer(cpu.branchPred) \ 9610465SAndreas.Sandberg@ARM.com else None 9710465SAndreas.Sandberg@ARM.com 9810465SAndreas.Sandberg@ARM.com # 0x01: L1I_CACHE_REFILL 9910465SAndreas.Sandberg@ARM.com self.addEventProbe(0x02, itb, "Refills") 10012117Sjose.marinho@arm.com # 0x03: L1D_CACHE_REFILL 10110465SAndreas.Sandberg@ARM.com # 0x04: L1D_CACHE 10210465SAndreas.Sandberg@ARM.com self.addEventProbe(0x05, dtb, "Refills") 10310465SAndreas.Sandberg@ARM.com self.addEventProbe(0x06, cpu, "RetiredLoads") 10410465SAndreas.Sandberg@ARM.com self.addEventProbe(0x07, cpu, "RetiredStores") 10510465SAndreas.Sandberg@ARM.com self.addEventProbe(0x08, cpu, "RetiredInsts") 10610465SAndreas.Sandberg@ARM.com # 0x09: EXC_TAKEN 10710465SAndreas.Sandberg@ARM.com # 0x0A: EXC_RETURN 10810465SAndreas.Sandberg@ARM.com # 0x0B: CID_WRITE_RETIRED 10910465SAndreas.Sandberg@ARM.com self.addEventProbe(0x0C, cpu, "RetiredBranches") 11010465SAndreas.Sandberg@ARM.com # 0x0D: BR_IMMED_RETIRED 11110465SAndreas.Sandberg@ARM.com # 0x0E: BR_RETURN_RETIRED 11210465SAndreas.Sandberg@ARM.com # 0x0F: UNALIGEND_LDST_RETIRED 11310465SAndreas.Sandberg@ARM.com self.addEventProbe(0x10, bpred, "Misses") 11410465SAndreas.Sandberg@ARM.com self.addEventProbe(0x11, cpu, "Cycles") 11510465SAndreas.Sandberg@ARM.com self.addEventProbe(0x12, bpred, "Branches") 11610465SAndreas.Sandberg@ARM.com self.addEventProbe(0x13, cpu, "RetiredLoads", "RetiredStores") 11710465SAndreas.Sandberg@ARM.com # 0x14: L1I_CACHE 11810465SAndreas.Sandberg@ARM.com # 0x15: L1D_CACHE_WB 11910465SAndreas.Sandberg@ARM.com # 0x16: L2D_CACHE 12010465SAndreas.Sandberg@ARM.com # 0x17: L2D_CACHE_REFILL 12110465SAndreas.Sandberg@ARM.com # 0x18: L2D_CACHE_WB 12210465SAndreas.Sandberg@ARM.com # 0x19: BUS_ACCESS 12310465SAndreas.Sandberg@ARM.com # 0x1A: MEMORY_ERROR 12410465SAndreas.Sandberg@ARM.com # 0x1B: INST_SPEC 12510465SAndreas.Sandberg@ARM.com # 0x1C: TTBR_WRITE_RETIRED 12610465SAndreas.Sandberg@ARM.com # 0x1D: BUS_CYCLES 12710465SAndreas.Sandberg@ARM.com # 0x1E: CHAIN 12810465SAndreas.Sandberg@ARM.com # 0x1F: L1D_CACHE_ALLOCATE 12910465SAndreas.Sandberg@ARM.com # 0x20: L2D_CACHE_ALLOCATE 13012117Sjose.marinho@arm.com # 0x21: BR_RETIRED 13112117Sjose.marinho@arm.com # 0x22: BR_MIS_PRED_RETIRED 13212117Sjose.marinho@arm.com # 0x23: STALL_FRONTEND 13312117Sjose.marinho@arm.com # 0x24: STALL_BACKEND 13412117Sjose.marinho@arm.com # 0x25: L1D_TLB 13512117Sjose.marinho@arm.com # 0x26: L1I_TLB 13612117Sjose.marinho@arm.com # 0x27: L2I_CACHE 13712117Sjose.marinho@arm.com # 0x28: L2I_CACHE_REFILL 13812117Sjose.marinho@arm.com # 0x29: L3D_CACHE_ALLOCATE 13912117Sjose.marinho@arm.com # 0x2A: L3D_CACHE_REFILL 14012117Sjose.marinho@arm.com # 0x2B: L3D_CACHE 14112117Sjose.marinho@arm.com # 0x2C: L3D_CACHE_WB 14212117Sjose.marinho@arm.com # 0x2D: L2D_TLB_REFILL 14312117Sjose.marinho@arm.com # 0x2E: L2I_TLB_REFILL 14412117Sjose.marinho@arm.com # 0x2F: L2D_TLB 14512117Sjose.marinho@arm.com # 0x30: L2I_TLB 14610465SAndreas.Sandberg@ARM.com 14710461SAndreas.Sandberg@ARM.com platform = Param.Platform(Parent.any, "Platform this device is part of.") 14810461SAndreas.Sandberg@ARM.com eventCounters = Param.Int(31, "Number of supported PMU counters") 14910461SAndreas.Sandberg@ARM.com pmuInterrupt = Param.Int(68, "PMU GIC interrupt number") 150