ArmISA.py revision 14095:4f5d16d7cf45 
1# Copyright (c) 2012-2013, 2015-2019 ARM Limited
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35#
36# Authors: Andreas Sandberg
37#          Giacomo Gabrielli
38
39from m5.params import *
40from m5.proxy import *
41from m5.SimObject import SimObject
42
43from m5.objects.ArmPMU import ArmPMU
44from m5.objects.ArmSystem import SveVectorLength
45from m5.objects.ISACommon import VecRegRenameMode
46
47# Enum for DecoderFlavour
48class DecoderFlavour(Enum): vals = ['Generic']
49
50class ArmISA(SimObject):
51    type = 'ArmISA'
52    cxx_class = 'ArmISA::ISA'
53    cxx_header = "arch/arm/isa.hh"
54
55    system = Param.System(Parent.any, "System this ISA object belongs to")
56
57    pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
58    decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
59
60    midr = Param.UInt32(0x410fc0f0, "MIDR value")
61
62    # See section B4.1.89 - B4.1.92 of the ARM ARM
63    #  VMSAv7 support
64    id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
65    id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
66    # no HW access | WFI stalling | ISB and DSB |
67    # all TLB maintenance | no Harvard
68    id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
69    # SuperSec | Coherent TLB | Bcast Maint |
70    # BP Maint | Cache Maint Set/way | Cache Maint MVA
71    id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
72
73    # See section B4.1.84 of ARM ARM
74    # All values are latest for ARMv7-A profile
75    id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
76    id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
77    id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
78    id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
79    id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
80    id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
81
82    fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
83
84    # [31:0] is implementation defined
85    id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
86        "AArch64 Auxiliary Feature Register 0")
87    # Reserved for future expansion
88    id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
89        "AArch64 Auxiliary Feature Register 1")
90
91    # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
92    id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
93        "AArch64 Debug Feature Register 0")
94    # Reserved for future expansion
95    id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
96        "AArch64 Debug Feature Register 1")
97
98    # !CRC32 | !SHA2 | !SHA1 | !AES
99    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
100        "AArch64 Instruction Set Attribute Register 0")
101    # Reserved for future expansion
102    id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
103        "AArch64 Instruction Set Attribute Register 1")
104
105    # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
106    id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
107        "AArch64 Memory Model Feature Register 0")
108    # HPDS
109    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000001000,
110        "AArch64 Memory Model Feature Register 1")
111    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
112        "AArch64 Memory Model Feature Register 2")
113
114    # Any access (read/write) to an unimplemented
115    # Implementation Defined registers is not causing an Undefined Instruction.
116    # It is rather executed as a NOP.
117    impdef_nop = Param.Bool(False,
118        "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
119
120    # This is required because in SE mode a generic System SimObject is
121    # allocated, instead of an ArmSystem
122    sve_vl_se = Param.SveVectorLength(1,
123        "SVE vector length in quadwords (128-bit), SE-mode only")
124