ArmISA.py revision 13116:d3c3e2533928 
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35#
36# Authors: Andreas Sandberg
37#          Giacomo Gabrielli
38
39from m5.params import *
40from m5.proxy import *
41from m5.SimObject import SimObject
42
43from ArmPMU import ArmPMU
44from ISACommon import VecRegRenameMode
45
46# Enum for DecoderFlavour
47class DecoderFlavour(Enum): vals = ['Generic']
48
49class ArmISA(SimObject):
50    type = 'ArmISA'
51    cxx_class = 'ArmISA::ISA'
52    cxx_header = "arch/arm/isa.hh"
53
54    system = Param.System(Parent.any, "System this ISA object belongs to")
55
56    pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
57    decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
58
59    midr = Param.UInt32(0x410fc0f0, "MIDR value")
60
61    # See section B4.1.89 - B4.1.92 of the ARM ARM
62    #  VMSAv7 support
63    id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
64    id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
65    # no HW access | WFI stalling | ISB and DSB |
66    # all TLB maintenance | no Harvard
67    id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
68    # SuperSec | Coherent TLB | Bcast Maint |
69    # BP Maint | Cache Maint Set/way | Cache Maint MVA
70    id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
71
72    # See section B4.1.84 of ARM ARM
73    # All values are latest for ARMv7-A profile
74    id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
75    id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
76    id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
77    id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
78    id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
79    id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
80
81    fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
82
83    # [31:0] is implementation defined
84    id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
85        "AArch64 Auxiliary Feature Register 0")
86    # Reserved for future expansion
87    id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
88        "AArch64 Auxiliary Feature Register 1")
89
90    # Initial vector register rename mode
91    vecRegRenameMode = Param.VecRegRenameMode('Full',
92        "Initial rename mode for vecregs")
93
94    # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
95    id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
96        "AArch64 Debug Feature Register 0")
97    # Reserved for future expansion
98    id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
99        "AArch64 Debug Feature Register 1")
100
101    # !CRC32 | !SHA2 | !SHA1 | !AES
102    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
103        "AArch64 Instruction Set Attribute Register 0")
104    # Reserved for future expansion
105    id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
106        "AArch64 Instruction Set Attribute Register 1")
107
108    # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
109    id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
110        "AArch64 Memory Model Feature Register 0")
111    # Reserved for future expansion
112    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
113        "AArch64 Memory Model Feature Register 1")
114    id_aa64mmfr2_el1 = Param.UInt64(0x0000000000000000,
115        "AArch64 Memory Model Feature Register 2")
116
117    # Any access (read/write) to an unimplemented
118    # Implementation Defined registers is not causing an Undefined Instruction.
119    # It is rather executed as a NOP.
120    impdef_nop = Param.Bool(False,
121        "Any access to a MISCREG_IMPDEF_UNIMPL register is executed as NOP")
122