ArmISA.py revision 11773:9db50b9eacf5 
1# Copyright (c) 2012-2013, 2015-2016 ARM Limited
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35#
36# Authors: Andreas Sandberg
37#          Giacomo Gabrielli
38
39from m5.params import *
40from m5.proxy import *
41from m5.SimObject import SimObject
42
43from ArmPMU import ArmPMU
44
45# Enum for DecoderFlavour
46class DecoderFlavour(Enum): vals = ['Generic']
47
48class ArmISA(SimObject):
49    type = 'ArmISA'
50    cxx_class = 'ArmISA::ISA'
51    cxx_header = "arch/arm/isa.hh"
52
53    system = Param.System(Parent.any, "System this ISA object belongs to")
54
55    pmu = Param.ArmPMU(NULL, "Performance Monitoring Unit")
56    decoderFlavour = Param.DecoderFlavour('Generic', "Decoder flavour specification")
57
58    midr = Param.UInt32(0x410fc0f0, "MIDR value")
59
60    # See section B4.1.89 - B4.1.92 of the ARM ARM
61    #  VMSAv7 support
62    id_mmfr0 = Param.UInt32(0x10201103, "Memory Model Feature Register 0")
63    id_mmfr1 = Param.UInt32(0x00000000, "Memory Model Feature Register 1")
64    # no HW access | WFI stalling | ISB and DSB |
65    # all TLB maintenance | no Harvard
66    id_mmfr2 = Param.UInt32(0x01230000, "Memory Model Feature Register 2")
67    # SuperSec | Coherent TLB | Bcast Maint |
68    # BP Maint | Cache Maint Set/way | Cache Maint MVA
69    id_mmfr3 = Param.UInt32(0x02102211, "Memory Model Feature Register 3")
70
71    # See section B4.1.84 of ARM ARM
72    # All values are latest for ARMv7-A profile
73    id_isar0 = Param.UInt32(0x02101111, "Instruction Set Attribute Register 0")
74    id_isar1 = Param.UInt32(0x02112111, "Instruction Set Attribute Register 1")
75    id_isar2 = Param.UInt32(0x21232141, "Instruction Set Attribute Register 2")
76    id_isar3 = Param.UInt32(0x01112131, "Instruction Set Attribute Register 3")
77    id_isar4 = Param.UInt32(0x10010142, "Instruction Set Attribute Register 4")
78    id_isar5 = Param.UInt32(0x00000000, "Instruction Set Attribute Register 5")
79
80    fpsid = Param.UInt32(0x410430a0, "Floating-point System ID Register")
81
82    # [31:0] is implementation defined
83    id_aa64afr0_el1 = Param.UInt64(0x0000000000000000,
84        "AArch64 Auxiliary Feature Register 0")
85    # Reserved for future expansion
86    id_aa64afr1_el1 = Param.UInt64(0x0000000000000000,
87        "AArch64 Auxiliary Feature Register 1")
88
89    # 1 CTX CMPs | 2 WRPs | 2 BRPs | !PMU | !Trace | Debug v8-A
90    id_aa64dfr0_el1 = Param.UInt64(0x0000000000101006,
91        "AArch64 Debug Feature Register 0")
92    # Reserved for future expansion
93    id_aa64dfr1_el1 = Param.UInt64(0x0000000000000000,
94        "AArch64 Debug Feature Register 1")
95
96    # !CRC32 | !SHA2 | !SHA1 | !AES
97    id_aa64isar0_el1 = Param.UInt64(0x0000000000000000,
98        "AArch64 Instruction Set Attribute Register 0")
99    # Reserved for future expansion
100    id_aa64isar1_el1 = Param.UInt64(0x0000000000000000,
101        "AArch64 Instruction Set Attribute Register 1")
102
103    # 4K | 64K | !16K | !BigEndEL0 | !SNSMem | !BigEnd | 8b ASID | 40b PA
104    id_aa64mmfr0_el1 = Param.UInt64(0x0000000000f00002,
105        "AArch64 Memory Model Feature Register 0")
106    # Reserved for future expansion
107    id_aa64mmfr1_el1 = Param.UInt64(0x0000000000000000,
108        "AArch64 Memory Model Feature Register 1")
109