vtophys.cc revision 5569:baeee670d4ce
1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 * Ali Saidi 31 */ 32 33#include <string> 34 35#include "arch/alpha/ev5.hh" 36#include "arch/alpha/vtophys.hh" 37#include "base/chunk_generator.hh" 38#include "base/trace.hh" 39#include "cpu/thread_context.hh" 40#include "mem/vport.hh" 41 42using namespace std; 43 44namespace AlphaISA { 45 46PageTableEntry 47kernel_pte_lookup(FunctionalPort *mem, Addr ptbr, VAddr vaddr) 48{ 49 Addr level1_pte = ptbr + vaddr.level1(); 50 PageTableEntry level1 = mem->read<uint64_t>(level1_pte); 51 if (!level1.valid()) { 52 DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr); 53 return 0; 54 } 55 56 Addr level2_pte = level1.paddr() + vaddr.level2(); 57 PageTableEntry level2 = mem->read<uint64_t>(level2_pte); 58 if (!level2.valid()) { 59 DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr); 60 return 0; 61 } 62 63 Addr level3_pte = level2.paddr() + vaddr.level3(); 64 PageTableEntry level3 = mem->read<uint64_t>(level3_pte); 65 if (!level3.valid()) { 66 DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr); 67 return 0; 68 } 69 return level3; 70} 71 72Addr 73vtophys(Addr vaddr) 74{ 75 Addr paddr = 0; 76 if (IsUSeg(vaddr)) 77 DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr); 78 else if (IsK0Seg(vaddr)) 79 paddr = K0Seg2Phys(vaddr); 80 else 81 panic("vtophys: ptbr is not set on virtual lookup"); 82 83 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 84 85 return paddr; 86} 87 88Addr 89vtophys(ThreadContext *tc, Addr addr) 90{ 91 VAddr vaddr = addr; 92 Addr ptbr = tc->readMiscRegNoEffect(IPR_PALtemp20); 93 Addr paddr = 0; 94 //@todo Andrew couldn't remember why he commented some of this code 95 //so I put it back in. Perhaps something to do with gdb debugging? 96 if (PcPAL(vaddr) && (vaddr < PalMax)) { 97 paddr = vaddr & ~ULL(1); 98 } else { 99 if (IsK0Seg(vaddr)) { 100 paddr = K0Seg2Phys(vaddr); 101 } else if (!ptbr) { 102 paddr = vaddr; 103 } else { 104 PageTableEntry pte = 105 kernel_pte_lookup(tc->getPhysPort(), ptbr, vaddr); 106 if (pte.valid()) 107 paddr = pte.paddr() | vaddr.offset(); 108 } 109 } 110 111 112 DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr); 113 114 return paddr; 115} 116 117} // namespace AlphaISA 118