utility.hh revision 8780:89e0822462a1
16145Snate@binkert.org/* 26145Snate@binkert.org * Copyright (c) 2003-2005 The Regents of The University of Michigan 36145Snate@binkert.org * All rights reserved. 46145Snate@binkert.org * 56145Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66145Snate@binkert.org * modification, are permitted provided that the following conditions are 76145Snate@binkert.org * met: redistributions of source code must retain the above copyright 86145Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96145Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106145Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116145Snate@binkert.org * documentation and/or other materials provided with the distribution; 126145Snate@binkert.org * neither the name of the copyright holders nor the names of its 136145Snate@binkert.org * contributors may be used to endorse or promote products derived from 146145Snate@binkert.org * this software without specific prior written permission. 156145Snate@binkert.org * 166145Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176145Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186145Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196145Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206145Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216145Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226145Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236145Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246145Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256145Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276145Snate@binkert.org * 286145Snate@binkert.org * Authors: Nathan Binkert 297832Snate@binkert.org * Steve Reinhardt 307832Snate@binkert.org */ 318645Snilay@cs.wisc.edu 327054Snate@binkert.org#ifndef __ARCH_ALPHA_UTILITY_HH__ 338232Snate@binkert.org#define __ARCH_ALPHA_UTILITY_HH__ 3411092Snilay@cs.wisc.edu 358229Snate@binkert.org#include "arch/alpha/isa_traits.hh" 3610301Snilay@cs.wisc.edu#include "arch/alpha/registers.hh" 376154Snate@binkert.org#include "arch/alpha/types.hh" 3810895Snilay@cs.wisc.edu#include "base/misc.hh" 3911108Sdavid.hashe@amd.com#include "cpu/static_inst.hh" 406145Snate@binkert.org#include "cpu/thread_context.hh" 417055Snate@binkert.org#include "arch/alpha/ev5.hh" 427055Snate@binkert.org 436145Snate@binkert.orgnamespace AlphaISA { 446145Snate@binkert.org 456145Snate@binkert.orginline PCState 466145Snate@binkert.orgbuildRetPC(const PCState &curPC, const PCState &callPC) 476145Snate@binkert.org{ 4810895Snilay@cs.wisc.edu PCState retPC = callPC; 496145Snate@binkert.org retPC.advance(); 5010918Sbrandon.potter@amd.com return retPC; 519230Snilay@cs.wisc.edu} 5211092Snilay@cs.wisc.edu 5311092Snilay@cs.wisc.eduuint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp); 5411092Snilay@cs.wisc.edu 556145Snate@binkert.orginline bool 5610370Snilay@cs.wisc.eduinUserMode(ThreadContext *tc) 5710370Snilay@cs.wisc.edu{ 587832Snate@binkert.org return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 597054Snate@binkert.org} 6010311Snilay@cs.wisc.edu 617054Snate@binkert.org/** 628259SBrad.Beckmann@amd.com * Function to insure ISA semantics about 0 registers. 636145Snate@binkert.org * @param tc The thread context. 647054Snate@binkert.org */ 659863Snilay@cs.wisc.edutemplate <class TC> 666145Snate@binkert.orgvoid zeroRegisters(TC *tc); 676145Snate@binkert.org 687054Snate@binkert.org// Alpha IPR register accessors 6910370Snilay@cs.wisc.eduinline bool PcPAL(Addr addr) { return addr & 0x3; } 7010370Snilay@cs.wisc.eduinline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 716145Snate@binkert.org 727054Snate@binkert.org//////////////////////////////////////////////////////////////////////// 7310311Snilay@cs.wisc.edu// 7410370Snilay@cs.wisc.edu// Translation stuff 7510370Snilay@cs.wisc.edu// 7610370Snilay@cs.wisc.edu 7710311Snilay@cs.wisc.eduinline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 7810370Snilay@cs.wisc.edu 7910370Snilay@cs.wisc.edu// User Virtual 8010370Snilay@cs.wisc.eduinline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 8110370Snilay@cs.wisc.edu 8210311Snilay@cs.wisc.edu// Kernel Direct Mapped 8310311Snilay@cs.wisc.eduinline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 8410311Snilay@cs.wisc.eduinline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 8511092Snilay@cs.wisc.edu 8610311Snilay@cs.wisc.edu// Kernel Virtual 877054Snate@binkert.orginline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 886145Snate@binkert.org 896145Snate@binkert.orginline Addr 907054Snate@binkert.orgTruncPage(Addr addr) 9110311Snilay@cs.wisc.edu{ return addr & ~(PageBytes - 1); } 9210311Snilay@cs.wisc.edu 936145Snate@binkert.orginline Addr 9410370Snilay@cs.wisc.eduRoundPage(Addr addr) 9510370Snilay@cs.wisc.edu{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 9610370Snilay@cs.wisc.edu 9710311Snilay@cs.wisc.eduvoid initIPRs(ThreadContext *tc, int cpuId); 986145Snate@binkert.orgvoid initCPU(ThreadContext *tc, int cpuId); 9910311Snilay@cs.wisc.edu 10010311Snilay@cs.wisc.eduvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1019465Snilay@cs.wisc.edu 10210311Snilay@cs.wisc.eduvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 10310311Snilay@cs.wisc.edu 10410311Snilay@cs.wisc.eduvoid skipFunction(ThreadContext *tc); 10510311Snilay@cs.wisc.edu 10610311Snilay@cs.wisc.eduinline void 10710895Snilay@cs.wisc.eduadvancePC(PCState &pc, const StaticInstPtr inst) 10810311Snilay@cs.wisc.edu{ 10910311Snilay@cs.wisc.edu pc.advance(); 11010311Snilay@cs.wisc.edu} 11110311Snilay@cs.wisc.edu 11210311Snilay@cs.wisc.eduinline uint64_t 11310311Snilay@cs.wisc.edugetExecutingAsid(ThreadContext *tc) 11410919Sbrandon.potter@amd.com{ 11510311Snilay@cs.wisc.edu return DTB_ASN_ASN(tc->readMiscRegNoEffect(IPR_DTB_ASN)); 11610311Snilay@cs.wisc.edu} 11710311Snilay@cs.wisc.edu 11810311Snilay@cs.wisc.edu} // namespace AlphaISA 11910311Snilay@cs.wisc.edu 12010311Snilay@cs.wisc.edu#endif // __ARCH_ALPHA_UTILITY_HH__ 12110311Snilay@cs.wisc.edu