utility.hh revision 6330:786136379872
1955SN/A/* 2955SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 37816Ssteve.reinhardt@amd.com * All rights reserved. 45871Snate@binkert.org * 51762SN/A * Redistribution and use in source and binary forms, with or without 6955SN/A * modification, are permitted provided that the following conditions are 7955SN/A * met: redistributions of source code must retain the above copyright 8955SN/A * notice, this list of conditions and the following disclaimer; 9955SN/A * redistributions in binary form must reproduce the above copyright 10955SN/A * notice, this list of conditions and the following disclaimer in the 11955SN/A * documentation and/or other materials provided with the distribution; 12955SN/A * neither the name of the copyright holders nor the names of its 13955SN/A * contributors may be used to endorse or promote products derived from 14955SN/A * this software without specific prior written permission. 15955SN/A * 16955SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17955SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18955SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19955SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20955SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21955SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22955SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23955SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24955SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25955SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26955SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27955SN/A * 28955SN/A * Authors: Nathan Binkert 29955SN/A * Steve Reinhardt 302665Ssaidi@eecs.umich.edu */ 312665Ssaidi@eecs.umich.edu 325863Snate@binkert.org#ifndef __ARCH_ALPHA_UTILITY_HH__ 33955SN/A#define __ARCH_ALPHA_UTILITY_HH__ 34955SN/A 35955SN/A#include "arch/alpha/types.hh" 36955SN/A#include "arch/alpha/isa_traits.hh" 37955SN/A#include "arch/alpha/registers.hh" 388878Ssteve.reinhardt@amd.com#include "base/misc.hh" 392632Sstever@eecs.umich.edu#include "config/full_system.hh" 408878Ssteve.reinhardt@amd.com#include "cpu/thread_context.hh" 412632Sstever@eecs.umich.edu 42955SN/Anamespace AlphaISA { 438878Ssteve.reinhardt@amd.com 442632Sstever@eecs.umich.eduuint64_t getArgument(ThreadContext *tc, int number, bool fp); 452761Sstever@eecs.umich.edu 462632Sstever@eecs.umich.eduinline bool 472632Sstever@eecs.umich.eduinUserMode(ThreadContext *tc) 482632Sstever@eecs.umich.edu{ 492761Sstever@eecs.umich.edu return (tc->readMiscRegNoEffect(IPR_DTB_CM) & 0x18) != 0; 502761Sstever@eecs.umich.edu} 512761Sstever@eecs.umich.edu 528878Ssteve.reinhardt@amd.cominline bool 538878Ssteve.reinhardt@amd.comisCallerSaveIntegerRegister(unsigned int reg) 542761Sstever@eecs.umich.edu{ 552761Sstever@eecs.umich.edu panic("register classification not implemented"); 562761Sstever@eecs.umich.edu return (reg >= 1 && reg <= 8) || (reg >= 22 && reg <= 25) || reg == 27; 572761Sstever@eecs.umich.edu} 582761Sstever@eecs.umich.edu 598878Ssteve.reinhardt@amd.cominline bool 608878Ssteve.reinhardt@amd.comisCalleeSaveIntegerRegister(unsigned int reg) 612632Sstever@eecs.umich.edu{ 622632Sstever@eecs.umich.edu panic("register classification not implemented"); 638878Ssteve.reinhardt@amd.com return reg >= 9 && reg <= 15; 648878Ssteve.reinhardt@amd.com} 652632Sstever@eecs.umich.edu 66955SN/Ainline bool 67955SN/AisCallerSaveFloatRegister(unsigned int reg) 68955SN/A{ 695863Snate@binkert.org panic("register classification not implemented"); 705863Snate@binkert.org return false; 715863Snate@binkert.org} 725863Snate@binkert.org 735863Snate@binkert.orginline bool 745863Snate@binkert.orgisCalleeSaveFloatRegister(unsigned int reg) 755863Snate@binkert.org{ 765863Snate@binkert.org panic("register classification not implemented"); 775863Snate@binkert.org return false; 785863Snate@binkert.org} 795863Snate@binkert.org 808878Ssteve.reinhardt@amd.cominline Addr 815863Snate@binkert.orgalignAddress(const Addr &addr, unsigned int nbytes) 825863Snate@binkert.org{ 835863Snate@binkert.org return (addr & ~(nbytes - 1)); 845863Snate@binkert.org} 855863Snate@binkert.org 865863Snate@binkert.org// Instruction address compression hooks 875863Snate@binkert.orginline Addr 885863Snate@binkert.orgrealPCToFetchPC(const Addr &addr) 895863Snate@binkert.org{ 905863Snate@binkert.org return addr; 915863Snate@binkert.org} 925863Snate@binkert.org 935863Snate@binkert.orginline Addr 945863Snate@binkert.orgfetchPCToRealPC(const Addr &addr) 955863Snate@binkert.org{ 968878Ssteve.reinhardt@amd.com return addr; 975863Snate@binkert.org} 985863Snate@binkert.org 995863Snate@binkert.org// the size of "fetched" instructions (not necessarily the size 1006654Snate@binkert.org// of real instructions for PISA) 101955SN/Ainline size_t 1025396Ssaidi@eecs.umich.edufetchInstSize() 1035863Snate@binkert.org{ 1045863Snate@binkert.org return sizeof(MachInst); 1054202Sbinkertn@umich.edu} 1065863Snate@binkert.org 1075863Snate@binkert.orginline MachInst 1085863Snate@binkert.orgmakeRegisterCopy(int dest, int src) 1095863Snate@binkert.org{ 110955SN/A panic("makeRegisterCopy not implemented"); 1116654Snate@binkert.org return 0; 1125273Sstever@gmail.com} 1135871Snate@binkert.org 1145273Sstever@gmail.com/** 1156655Snate@binkert.org * Function to insure ISA semantics about 0 registers. 1168878Ssteve.reinhardt@amd.com * @param tc The thread context. 1176655Snate@binkert.org */ 1186655Snate@binkert.orgtemplate <class TC> 1199219Spower.jg@gmail.comvoid zeroRegisters(TC *tc); 1206655Snate@binkert.org 1215871Snate@binkert.org// Alpha IPR register accessors 1226654Snate@binkert.orginline bool PcPAL(Addr addr) { return addr & 0x3; } 1238947Sandreas.hansson@arm.cominline void startupCPU(ThreadContext *tc, int cpuId) { tc->activate(0); } 1245396Ssaidi@eecs.umich.edu 1258120Sgblack@eecs.umich.edu//////////////////////////////////////////////////////////////////////// 1268120Sgblack@eecs.umich.edu// 1278120Sgblack@eecs.umich.edu// Translation stuff 1288120Sgblack@eecs.umich.edu// 1298120Sgblack@eecs.umich.edu 1308120Sgblack@eecs.umich.eduinline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 1318120Sgblack@eecs.umich.edu 1328120Sgblack@eecs.umich.edu// User Virtual 1338879Ssteve.reinhardt@amd.cominline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 1348879Ssteve.reinhardt@amd.com 1358879Ssteve.reinhardt@amd.com// Kernel Direct Mapped 1368879Ssteve.reinhardt@amd.cominline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 1378879Ssteve.reinhardt@amd.cominline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 1388879Ssteve.reinhardt@amd.com 1398879Ssteve.reinhardt@amd.com// Kernel Virtual 1408879Ssteve.reinhardt@amd.cominline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 1418879Ssteve.reinhardt@amd.com 1428879Ssteve.reinhardt@amd.cominline Addr 1438879Ssteve.reinhardt@amd.comTruncPage(Addr addr) 1448879Ssteve.reinhardt@amd.com{ return addr & ~(PageBytes - 1); } 1458879Ssteve.reinhardt@amd.com 1468120Sgblack@eecs.umich.eduinline Addr 1478120Sgblack@eecs.umich.eduRoundPage(Addr addr) 1488120Sgblack@eecs.umich.edu{ return (addr + PageBytes - 1) & ~(PageBytes - 1); } 1498120Sgblack@eecs.umich.edu 1508120Sgblack@eecs.umich.eduvoid initIPRs(ThreadContext *tc, int cpuId); 1518120Sgblack@eecs.umich.edu#if FULL_SYSTEM 1528120Sgblack@eecs.umich.eduvoid initCPU(ThreadContext *tc, int cpuId); 1538120Sgblack@eecs.umich.edu 1548120Sgblack@eecs.umich.edu/** 1558120Sgblack@eecs.umich.edu * Function to check for and process any interrupts. 1568120Sgblack@eecs.umich.edu * @param tc The thread context. 1578120Sgblack@eecs.umich.edu */ 1588120Sgblack@eecs.umich.edutemplate <class TC> 1598120Sgblack@eecs.umich.eduvoid processInterrupts(TC *tc); 1608879Ssteve.reinhardt@amd.com#endif 1618879Ssteve.reinhardt@amd.com 1628879Ssteve.reinhardt@amd.comvoid copyRegs(ThreadContext *src, ThreadContext *dest); 1638879Ssteve.reinhardt@amd.com 1648879Ssteve.reinhardt@amd.comvoid copyMiscRegs(ThreadContext *src, ThreadContext *dest); 1658879Ssteve.reinhardt@amd.com 1668879Ssteve.reinhardt@amd.com} // namespace AlphaISA 1678879Ssteve.reinhardt@amd.com 1689227Sandreas.hansson@arm.com#endif // __ARCH_ALPHA_UTILITY_HH__ 1699227Sandreas.hansson@arm.com