utility.hh revision 4181:6edaeff44647
1/* 2 * Copyright (c) 2003-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Nathan Binkert 29 * Steve Reinhardt 30 */ 31 32#ifndef __ARCH_ALPHA_UTILITY_HH__ 33#define __ARCH_ALPHA_UTILITY_HH__ 34 35#include "config/full_system.hh" 36#include "arch/alpha/types.hh" 37#include "arch/alpha/isa_traits.hh" 38#include "arch/alpha/regfile.hh" 39#include "base/misc.hh" 40#include "cpu/thread_context.hh" 41 42namespace AlphaISA 43{ 44 45 static inline bool 46 inUserMode(ThreadContext *tc) 47 { 48 return (tc->readMiscRegNoEffect(AlphaISA::IPR_DTB_CM) & 0x18) != 0; 49 } 50 51 enum PredecodeResult { 52 MoreBytes = 1, 53 ExtMIReady = 2 54 }; 55 56 static inline unsigned int 57 predecode(ExtMachInst & ext_inst, Addr pc, MachInst inst, ThreadContext *) { 58 ext_inst = inst; 59#if FULL_SYSTEM 60 if (pc && 0x1) 61 ext_inst|=(static_cast<ExtMachInst>(pc & 0x1) << 32); 62#endif 63 return MoreBytes | ExtMIReady; 64 } 65 66 inline bool isCallerSaveIntegerRegister(unsigned int reg) { 67 panic("register classification not implemented"); 68 return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27); 69 } 70 71 inline bool isCalleeSaveIntegerRegister(unsigned int reg) { 72 panic("register classification not implemented"); 73 return (reg >= 9 && reg <= 15); 74 } 75 76 inline bool isCallerSaveFloatRegister(unsigned int reg) { 77 panic("register classification not implemented"); 78 return false; 79 } 80 81 inline bool isCalleeSaveFloatRegister(unsigned int reg) { 82 panic("register classification not implemented"); 83 return false; 84 } 85 86 inline Addr alignAddress(const Addr &addr, 87 unsigned int nbytes) { 88 return (addr & ~(nbytes - 1)); 89 } 90 91 // Instruction address compression hooks 92 inline Addr realPCToFetchPC(const Addr &addr) { 93 return addr; 94 } 95 96 inline Addr fetchPCToRealPC(const Addr &addr) { 97 return addr; 98 } 99 100 // the size of "fetched" instructions (not necessarily the size 101 // of real instructions for PISA) 102 inline size_t fetchInstSize() { 103 return sizeof(MachInst); 104 } 105 106 inline MachInst makeRegisterCopy(int dest, int src) { 107 panic("makeRegisterCopy not implemented"); 108 return 0; 109 } 110 111 // Machine operations 112 113 void saveMachineReg(AnyReg &savereg, const RegFile ®_file, 114 int regnum); 115 116 void restoreMachineReg(RegFile ®s, const AnyReg ®, 117 int regnum); 118 119 /** 120 * Function to insure ISA semantics about 0 registers. 121 * @param tc The thread context. 122 */ 123 template <class TC> 124 void zeroRegisters(TC *tc); 125 126 // Alpha IPR register accessors 127 inline bool PcPAL(Addr addr) { return addr & 0x3; } 128#if FULL_SYSTEM 129 130 //////////////////////////////////////////////////////////////////////// 131 // 132 // Translation stuff 133 // 134 135 inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; } 136 137 // User Virtual 138 inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; } 139 140 // Kernel Direct Mapped 141 inline bool IsK0Seg(Addr a) { return K0SegBase <= a && a <= K0SegEnd; } 142 inline Addr K0Seg2Phys(Addr addr) { return addr & ~K0SegBase; } 143 144 // Kernel Virtual 145 inline bool IsK1Seg(Addr a) { return K1SegBase <= a && a <= K1SegEnd; } 146 147 inline Addr 148 TruncPage(Addr addr) 149 { return addr & ~(PageBytes - 1); } 150 151 inline Addr 152 RoundPage(Addr addr) 153 { return (addr + PageBytes - 1) & ~(PageBytes - 1); } 154 155 void initCPU(ThreadContext *tc, int cpuId); 156 void initIPRs(ThreadContext *tc, int cpuId); 157 158 /** 159 * Function to check for and process any interrupts. 160 * @param tc The thread context. 161 */ 162 template <class TC> 163 void processInterrupts(TC *tc); 164#endif 165 166} // namespace AlphaISA 167 168#endif 169