utility.cc revision 7087
19793Sakash.bagdia@arm.com/* 29518SAndreas.Sandberg@ARM.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 39518SAndreas.Sandberg@ARM.com * All rights reserved. 49518SAndreas.Sandberg@ARM.com * 59518SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 69518SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 79518SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 89518SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 99518SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 109518SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 119518SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 129518SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 135347Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 147534Ssteve.reinhardt@amd.com * this software without specific prior written permission. 153395Shsul@eecs.umich.edu * 163395Shsul@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 173395Shsul@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 183395Shsul@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 193395Shsul@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 203395Shsul@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 213395Shsul@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 223395Shsul@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233395Shsul@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243395Shsul@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253395Shsul@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 263395Shsul@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273395Shsul@eecs.umich.edu * 283395Shsul@eecs.umich.edu * Authors: Nathan Binkert 293395Shsul@eecs.umich.edu * Ali Saidi 303395Shsul@eecs.umich.edu */ 313395Shsul@eecs.umich.edu 323395Shsul@eecs.umich.edu#include "arch/alpha/ev5.hh" 333395Shsul@eecs.umich.edu#include "arch/alpha/utility.hh" 343395Shsul@eecs.umich.edu 353395Shsul@eecs.umich.edu#if FULL_SYSTEM 363395Shsul@eecs.umich.edu#include "arch/alpha/vtophys.hh" 373395Shsul@eecs.umich.edu#include "mem/vport.hh" 383395Shsul@eecs.umich.edu#endif 393395Shsul@eecs.umich.edu 403395Shsul@eecs.umich.edunamespace AlphaISA { 413395Shsul@eecs.umich.edu 429457Svilanova@ac.upc.eduuint64_t 433395Shsul@eecs.umich.edugetArgument(ThreadContext *tc, int number, bool fp) 443509Shsul@eecs.umich.edu{ 456654Snate@binkert.org#if FULL_SYSTEM 469520SAndreas.Sandberg@ARM.com const int NumArgumentRegs = 6; 479665Sandreas.hansson@arm.com if (number < NumArgumentRegs) { 489520SAndreas.Sandberg@ARM.com if (fp) 493395Shsul@eecs.umich.edu return tc->readFloatRegBits(16 + number); 506654Snate@binkert.org else 513395Shsul@eecs.umich.edu return tc->readIntReg(16 + number); 526654Snate@binkert.org } else { 536654Snate@binkert.org Addr sp = tc->readIntReg(StackPointerReg); 546654Snate@binkert.org VirtualPort *vp = tc->getVirtPort(); 553395Shsul@eecs.umich.edu uint64_t arg = vp->read<uint64_t>(sp + 569139Snilay@cs.wisc.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 579520SAndreas.Sandberg@ARM.com return arg; 589520SAndreas.Sandberg@ARM.com } 599520SAndreas.Sandberg@ARM.com#else 609139Snilay@cs.wisc.edu panic("getArgument() is Full system only\n"); 613481Shsul@eecs.umich.edu M5_DUMMY_RETURN; 629139Snilay@cs.wisc.edu#endif 633481Shsul@eecs.umich.edu} 649139Snilay@cs.wisc.edu 659139Snilay@cs.wisc.eduvoid 669139Snilay@cs.wisc.educopyRegs(ThreadContext *src, ThreadContext *dest) 679139Snilay@cs.wisc.edu{ 689139Snilay@cs.wisc.edu // First loop through the integer registers. 699139Snilay@cs.wisc.edu for (int i = 0; i < NumIntRegs; ++i) 709139Snilay@cs.wisc.edu dest->setIntReg(i, src->readIntReg(i)); 719139Snilay@cs.wisc.edu 723481Shsul@eecs.umich.edu // Then loop through the floating point registers. 739518SAndreas.Sandberg@ARM.com for (int i = 0; i < NumFloatRegs; ++i) 749518SAndreas.Sandberg@ARM.com dest->setFloatRegBits(i, src->readFloatRegBits(i)); 759518SAndreas.Sandberg@ARM.com 763481Shsul@eecs.umich.edu // Copy misc. registers 779139Snilay@cs.wisc.edu copyMiscRegs(src, dest); 789139Snilay@cs.wisc.edu 793481Shsul@eecs.umich.edu // Lastly copy PC/NPC 809139Snilay@cs.wisc.edu dest->setPC(src->readPC()); 819139Snilay@cs.wisc.edu dest->setNextPC(src->readNextPC()); 829139Snilay@cs.wisc.edu} 839139Snilay@cs.wisc.edu 849139Snilay@cs.wisc.eduvoid 853481Shsul@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 863481Shsul@eecs.umich.edu{ 873481Shsul@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPCR, 889665Sandreas.hansson@arm.com src->readMiscRegNoEffect(MISCREG_FPCR)); 899665Sandreas.hansson@arm.com dest->setMiscRegNoEffect(MISCREG_UNIQ, 909665Sandreas.hansson@arm.com src->readMiscRegNoEffect(MISCREG_UNIQ)); 919665Sandreas.hansson@arm.com dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 929665Sandreas.hansson@arm.com src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 938919Snilay@cs.wisc.edu dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 948919Snilay@cs.wisc.edu src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 958919Snilay@cs.wisc.edu 9610159Sgedare@rtems.org copyIprs(src, dest); 9710159Sgedare@rtems.org} 988919Snilay@cs.wisc.edu 998919Snilay@cs.wisc.edu} // namespace AlphaISA 1008919Snilay@cs.wisc.edu 1018919Snilay@cs.wisc.edu