utility.cc revision 6379
14826Ssaidi@eecs.umich.edu/* 24826Ssaidi@eecs.umich.edu * Copyright (c) 2003-2005 The Regents of The University of Michigan 34826Ssaidi@eecs.umich.edu * All rights reserved. 44826Ssaidi@eecs.umich.edu * 54826Ssaidi@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 64826Ssaidi@eecs.umich.edu * modification, are permitted provided that the following conditions are 74826Ssaidi@eecs.umich.edu * met: redistributions of source code must retain the above copyright 84826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 94826Ssaidi@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 104826Ssaidi@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 114826Ssaidi@eecs.umich.edu * documentation and/or other materials provided with the distribution; 124826Ssaidi@eecs.umich.edu * neither the name of the copyright holders nor the names of its 134826Ssaidi@eecs.umich.edu * contributors may be used to endorse or promote products derived from 144826Ssaidi@eecs.umich.edu * this software without specific prior written permission. 154826Ssaidi@eecs.umich.edu * 164826Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 174826Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 184826Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 194826Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 204826Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 214826Ssaidi@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 224826Ssaidi@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 234826Ssaidi@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 244826Ssaidi@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 254826Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 264826Ssaidi@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 274826Ssaidi@eecs.umich.edu * 284826Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 294826Ssaidi@eecs.umich.edu * Ali Saidi 304826Ssaidi@eecs.umich.edu */ 314826Ssaidi@eecs.umich.edu 326330Sgblack@eecs.umich.edu#include "arch/alpha/ev5.hh" 334826Ssaidi@eecs.umich.edu#include "arch/alpha/utility.hh" 344826Ssaidi@eecs.umich.edu 354826Ssaidi@eecs.umich.edu#if FULL_SYSTEM 364826Ssaidi@eecs.umich.edu#include "arch/alpha/vtophys.hh" 374826Ssaidi@eecs.umich.edu#include "mem/vport.hh" 384826Ssaidi@eecs.umich.edu#endif 394826Ssaidi@eecs.umich.edu 405569Snate@binkert.orgnamespace AlphaISA { 414826Ssaidi@eecs.umich.edu 425569Snate@binkert.orguint64_t 435569Snate@binkert.orggetArgument(ThreadContext *tc, int number, bool fp) 444826Ssaidi@eecs.umich.edu{ 454826Ssaidi@eecs.umich.edu#if FULL_SYSTEM 465958Sgblack@eecs.umich.edu const int NumArgumentRegs = 6; 474826Ssaidi@eecs.umich.edu if (number < NumArgumentRegs) { 484826Ssaidi@eecs.umich.edu if (fp) 495958Sgblack@eecs.umich.edu return tc->readFloatRegBits(16 + number); 504826Ssaidi@eecs.umich.edu else 515958Sgblack@eecs.umich.edu return tc->readIntReg(16 + number); 524826Ssaidi@eecs.umich.edu } else { 534826Ssaidi@eecs.umich.edu Addr sp = tc->readIntReg(StackPointerReg); 545498Ssaidi@eecs.umich.edu VirtualPort *vp = tc->getVirtPort(); 554826Ssaidi@eecs.umich.edu uint64_t arg = vp->read<uint64_t>(sp + 564826Ssaidi@eecs.umich.edu (number-NumArgumentRegs) * sizeof(uint64_t)); 574826Ssaidi@eecs.umich.edu return arg; 584826Ssaidi@eecs.umich.edu } 594826Ssaidi@eecs.umich.edu#else 604826Ssaidi@eecs.umich.edu panic("getArgument() is Full system only\n"); 615569Snate@binkert.org M5_DUMMY_RETURN; 624826Ssaidi@eecs.umich.edu#endif 634826Ssaidi@eecs.umich.edu} 644826Ssaidi@eecs.umich.edu 656329Sgblack@eecs.umich.eduvoid 666329Sgblack@eecs.umich.educopyRegs(ThreadContext *src, ThreadContext *dest) 676329Sgblack@eecs.umich.edu{ 686329Sgblack@eecs.umich.edu // First loop through the integer registers. 696329Sgblack@eecs.umich.edu for (int i = 0; i < NumIntRegs; ++i) 706329Sgblack@eecs.umich.edu dest->setIntReg(i, src->readIntReg(i)); 716329Sgblack@eecs.umich.edu 726329Sgblack@eecs.umich.edu // Then loop through the floating point registers. 736329Sgblack@eecs.umich.edu for (int i = 0; i < NumFloatRegs; ++i) 746329Sgblack@eecs.umich.edu dest->setFloatRegBits(i, src->readFloatRegBits(i)); 756329Sgblack@eecs.umich.edu 766329Sgblack@eecs.umich.edu // Copy misc. registers 776329Sgblack@eecs.umich.edu copyMiscRegs(src, dest); 786329Sgblack@eecs.umich.edu 796329Sgblack@eecs.umich.edu // Lastly copy PC/NPC 806329Sgblack@eecs.umich.edu dest->setPC(src->readPC()); 816329Sgblack@eecs.umich.edu dest->setNextPC(src->readNextPC()); 826329Sgblack@eecs.umich.edu} 836329Sgblack@eecs.umich.edu 846329Sgblack@eecs.umich.eduvoid 856329Sgblack@eecs.umich.educopyMiscRegs(ThreadContext *src, ThreadContext *dest) 866329Sgblack@eecs.umich.edu{ 876329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_FPCR, 886329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_FPCR)); 896329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_UNIQ, 906329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_UNIQ)); 916329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_LOCKFLAG, 926329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_LOCKFLAG)); 936329Sgblack@eecs.umich.edu dest->setMiscRegNoEffect(MISCREG_LOCKADDR, 946329Sgblack@eecs.umich.edu src->readMiscRegNoEffect(MISCREG_LOCKADDR)); 956329Sgblack@eecs.umich.edu 966329Sgblack@eecs.umich.edu copyIprs(src, dest); 976329Sgblack@eecs.umich.edu} 986329Sgblack@eecs.umich.edu 994826Ssaidi@eecs.umich.edu} // namespace AlphaISA 1004826Ssaidi@eecs.umich.edu 101