types.hh revision 2665
12428SN/A/* 22428SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32428SN/A * All rights reserved. 42428SN/A * 52428SN/A * Redistribution and use in source and binary forms, with or without 62428SN/A * modification, are permitted provided that the following conditions are 72428SN/A * met: redistributions of source code must retain the above copyright 82428SN/A * notice, this list of conditions and the following disclaimer; 92428SN/A * redistributions in binary form must reproduce the above copyright 102428SN/A * notice, this list of conditions and the following disclaimer in the 112428SN/A * documentation and/or other materials provided with the distribution; 122428SN/A * neither the name of the copyright holders nor the names of its 132428SN/A * contributors may be used to endorse or promote products derived from 142428SN/A * this software without specific prior written permission. 152428SN/A * 162428SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172428SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182428SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192428SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202428SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212428SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222428SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232428SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242428SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252428SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262428SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * Authors: Nathan Binkert 292665Ssaidi@eecs.umich.edu * Steve Reinhardt 302428SN/A */ 312428SN/A 322428SN/A#ifndef __ARCH_ALPHA_TYPES_HH__ 332428SN/A#define __ARCH_ALPHA_TYPES_HH__ 342428SN/A 352428SN/A#include "sim/host.hh" 362428SN/A 372428SN/Anamespace AlphaISA 382428SN/A{ 392428SN/A 402428SN/A typedef uint32_t MachInst; 412428SN/A typedef uint64_t ExtMachInst; 422428SN/A typedef uint8_t RegIndex; 432428SN/A 442428SN/A typedef uint64_t IntReg; 452428SN/A 462428SN/A // floating point register file entry type 472455SN/A typedef double FloatReg; 482455SN/A typedef uint64_t FloatRegBits; 492428SN/A 502428SN/A // control register file contents 512428SN/A typedef uint64_t MiscReg; 522428SN/A 532428SN/A typedef union { 542428SN/A IntReg intreg; 552428SN/A FloatReg fpreg; 562428SN/A MiscReg ctrlreg; 572428SN/A } AnyReg; 582428SN/A 592428SN/A enum annotes { 602428SN/A ANNOTE_NONE = 0, 612428SN/A // An impossible number for instruction annotations 622428SN/A ITOUCH_ANNOTE = 0xffffffff, 632428SN/A }; 642428SN/A 652428SN/A} // namespace AlphaISA 662428SN/A 672428SN/A#endif 68