tlb.hh revision 5894 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ARCH_ALPHA_TLB_HH__
33#define __ARCH_ALPHA_TLB_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "arch/alpha/pagetable.hh"
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46#include "sim/faults.hh"
47#include "sim/tlb.hh"
48
49class ThreadContext;
50
51namespace AlphaISA {
52
53class TlbEntry;
54
55class TLB : public BaseTLB
56{
57  protected:
58    typedef std::multimap<Addr, int> PageTable;
59    PageTable lookupTable;  // Quick lookup into page table
60
61    TlbEntry *table;        // the Page Table
62    int size;               // TLB Size
63    int nlu;                // not last used entry (for replacement)
64
65    void nextnlu() { if (++nlu >= size) nlu = 0; }
66    TlbEntry *lookup(Addr vpn, uint8_t asn);
67
68  public:
69    typedef AlphaTLBParams Params;
70    TLB(const Params *p);
71    virtual ~TLB();
72
73    int getsize() const { return size; }
74
75    TlbEntry &index(bool advance = true);
76    void insert(Addr vaddr, TlbEntry &entry);
77
78    void flushAll();
79    void flushProcesses();
80    void flushAddr(Addr addr, uint8_t asn);
81
82    void
83    demapPage(Addr vaddr, uint64_t asn)
84    {
85        assert(asn < (1 << 8));
86        flushAddr(vaddr, asn);
87    }
88
89    // static helper functions... really EV5 VM traits
90    static bool
91    validVirtualAddress(Addr vaddr)
92    {
93        // unimplemented bits must be all 0 or all 1
94        Addr unimplBits = vaddr & VAddrUnImplMask;
95        return unimplBits == 0 || unimplBits == VAddrUnImplMask;
96    }
97
98    static Fault checkCacheability(RequestPtr &req, bool itb = false);
99
100    // Checkpointing
101    virtual void serialize(std::ostream &os);
102    virtual void unserialize(Checkpoint *cp, const std::string &section);
103
104    // Most recently used page table entries
105    TlbEntry *EntryCache[3];
106    inline void
107    flushCache()
108    {
109        memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
110    }
111
112    inline TlbEntry *
113    updateCache(TlbEntry *entry) {
114        EntryCache[2] = EntryCache[1];
115        EntryCache[1] = EntryCache[0];
116        EntryCache[0] = entry;
117        return entry;
118    }
119};
120
121class ITB : public TLB
122{
123  protected:
124    mutable Stats::Scalar<> hits;
125    mutable Stats::Scalar<> misses;
126    mutable Stats::Scalar<> acv;
127    mutable Stats::Formula accesses;
128
129  public:
130    typedef AlphaITBParams Params;
131    ITB(const Params *p);
132    virtual void regStats();
133
134    Fault translateAtomic(RequestPtr req, ThreadContext *tc);
135    void translateTiming(RequestPtr req, ThreadContext *tc,
136            Translation *translation);
137};
138
139class DTB : public TLB
140{
141  protected:
142    mutable Stats::Scalar<> read_hits;
143    mutable Stats::Scalar<> read_misses;
144    mutable Stats::Scalar<> read_acv;
145    mutable Stats::Scalar<> read_accesses;
146    mutable Stats::Scalar<> write_hits;
147    mutable Stats::Scalar<> write_misses;
148    mutable Stats::Scalar<> write_acv;
149    mutable Stats::Scalar<> write_accesses;
150    Stats::Formula hits;
151    Stats::Formula misses;
152    Stats::Formula acv;
153    Stats::Formula accesses;
154
155  public:
156    typedef AlphaDTBParams Params;
157    DTB(const Params *p);
158    virtual void regStats();
159
160    Fault translateAtomic(RequestPtr req, ThreadContext *tc, bool write);
161    void translateTiming(RequestPtr req, ThreadContext *tc,
162            Translation *translation, bool write);
163};
164
165} // namespace AlphaISA
166
167#endif // __ARCH_ALPHA_TLB_HH__
168