tlb.hh revision 5532 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 *          Steve Reinhardt
30 */
31
32#ifndef __ALPHA_MEMORY_HH__
33#define __ALPHA_MEMORY_HH__
34
35#include <map>
36
37#include "arch/alpha/ev5.hh"
38#include "arch/alpha/isa_traits.hh"
39#include "arch/alpha/pagetable.hh"
40#include "arch/alpha/utility.hh"
41#include "arch/alpha/vtophys.hh"
42#include "base/statistics.hh"
43#include "mem/request.hh"
44#include "params/AlphaDTB.hh"
45#include "params/AlphaITB.hh"
46#include "sim/faults.hh"
47#include "sim/tlb.hh"
48
49class ThreadContext;
50
51namespace AlphaISA
52{
53    class TlbEntry;
54
55    class TLB : public BaseTLB
56    {
57      protected:
58        typedef std::multimap<Addr, int> PageTable;
59        PageTable lookupTable;  // Quick lookup into page table
60
61        TlbEntry *table;        // the Page Table
62        int size;               // TLB Size
63        int nlu;                // not last used entry (for replacement)
64
65        void nextnlu() { if (++nlu >= size) nlu = 0; }
66        TlbEntry *lookup(Addr vpn, uint8_t asn);
67
68      public:
69        typedef AlphaTLBParams Params;
70        TLB(const Params *p);
71        virtual ~TLB();
72
73        int getsize() const { return size; }
74
75        TlbEntry &index(bool advance = true);
76        void insert(Addr vaddr, TlbEntry &entry);
77
78        void flushAll();
79        void flushProcesses();
80        void flushAddr(Addr addr, uint8_t asn);
81
82        void demapPage(Addr vaddr, uint64_t asn)
83        {
84            assert(asn < (1 << 8));
85            flushAddr(vaddr, asn);
86        }
87
88        // static helper functions... really EV5 VM traits
89        static bool validVirtualAddress(Addr vaddr) {
90            // unimplemented bits must be all 0 or all 1
91            Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
92            return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
93        }
94
95        static Fault checkCacheability(RequestPtr &req, bool itb = false);
96
97        // Checkpointing
98        virtual void serialize(std::ostream &os);
99        virtual void unserialize(Checkpoint *cp, const std::string &section);
100
101        // Most recently used page table entries
102        TlbEntry *EntryCache[3];
103        inline void flushCache()
104        {
105            memset(EntryCache, 0, 3 * sizeof(TlbEntry*));
106        }
107
108        inline TlbEntry* updateCache(TlbEntry *entry) {
109            EntryCache[2] = EntryCache[1];
110            EntryCache[1] = EntryCache[0];
111            EntryCache[0] = entry;
112            return entry;
113        }
114    };
115
116    class ITB : public TLB
117    {
118      protected:
119        mutable Stats::Scalar<> hits;
120        mutable Stats::Scalar<> misses;
121        mutable Stats::Scalar<> acv;
122        mutable Stats::Formula accesses;
123
124      public:
125        typedef AlphaITBParams Params;
126        ITB(const Params *p);
127        virtual void regStats();
128
129        Fault translate(RequestPtr &req, ThreadContext *tc);
130    };
131
132    class DTB : public TLB
133    {
134      protected:
135        mutable Stats::Scalar<> read_hits;
136        mutable Stats::Scalar<> read_misses;
137        mutable Stats::Scalar<> read_acv;
138        mutable Stats::Scalar<> read_accesses;
139        mutable Stats::Scalar<> write_hits;
140        mutable Stats::Scalar<> write_misses;
141        mutable Stats::Scalar<> write_acv;
142        mutable Stats::Scalar<> write_accesses;
143        Stats::Formula hits;
144        Stats::Formula misses;
145        Stats::Formula acv;
146        Stats::Formula accesses;
147
148      public:
149        typedef AlphaDTBParams Params;
150        DTB(const Params *p);
151        virtual void regStats();
152
153        Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
154    };
155}
156
157#endif // __ALPHA_MEMORY_HH__
158