tlb.hh revision 4967
1837SN/A/* 21762SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 3837SN/A * All rights reserved. 4837SN/A * 5837SN/A * Redistribution and use in source and binary forms, with or without 6837SN/A * modification, are permitted provided that the following conditions are 7837SN/A * met: redistributions of source code must retain the above copyright 8837SN/A * notice, this list of conditions and the following disclaimer; 9837SN/A * redistributions in binary form must reproduce the above copyright 10837SN/A * notice, this list of conditions and the following disclaimer in the 11837SN/A * documentation and/or other materials provided with the distribution; 12837SN/A * neither the name of the copyright holders nor the names of its 13837SN/A * contributors may be used to endorse or promote products derived from 14837SN/A * this software without specific prior written permission. 15837SN/A * 16837SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17837SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18837SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19837SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20837SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21837SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22837SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23837SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24837SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25837SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26837SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272665SN/A * 282760SN/A * Authors: Nathan Binkert 292760SN/A * Steve Reinhardt 30837SN/A */ 31837SN/A 321730SN/A#ifndef __ALPHA_MEMORY_HH__ 33837SN/A#define __ALPHA_MEMORY_HH__ 34837SN/A 35837SN/A#include <map> 36837SN/A 3711263Sandreas.sandberg@arm.com#include "arch/alpha/ev5.hh" 3811263Sandreas.sandberg@arm.com#include "arch/alpha/isa_traits.hh" 39837SN/A#include "arch/alpha/pagetable.hh" 401114SN/A#include "arch/alpha/utility.hh" 411027SN/A#include "arch/alpha/vtophys.hh" 4211263Sandreas.sandberg@arm.com#include "base/statistics.hh" 4311263Sandreas.sandberg@arm.com#include "mem/request.hh" 4411263Sandreas.sandberg@arm.com#include "sim/faults.hh" 4511263Sandreas.sandberg@arm.com#include "sim/sim_object.hh" 4611263Sandreas.sandberg@arm.com 474762SN/Aclass ThreadContext; 481027SN/A 49837SN/Anamespace AlphaISA 501843SN/A{ 511843SN/A class PTE; 521843SN/A 531843SN/A class TLB : public SimObject 541843SN/A { 551843SN/A protected: 561843SN/A typedef std::multimap<Addr, int> PageTable; 571843SN/A PageTable lookupTable; // Quick lookup into page table 581843SN/A 591843SN/A PTE *table; // the Page Table 601843SN/A int size; // TLB Size 61837SN/A int nlu; // not last used entry (for replacement) 62837SN/A 63837SN/A void nextnlu() { if (++nlu >= size) nlu = 0; } 64837SN/A PTE *lookup(Addr vpn, uint8_t asn); 655543SN/A 665543SN/A public: 675543SN/A TLB(const std::string &name, int size); 685543SN/A virtual ~TLB(); 69837SN/A 70837SN/A int getsize() const { return size; } 71837SN/A 72837SN/A PTE &index(bool advance = true); 73837SN/A void insert(Addr vaddr, PTE &pte); 74837SN/A 75837SN/A void flushAll(); 76837SN/A void flushProcesses(); 77837SN/A void flushAddr(Addr addr, uint8_t asn); 78837SN/A 79837SN/A // static helper functions... really EV5 VM traits 80837SN/A static bool validVirtualAddress(Addr vaddr) { 81837SN/A // unimplemented bits must be all 0 or all 1 82837SN/A Addr unimplBits = vaddr & EV5::VAddrUnImplMask; 83837SN/A return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask); 84837SN/A } 851843SN/A 861843SN/A static Fault checkCacheability(RequestPtr &req); 87837SN/A 88837SN/A // Checkpointing 89837SN/A virtual void serialize(std::ostream &os); 90837SN/A virtual void unserialize(Checkpoint *cp, const std::string §ion); 91837SN/A 92837SN/A // Most recently used page table entries 93837SN/A PTE *PTECache[3]; 94837SN/A inline void flushCache() { memset(PTECache, 0, 3 * sizeof(PTE*)); } 95837SN/A inline PTE* updateCache(PTE *pte) { 96837SN/A PTECache[2] = PTECache[1]; 97837SN/A PTECache[1] = PTECache[0]; 98837SN/A PTECache[0] = pte; 99854SN/A return pte; 100837SN/A } 101854SN/A }; 1021027SN/A 1031027SN/A class ITB : public TLB 1041027SN/A { 1051027SN/A protected: 1061114SN/A mutable Stats::Scalar<> hits; 1071843SN/A mutable Stats::Scalar<> misses; 1081843SN/A mutable Stats::Scalar<> acv; 1091843SN/A mutable Stats::Formula accesses; 1101843SN/A 1111843SN/A public: 1121843SN/A ITB(const std::string &name, int size); 113837SN/A virtual void regStats(); 114837SN/A 115879SN/A Fault translate(RequestPtr &req, ThreadContext *tc); 1162566SN/A }; 117837SN/A 118837SN/A class DTB : public TLB 1191817SN/A { 120837SN/A protected: 1219339SN/A mutable Stats::Scalar<> read_hits; 122837SN/A mutable Stats::Scalar<> read_misses; 123854SN/A mutable Stats::Scalar<> read_acv; 124854SN/A mutable Stats::Scalar<> read_accesses; 125854SN/A mutable Stats::Scalar<> write_hits; 126854SN/A mutable Stats::Scalar<> write_misses; 127854SN/A mutable Stats::Scalar<> write_acv; 128854SN/A mutable Stats::Scalar<> write_accesses; 129854SN/A Stats::Formula hits; 130854SN/A Stats::Formula misses; 131854SN/A Stats::Formula acv; 132854SN/A Stats::Formula accesses; 133854SN/A 134854SN/A public: 135854SN/A DTB(const std::string &name, int size); 136854SN/A virtual void regStats(); 137854SN/A 138854SN/A Fault translate(RequestPtr &req, ThreadContext *tc, bool write); 139854SN/A }; 140854SN/A} 141854SN/A 142854SN/A#endif // __ALPHA_MEMORY_HH__ 143854SN/A