tlb.hh revision 2517 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ALPHA_MEMORY_HH__
30#define __ALPHA_MEMORY_HH__
31
32#include <map>
33
34#include "arch/alpha/ev5.hh"
35#include "arch/alpha/isa_traits.hh"
36#include "arch/alpha/faults.hh"
37#include "base/statistics.hh"
38#include "mem/request.hh"
39#include "sim/sim_object.hh"
40
41class ExecContext;
42
43class AlphaTLB : public SimObject
44{
45  protected:
46    typedef std::multimap<Addr, int> PageTable;
47    PageTable lookupTable;	// Quick lookup into page table
48
49    AlphaISA::PTE *table;	// the Page Table
50    int size;			// TLB Size
51    int nlu;			// not last used entry (for replacement)
52
53    void nextnlu() { if (++nlu >= size) nlu = 0; }
54    AlphaISA::PTE *lookup(Addr vpn, uint8_t asn) const;
55
56  public:
57    AlphaTLB(const std::string &name, int size);
58    virtual ~AlphaTLB();
59
60    int getsize() const { return size; }
61
62    AlphaISA::PTE &index(bool advance = true);
63    void insert(Addr vaddr, AlphaISA::PTE &pte);
64
65    void flushAll();
66    void flushProcesses();
67    void flushAddr(Addr addr, uint8_t asn);
68
69    // static helper functions... really EV5 VM traits
70    static bool validVirtualAddress(Addr vaddr) {
71        // unimplemented bits must be all 0 or all 1
72        Addr unimplBits = vaddr & EV5::VAddrUnImplMask;
73        return (unimplBits == 0) || (unimplBits == EV5::VAddrUnImplMask);
74    }
75
76    static void checkCacheability(CpuRequestPtr &req);
77
78    // Checkpointing
79    virtual void serialize(std::ostream &os);
80    virtual void unserialize(Checkpoint *cp, const std::string &section);
81};
82
83class AlphaITB : public AlphaTLB
84{
85  protected:
86    mutable Stats::Scalar<> hits;
87    mutable Stats::Scalar<> misses;
88    mutable Stats::Scalar<> acv;
89    mutable Stats::Formula accesses;
90
91  public:
92    AlphaITB(const std::string &name, int size);
93    virtual void regStats();
94
95    Fault translate(CpuRequestPtr &req) const;
96};
97
98class AlphaDTB : public AlphaTLB
99{
100  protected:
101    mutable Stats::Scalar<> read_hits;
102    mutable Stats::Scalar<> read_misses;
103    mutable Stats::Scalar<> read_acv;
104    mutable Stats::Scalar<> read_accesses;
105    mutable Stats::Scalar<> write_hits;
106    mutable Stats::Scalar<> write_misses;
107    mutable Stats::Scalar<> write_acv;
108    mutable Stats::Scalar<> write_accesses;
109    Stats::Formula hits;
110    Stats::Formula misses;
111    Stats::Formula acv;
112    Stats::Formula accesses;
113
114  public:
115    AlphaDTB(const std::string &name, int size);
116    virtual void regStats();
117
118    Fault translate(CpuRequestPtr &req, bool write) const;
119};
120
121#endif // __ALPHA_MEMORY_HH__
122